| 1 |
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| 2 | #ifndef _ASM_X86_SYNC_CORE_H
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| 3 | #define _ASM_X86_SYNC_CORE_H
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| 4 |
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| 5 | #include <linux/preempt.h>
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| 6 | #include <asm/processor.h>
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| 7 | #include <asm/cpufeature.h>
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| 8 | #include <asm/special_insns.h>
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| 9 |
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| 10 | #ifdef CONFIG_X86_32
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| 11 | static __always_inline void iret_to_self(void)
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| 12 | {
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| 13 | asm volatile (
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| 14 | "pushfl\n\t"
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| 15 | "pushl %%cs\n\t"
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| 16 | "pushl $1f\n\t"
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| 17 | "iret\n\t"
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| 18 | "1:"
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| 19 | : ASM_CALL_CONSTRAINT : : "memory");
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| 20 | }
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| 21 | #else
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| 22 | static __always_inline void iret_to_self(void)
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| 23 | {
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| 24 | unsigned int tmp;
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| 25 |
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| 26 | asm volatile (
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| 27 | "mov %%ss, %0\n\t"
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| 28 | "pushq %q0\n\t"
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| 29 | "pushq %%rsp\n\t"
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| 30 | "addq $8, (%%rsp)\n\t"
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| 31 | "pushfq\n\t"
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| 32 | "mov %%cs, %0\n\t"
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| 33 | "pushq %q0\n\t"
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| 34 | "pushq $1f\n\t"
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| 35 | "iretq\n\t"
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| 36 | "1:"
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| 37 | : "=&r" (tmp), ASM_CALL_CONSTRAINT : : "cc", "memory");
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| 38 | }
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| 39 | #endif
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| 40 |
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| 41 | |
| 42 | * This function forces the icache and prefetched instruction stream to
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| 43 | * catch up with reality in two very specific cases:
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| 44 | *
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| 45 | * a) Text was modified using one virtual address and is about to be executed
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| 46 | * from the same physical page at a different virtual address.
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| 47 | *
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| 48 | * b) Text was modified on a different CPU, may subsequently be
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| 49 | * executed on this CPU, and you want to make sure the new version
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| 50 | * gets executed. This generally means you're calling this in an IPI.
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| 51 | *
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| 52 | * If you're calling this for a different reason, you're probably doing
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| 53 | * it wrong.
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| 54 | *
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| 55 | * Like all of Linux's memory ordering operations, this is a
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| 56 | * compiler barrier as well.
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| 57 |
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| 58 | static __always_inline void sync_core(void)
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| 59 | {
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| 60 | |
| 61 | * The SERIALIZE instruction is the most straightforward way to
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| 62 | * do this, but it is not universally available.
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| 63 |
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| 64 | if (cpu_feature_enabled(X86_FEATURE_SERIALIZE)) {
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| 65 | serialize();
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| 66 | return;
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| 67 | }
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| 68 |
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| 69 | |
| 70 | * For all other processors, there are quite a few ways to do this.
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| 71 | * IRET-to-self is nice because it works on every CPU, at any CPL
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| 72 | * (so it's compatible with paravirtualization), and it never exits
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| 73 | * to a hypervisor. The only downsides are that it's a bit slow
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| 74 | * (it seems to be a bit more than 2x slower than the fastest
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| 75 | * options) and that it unmasks NMIs. The "push %cs" is needed,
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| 76 | * because in paravirtual environments __KERNEL_CS may not be a
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| 77 | * valid CS value when we do IRET directly.
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| 78 | *
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| 79 | * In case NMI unmasking or performance ever becomes a problem,
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| 80 | * the next best option appears to be MOV-to-CR2 and an
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| 81 | * unconditional jump. That sequence also works on all CPUs,
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| 82 | * but it will fault at CPL3 (i.e. Xen PV).
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| 83 | *
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| 84 | * CPUID is the conventional way, but it's nasty: it doesn't
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| 85 | * exist on some 486-like CPUs, and it usually exits to a
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| 86 | * hypervisor.
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| 87 |
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| 88 | iret_to_self();
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| 89 | }
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| 90 |
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| 91 | |
| 92 | * Ensure that a core serializing instruction is issued before returning
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| 93 | * to user-mode. x86 implements return to user-space through sysexit,
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| 94 | * sysrel, and sysretq, which are not core serializing.
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| 95 |
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| 96 | static inline void sync_core_before_usermode(void)
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| 97 | {
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| 98 |
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| 99 | if (cpu_feature_enabled(X86_FEATURE_PTI))
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| 100 | return;
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| 101 |
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| 102 | |
| 103 | * Even if we're in an interrupt, we might reschedule before returning,
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| 104 | * in which case we could switch to a different thread in the same mm
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| 105 | * and return using SYSRET or SYSEXIT. Instead of trying to keep
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| 106 | * track of our need to sync the core, just sync right away.
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| 107 |
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| 108 | sync_core();
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| 109 | }
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| 110 |
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| 111 | #endif
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