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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * AMD CPU Microcode Update Driver for Linux
4 *
5 * This driver allows to upgrade microcode on F10h AMD
6 * CPUs and later.
7 *
8 * Copyright (C) 2008-2011 Advanced Micro Devices Inc.
9 * 2013-2018 Borislav Petkov <[email protected]>
10 *
11 * Author: Peter Oruba <[email protected]>
12 *
13 * Based on work by:
14 * Tigran Aivazian <[email protected]>
15 *
16 * early loader:
17 * Copyright (C) 2013 Advanced Micro Devices, Inc.
18 *
19 * Author: Jacob Shin <[email protected]>
20 * Fixes: Borislav Petkov <[email protected]>
21 */
22#define pr_fmt(fmt) "microcode: " fmt
23
24#include <linux/earlycpio.h>
25#include <linux/firmware.h>
26#include <linux/bsearch.h>
27#include <linux/uaccess.h>
28#include <linux/vmalloc.h>
29#include <linux/initrd.h>
30#include <linux/kernel.h>
31#include <linux/pci.h>
32
33#include <crypto/sha2.h>
34
35#include <asm/microcode.h>
36#include <asm/processor.h>
37#include <asm/cpuid/api.h>
38#include <asm/cmdline.h>
39#include <asm/setup.h>
40#include <asm/cpu.h>
41#include <asm/msr.h>
42#include <asm/tlb.h>
43
44#include "internal.h"
45
46struct ucode_patch {
47 struct list_head plist;
48 void *data;
49 unsigned int size;
50 u32 patch_id;
51 u16 equiv_cpu;
52};
53
54static LIST_HEAD(microcode_cache);
55
56#define UCODE_MAGIC 0x00414d44
57#define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000
58#define UCODE_UCODE_TYPE 0x00000001
59
60#define SECTION_HDR_SIZE 8
61#define CONTAINER_HDR_SZ 12
62
63struct equiv_cpu_entry {
64 u32 installed_cpu;
65 u32 fixed_errata_mask;
66 u32 fixed_errata_compare;
67 u16 equiv_cpu;
68 u16 res;
69} __packed;
70
71struct microcode_header_amd {
72 u32 data_code;
73 u32 patch_id;
74 u16 mc_patch_data_id;
75 u8 mc_patch_data_len;
76 u8 init_flag;
77 u32 mc_patch_data_checksum;
78 u32 nb_dev_id;
79 u32 sb_dev_id;
80 u16 processor_rev_id;
81 u8 nb_rev_id;
82 u8 sb_rev_id;
83 u8 bios_api_rev;
84 u8 reserved1[3];
85 u32 match_reg[8];
86} __packed;
87
88struct microcode_amd {
89 struct microcode_header_amd hdr;
90 unsigned int mpb[];
91};
92
93static struct equiv_cpu_table {
94 unsigned int num_entries;
95 struct equiv_cpu_entry *entry;
96} equiv_table;
97
98union zen_patch_rev {
99 struct {
100 __u32 rev : 8,
101 stepping : 4,
102 model : 4,
103 __reserved : 4,
104 ext_model : 4,
105 ext_fam : 8;
106 };
107 __u32 ucode_rev;
108};
109
110union cpuid_1_eax {
111 struct {
112 __u32 stepping : 4,
113 model : 4,
114 family : 4,
115 __reserved0 : 4,
116 ext_model : 4,
117 ext_fam : 8,
118 __reserved1 : 4;
119 };
120 __u32 full;
121};
122
123/*
124 * This points to the current valid container of microcode patches which we will
125 * save from the initrd/builtin before jettisoning its contents. @mc is the
126 * microcode patch we found to match.
127 */
128struct cont_desc {
129 struct microcode_amd *mc;
130 u32 psize;
131 u8 *data;
132 size_t size;
133};
134
135/*
136 * Microcode patch container file is prepended to the initrd in cpio
137 * format. See Documentation/arch/x86/microcode.rst
138 */
139static const char ucode_path[] = "kernel/x86/microcode/AuthenticAMD.bin";
140
141/*
142 * This is CPUID(1).EAX on the BSP. It is used in two ways:
143 *
144 * 1. To ignore the equivalence table on Zen1 and newer.
145 *
146 * 2. To match which patches to load because the patch revision ID
147 * already contains the f/m/s for which the microcode is destined
148 * for.
149 */
150static u32 bsp_cpuid_1_eax __ro_after_init;
151
152static bool sha_check = true;
153
154struct patch_digest {
155 u32 patch_id;
156 u8 sha256[SHA256_DIGEST_SIZE];
157};
158
159#include "amd_shas.c"
160
161static int cmp_id(const void *key, const void *elem)
162{
163 struct patch_digest *pd = (struct patch_digest *)elem;
164 u32 patch_id = *(u32 *)key;
165
166 if (patch_id == pd->patch_id)
167 return 0;
168 else if (patch_id < pd->patch_id)
169 return -1;
170 else
171 return 1;
172}
173
174static u32 cpuid_to_ucode_rev(unsigned int val)
175{
176 union zen_patch_rev p = {};
177 union cpuid_1_eax c;
178
179 c.full = val;
180
181 p.stepping = c.stepping;
182 p.model = c.model;
183 p.ext_model = c.ext_model;
184 p.ext_fam = c.ext_fam;
185
186 return p.ucode_rev;
187}
188
189static u32 get_cutoff_revision(u32 rev)
190{
191 switch (rev >> 8) {
192 case 0x80012: return 0x8001277; break;
193 case 0x80082: return 0x800820f; break;
194 case 0x83010: return 0x830107c; break;
195 case 0x86001: return 0x860010e; break;
196 case 0x86081: return 0x8608108; break;
197 case 0x87010: return 0x8701034; break;
198 case 0x8a000: return 0x8a0000a; break;
199 case 0xa0010: return 0xa00107a; break;
200 case 0xa0011: return 0xa0011da; break;
201 case 0xa0012: return 0xa001243; break;
202 case 0xa0082: return 0xa00820e; break;
203 case 0xa1011: return 0xa101153; break;
204 case 0xa1012: return 0xa10124e; break;
205 case 0xa1081: return 0xa108109; break;
206 case 0xa2010: return 0xa20102f; break;
207 case 0xa2012: return 0xa201212; break;
208 case 0xa4041: return 0xa404109; break;
209 case 0xa5000: return 0xa500013; break;
210 case 0xa6012: return 0xa60120a; break;
211 case 0xa7041: return 0xa704109; break;
212 case 0xa7052: return 0xa705208; break;
213 case 0xa7080: return 0xa708009; break;
214 case 0xa70c0: return 0xa70C009; break;
215 case 0xaa001: return 0xaa00116; break;
216 case 0xaa002: return 0xaa00218; break;
217 case 0xb0021: return 0xb002146; break;
218 case 0xb0081: return 0xb008111; break;
219 case 0xb1010: return 0xb101046; break;
220 case 0xb2040: return 0xb204031; break;
221 case 0xb4040: return 0xb404031; break;
222 case 0xb4041: return 0xb404101; break;
223 case 0xb6000: return 0xb600031; break;
224 case 0xb6080: return 0xb608031; break;
225 case 0xb7000: return 0xb700031; break;
226 default: break;
227
228 }
229 return 0;
230}
231
232static bool need_sha_check(u32 cur_rev)
233{
234 u32 cutoff;
235
236 cutoff = get_cutoff_revision(cur_rev);
237 if (cutoff)
238 return cur_rev <= cutoff;
239
240 pr_info("You should not be seeing this. Please send the following couple of lines to x86-<at>-kernel.org\n");
241 pr_info("CPUID(1).EAX: 0x%x, current revision: 0x%x\n", bsp_cpuid_1_eax, cur_rev);
242 return true;
243}
244
245static bool cpu_has_entrysign(void)
246{
247 unsigned int fam = x86_family(bsp_cpuid_1_eax);
248 unsigned int model = x86_model(bsp_cpuid_1_eax);
249
250 if (fam == 0x17 || fam == 0x19)
251 return true;
252
253 if (fam == 0x1a) {
254 if (model <= 0x2f ||
255 (0x40 <= model && model <= 0x4f) ||
256 (0x60 <= model && model <= 0x7f))
257 return true;
258 }
259
260 return false;
261}
262
263static bool verify_sha256_digest(u32 patch_id, u32 cur_rev, const u8 *data, unsigned int len)
264{
265 struct patch_digest *pd = NULL;
266 u8 digest[SHA256_DIGEST_SIZE];
267 int i;
268
269 if (!cpu_has_entrysign())
270 return true;
271
272 if (!need_sha_check(cur_rev))
273 return true;
274
275 if (!sha_check)
276 return true;
277
278 pd = bsearch(&patch_id, phashes, ARRAY_SIZE(phashes), sizeof(struct patch_digest), cmp_id);
279 if (!pd) {
280 pr_err("No sha256 digest for patch ID: 0x%x found\n", patch_id);
281 return false;
282 }
283
284 sha256(data, len, digest);
285
286 if (memcmp(digest, pd->sha256, sizeof(digest))) {
287 pr_err("Patch 0x%x SHA256 digest mismatch!\n", patch_id);
288
289 for (i = 0; i < SHA256_DIGEST_SIZE; i++)
290 pr_cont("0x%x ", digest[i]);
291 pr_info("\n");
292
293 return false;
294 }
295
296 return true;
297}
298
299static union cpuid_1_eax ucode_rev_to_cpuid(unsigned int val)
300{
301 union zen_patch_rev p;
302 union cpuid_1_eax c;
303
304 p.ucode_rev = val;
305 c.full = 0;
306
307 c.stepping = p.stepping;
308 c.model = p.model;
309 c.ext_model = p.ext_model;
310 c.family = 0xf;
311 c.ext_fam = p.ext_fam;
312
313 return c;
314}
315
316static u32 get_patch_level(void)
317{
318 u32 rev, dummy __always_unused;
319
320 if (IS_ENABLED(CONFIG_MICROCODE_DBG) && x86_hypervisor_present) {
321 int cpu = smp_processor_id();
322
323 if (!microcode_rev[cpu]) {
324 if (!base_rev)
325 base_rev = cpuid_to_ucode_rev(bsp_cpuid_1_eax);
326
327 microcode_rev[cpu] = base_rev;
328
329 ucode_dbg("CPU%d, base_rev: 0x%x\n", cpu, base_rev);
330 }
331
332 return microcode_rev[cpu];
333 }
334
335 native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
336 if (!rev) {
337 if (x86_family(bsp_cpuid_1_eax) < 0x17)
338 return rev;
339
340 rev = cpuid_to_ucode_rev(bsp_cpuid_1_eax);
341 pr_info_once("No current revision, generating the lowest one: 0x%x\n", rev);
342 }
343
344 return rev;
345}
346
347static u16 find_equiv_id(struct equiv_cpu_table *et, u32 sig)
348{
349 unsigned int i;
350
351 /* Zen and newer do not need an equivalence table. */
352 if (x86_family(bsp_cpuid_1_eax) >= 0x17)
353 return 0;
354
355 if (!et || !et->num_entries)
356 return 0;
357
358 for (i = 0; i < et->num_entries; i++) {
359 struct equiv_cpu_entry *e = &et->entry[i];
360
361 if (sig == e->installed_cpu)
362 return e->equiv_cpu;
363 }
364 return 0;
365}
366
367/*
368 * Check whether there is a valid microcode container file at the beginning
369 * of @buf of size @buf_size.
370 */
371static bool verify_container(const u8 *buf, size_t buf_size)
372{
373 u32 cont_magic;
374
375 if (buf_size <= CONTAINER_HDR_SZ) {
376 ucode_dbg("Truncated microcode container header.\n");
377 return false;
378 }
379
380 cont_magic = *(const u32 *)buf;
381 if (cont_magic != UCODE_MAGIC) {
382 ucode_dbg("Invalid magic value (0x%08x).\n", cont_magic);
383 return false;
384 }
385
386 return true;
387}
388
389/*
390 * Check whether there is a valid, non-truncated CPU equivalence table at the
391 * beginning of @buf of size @buf_size.
392 */
393static bool verify_equivalence_table(const u8 *buf, size_t buf_size)
394{
395 const u32 *hdr = (const u32 *)buf;
396 u32 cont_type, equiv_tbl_len;
397
398 if (!verify_container(buf, buf_size))
399 return false;
400
401 /* Zen and newer do not need an equivalence table. */
402 if (x86_family(bsp_cpuid_1_eax) >= 0x17)
403 return true;
404
405 cont_type = hdr[1];
406 if (cont_type != UCODE_EQUIV_CPU_TABLE_TYPE) {
407 ucode_dbg("Wrong microcode container equivalence table type: %u.\n",
408 cont_type);
409 return false;
410 }
411
412 buf_size -= CONTAINER_HDR_SZ;
413
414 equiv_tbl_len = hdr[2];
415 if (equiv_tbl_len < sizeof(struct equiv_cpu_entry) ||
416 buf_size < equiv_tbl_len) {
417 ucode_dbg("Truncated equivalence table.\n");
418 return false;
419 }
420
421 return true;
422}
423
424/*
425 * Check whether there is a valid, non-truncated microcode patch section at the
426 * beginning of @buf of size @buf_size.
427 *
428 * On success, @sh_psize returns the patch size according to the section header,
429 * to the caller.
430 */
431static bool __verify_patch_section(const u8 *buf, size_t buf_size, u32 *sh_psize)
432{
433 u32 p_type, p_size;
434 const u32 *hdr;
435
436 if (buf_size < SECTION_HDR_SIZE) {
437 ucode_dbg("Truncated patch section.\n");
438 return false;
439 }
440
441 hdr = (const u32 *)buf;
442 p_type = hdr[0];
443 p_size = hdr[1];
444
445 if (p_type != UCODE_UCODE_TYPE) {
446 ucode_dbg("Invalid type field (0x%x) in container file section header.\n",
447 p_type);
448 return false;
449 }
450
451 if (p_size < sizeof(struct microcode_header_amd)) {
452 ucode_dbg("Patch of size %u too short.\n", p_size);
453 return false;
454 }
455
456 *sh_psize = p_size;
457
458 return true;
459}
460
461/*
462 * Check whether the passed remaining file @buf_size is large enough to contain
463 * a patch of the indicated @sh_psize (and also whether this size does not
464 * exceed the per-family maximum). @sh_psize is the size read from the section
465 * header.
466 */
467static bool __verify_patch_size(u32 sh_psize, size_t buf_size)
468{
469 u8 family = x86_family(bsp_cpuid_1_eax);
470 u32 max_size;
471
472 if (family >= 0x15)
473 goto ret;
474
475#define F1XH_MPB_MAX_SIZE 2048
476#define F14H_MPB_MAX_SIZE 1824
477
478 switch (family) {
479 case 0x10 ... 0x12:
480 max_size = F1XH_MPB_MAX_SIZE;
481 break;
482 case 0x14:
483 max_size = F14H_MPB_MAX_SIZE;
484 break;
485 default:
486 WARN(1, "%s: WTF family: 0x%x\n", __func__, family);
487 return false;
488 }
489
490 if (sh_psize > max_size)
491 return false;
492
493ret:
494 /* Working with the whole buffer so < is ok. */
495 return sh_psize <= buf_size;
496}
497
498/*
499 * Verify the patch in @buf.
500 *
501 * Returns:
502 * negative: on error
503 * positive: patch is not for this family, skip it
504 * 0: success
505 */
506static int verify_patch(const u8 *buf, size_t buf_size, u32 *patch_size)
507{
508 u8 family = x86_family(bsp_cpuid_1_eax);
509 struct microcode_header_amd *mc_hdr;
510 u32 cur_rev, cutoff, patch_rev;
511 u32 sh_psize;
512 u16 proc_id;
513 u8 patch_fam;
514
515 if (!__verify_patch_section(buf, buf_size, &sh_psize))
516 return -1;
517
518 /*
519 * The section header length is not included in this indicated size
520 * but is present in the leftover file length so we need to subtract
521 * it before passing this value to the function below.
522 */
523 buf_size -= SECTION_HDR_SIZE;
524
525 /*
526 * Check if the remaining buffer is big enough to contain a patch of
527 * size sh_psize, as the section claims.
528 */
529 if (buf_size < sh_psize) {
530 ucode_dbg("Patch of size %u truncated.\n", sh_psize);
531 return -1;
532 }
533
534 if (!__verify_patch_size(sh_psize, buf_size)) {
535 ucode_dbg("Per-family patch size mismatch.\n");
536 return -1;
537 }
538
539 *patch_size = sh_psize;
540
541 mc_hdr = (struct microcode_header_amd *)(buf + SECTION_HDR_SIZE);
542 if (mc_hdr->nb_dev_id || mc_hdr->sb_dev_id) {
543 pr_err("Patch-ID 0x%08x: chipset-specific code unsupported.\n", mc_hdr->patch_id);
544 return -1;
545 }
546
547 proc_id = mc_hdr->processor_rev_id;
548 patch_fam = 0xf + (proc_id >> 12);
549
550 if (patch_fam != family)
551 return 1;
552
553 cur_rev = get_patch_level();
554
555 /* No cutoff revision means old/unaffected by signing algorithm weakness => matches */
556 cutoff = get_cutoff_revision(cur_rev);
557 if (!cutoff)
558 goto ok;
559
560 patch_rev = mc_hdr->patch_id;
561
562 ucode_dbg("cur_rev: 0x%x, cutoff: 0x%x, patch_rev: 0x%x\n",
563 cur_rev, cutoff, patch_rev);
564
565 if (cur_rev <= cutoff && patch_rev <= cutoff)
566 goto ok;
567
568 if (cur_rev > cutoff && patch_rev > cutoff)
569 goto ok;
570
571 return 1;
572
573ok:
574 ucode_dbg("Patch-ID 0x%08x: family: 0x%x\n", mc_hdr->patch_id, patch_fam);
575
576 return 0;
577}
578
579static bool mc_patch_matches(struct microcode_amd *mc, u16 eq_id)
580{
581 /* Zen and newer do not need an equivalence table. */
582 if (x86_family(bsp_cpuid_1_eax) >= 0x17)
583 return ucode_rev_to_cpuid(mc->hdr.patch_id).full == bsp_cpuid_1_eax;
584 else
585 return eq_id == mc->hdr.processor_rev_id;
586}
587
588/*
589 * This scans the ucode blob for the proper container as we can have multiple
590 * containers glued together.
591 *
592 * Returns the amount of bytes consumed while scanning. @desc contains all the
593 * data we're going to use in later stages of the application.
594 */
595static size_t parse_container(u8 *ucode, size_t size, struct cont_desc *desc)
596{
597 struct equiv_cpu_table table;
598 size_t orig_size = size;
599 u32 *hdr = (u32 *)ucode;
600 u16 eq_id;
601 u8 *buf;
602
603 if (!verify_equivalence_table(ucode, size))
604 return 0;
605
606 buf = ucode;
607
608 table.entry = (struct equiv_cpu_entry *)(buf + CONTAINER_HDR_SZ);
609 table.num_entries = hdr[2] / sizeof(struct equiv_cpu_entry);
610
611 /*
612 * Find the equivalence ID of our CPU in this table. Even if this table
613 * doesn't contain a patch for the CPU, scan through the whole container
614 * so that it can be skipped in case there are other containers appended.
615 */
616 eq_id = find_equiv_id(&table, bsp_cpuid_1_eax);
617
618 buf += hdr[2] + CONTAINER_HDR_SZ;
619 size -= hdr[2] + CONTAINER_HDR_SZ;
620
621 /*
622 * Scan through the rest of the container to find where it ends. We do
623 * some basic sanity-checking too.
624 */
625 while (size > 0) {
626 struct microcode_amd *mc;
627 u32 patch_size;
628 int ret;
629
630 ret = verify_patch(buf, size, &patch_size);
631 if (ret < 0) {
632 /*
633 * Patch verification failed, skip to the next container, if
634 * there is one. Before exit, check whether that container has
635 * found a patch already. If so, use it.
636 */
637 goto out;
638 } else if (ret > 0) {
639 goto skip;
640 }
641
642 mc = (struct microcode_amd *)(buf + SECTION_HDR_SIZE);
643
644 if (mc_patch_matches(mc, eq_id)) {
645 desc->psize = patch_size;
646 desc->mc = mc;
647
648 ucode_dbg(" match: size: %d\n", patch_size);
649 }
650
651skip:
652 /* Skip patch section header too: */
653 buf += patch_size + SECTION_HDR_SIZE;
654 size -= patch_size + SECTION_HDR_SIZE;
655 }
656
657out:
658 /*
659 * If we have found a patch (desc->mc), it means we're looking at the
660 * container which has a patch for this CPU so return 0 to mean, @ucode
661 * already points to the proper container. Otherwise, we return the size
662 * we scanned so that we can advance to the next container in the
663 * buffer.
664 */
665 if (desc->mc) {
666 desc->data = ucode;
667 desc->size = orig_size - size;
668
669 return 0;
670 }
671
672 return orig_size - size;
673}
674
675/*
676 * Scan the ucode blob for the proper container as we can have multiple
677 * containers glued together.
678 */
679static void scan_containers(u8 *ucode, size_t size, struct cont_desc *desc)
680{
681 while (size) {
682 size_t s = parse_container(ucode, size, desc);
683 if (!s)
684 return;
685
686 /* catch wraparound */
687 if (size >= s) {
688 ucode += s;
689 size -= s;
690 } else {
691 return;
692 }
693 }
694}
695
696static bool __apply_microcode_amd(struct microcode_amd *mc, u32 *cur_rev,
697 unsigned int psize)
698{
699 unsigned long p_addr = (unsigned long)&mc->hdr.data_code;
700
701 if (!verify_sha256_digest(mc->hdr.patch_id, *cur_rev, (const u8 *)p_addr, psize))
702 return false;
703
704 native_wrmsrq(MSR_AMD64_PATCH_LOADER, p_addr);
705
706 if (x86_family(bsp_cpuid_1_eax) == 0x17) {
707 unsigned long p_addr_end = p_addr + psize - 1;
708
709 invlpg(p_addr);
710
711 /*
712 * Flush next page too if patch image is crossing a page
713 * boundary.
714 */
715 if (p_addr >> PAGE_SHIFT != p_addr_end >> PAGE_SHIFT)
716 invlpg(p_addr_end);
717 }
718
719 if (IS_ENABLED(CONFIG_MICROCODE_DBG) && x86_hypervisor_present)
720 microcode_rev[smp_processor_id()] = mc->hdr.patch_id;
721
722 /* verify patch application was successful */
723 *cur_rev = get_patch_level();
724
725 ucode_dbg("updated rev: 0x%x\n", *cur_rev);
726
727 if (*cur_rev != mc->hdr.patch_id)
728 return false;
729
730 return true;
731}
732
733static bool get_builtin_microcode(struct cpio_data *cp)
734{
735 char fw_name[36] = "amd-ucode/microcode_amd.bin";
736 u8 family = x86_family(bsp_cpuid_1_eax);
737 struct firmware fw;
738
739 if (IS_ENABLED(CONFIG_X86_32))
740 return false;
741
742 if (family >= 0x15)
743 snprintf(fw_name, sizeof(fw_name),
744 "amd-ucode/microcode_amd_fam%02hhxh.bin", family);
745
746 if (firmware_request_builtin(&fw, fw_name)) {
747 cp->size = fw.size;
748 cp->data = (void *)fw.data;
749 return true;
750 }
751
752 return false;
753}
754
755static bool __init find_blobs_in_containers(struct cpio_data *ret)
756{
757 struct cpio_data cp;
758 bool found;
759
760 if (!get_builtin_microcode(&cp))
761 cp = find_microcode_in_initrd(ucode_path);
762
763 found = cp.data && cp.size;
764 if (found)
765 *ret = cp;
766
767 return found;
768}
769
770/*
771 * Early load occurs before we can vmalloc(). So we look for the microcode
772 * patch container file in initrd, traverse equivalent cpu table, look for a
773 * matching microcode patch, and update, all in initrd memory in place.
774 * When vmalloc() is available for use later -- on 64-bit during first AP load,
775 * and on 32-bit during save_microcode_in_initrd() -- we can call
776 * load_microcode_amd() to save equivalent cpu table and microcode patches in
777 * kernel heap memory.
778 */
779void __init load_ucode_amd_bsp(struct early_load_data *ed, unsigned int cpuid_1_eax)
780{
781 struct cont_desc desc = { };
782 struct microcode_amd *mc;
783 struct cpio_data cp = { };
784 char buf[4];
785 u32 rev;
786
787 if (cmdline_find_option(boot_command_line, "microcode.amd_sha_check", buf, 4)) {
788 if (!strncmp(buf, "off", 3)) {
789 sha_check = false;
790 pr_warn_once("It is a very very bad idea to disable the blobs SHA check!\n");
791 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
792 }
793 }
794
795 bsp_cpuid_1_eax = cpuid_1_eax;
796
797 rev = get_patch_level();
798 ed->old_rev = rev;
799
800 /* Needed in load_microcode_amd() */
801 ucode_cpu_info[0].cpu_sig.sig = cpuid_1_eax;
802
803 if (!find_blobs_in_containers(&cp))
804 return;
805
806 scan_containers(cp.data, cp.size, &desc);
807
808 mc = desc.mc;
809 if (!mc)
810 return;
811
812 /*
813 * Allow application of the same revision to pick up SMT-specific
814 * changes even if the revision of the other SMT thread is already
815 * up-to-date.
816 */
817 if (ed->old_rev > mc->hdr.patch_id)
818 return;
819
820 if (__apply_microcode_amd(mc, &rev, desc.psize))
821 ed->new_rev = rev;
822}
823
824static inline bool patch_cpus_equivalent(struct ucode_patch *p,
825 struct ucode_patch *n,
826 bool ignore_stepping)
827{
828 /* Zen and newer hardcode the f/m/s in the patch ID */
829 if (x86_family(bsp_cpuid_1_eax) >= 0x17) {
830 union cpuid_1_eax p_cid = ucode_rev_to_cpuid(p->patch_id);
831 union cpuid_1_eax n_cid = ucode_rev_to_cpuid(n->patch_id);
832
833 if (ignore_stepping) {
834 p_cid.stepping = 0;
835 n_cid.stepping = 0;
836 }
837
838 return p_cid.full == n_cid.full;
839 } else {
840 return p->equiv_cpu == n->equiv_cpu;
841 }
842}
843
844/*
845 * a small, trivial cache of per-family ucode patches
846 */
847static struct ucode_patch *cache_find_patch(struct ucode_cpu_info *uci, u16 equiv_cpu)
848{
849 struct ucode_patch *p;
850 struct ucode_patch n;
851
852 n.equiv_cpu = equiv_cpu;
853 n.patch_id = uci->cpu_sig.rev;
854
855 list_for_each_entry(p, &microcode_cache, plist)
856 if (patch_cpus_equivalent(p, &n, false))
857 return p;
858
859 return NULL;
860}
861
862static inline int patch_newer(struct ucode_patch *p, struct ucode_patch *n)
863{
864 /* Zen and newer hardcode the f/m/s in the patch ID */
865 if (x86_family(bsp_cpuid_1_eax) >= 0x17) {
866 union zen_patch_rev zp, zn;
867
868 zp.ucode_rev = p->patch_id;
869 zn.ucode_rev = n->patch_id;
870
871 if (zn.stepping != zp.stepping)
872 return -1;
873
874 return zn.rev > zp.rev;
875 } else {
876 return n->patch_id > p->patch_id;
877 }
878}
879
880static void update_cache(struct ucode_patch *new_patch)
881{
882 struct ucode_patch *p;
883 int ret;
884
885 list_for_each_entry(p, &microcode_cache, plist) {
886 if (patch_cpus_equivalent(p, new_patch, true)) {
887 ret = patch_newer(p, new_patch);
888 if (ret < 0)
889 continue;
890 else if (!ret) {
891 /* we already have the latest patch */
892 kfree(new_patch->data);
893 kfree(new_patch);
894 return;
895 }
896
897 list_replace(&p->plist, &new_patch->plist);
898 kfree(p->data);
899 kfree(p);
900 return;
901 }
902 }
903 /* no patch found, add it */
904 list_add_tail(&new_patch->plist, &microcode_cache);
905}
906
907static void free_cache(void)
908{
909 struct ucode_patch *p, *tmp;
910
911 list_for_each_entry_safe(p, tmp, &microcode_cache, plist) {
912 __list_del(p->plist.prev, p->plist.next);
913 kfree(p->data);
914 kfree(p);
915 }
916}
917
918static struct ucode_patch *find_patch(unsigned int cpu)
919{
920 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
921 u16 equiv_id = 0;
922
923 uci->cpu_sig.rev = get_patch_level();
924
925 if (x86_family(bsp_cpuid_1_eax) < 0x17) {
926 equiv_id = find_equiv_id(&equiv_table, uci->cpu_sig.sig);
927 if (!equiv_id)
928 return NULL;
929 }
930
931 return cache_find_patch(uci, equiv_id);
932}
933
934void reload_ucode_amd(unsigned int cpu)
935{
936 u32 rev, dummy __always_unused;
937 struct microcode_amd *mc;
938 struct ucode_patch *p;
939
940 p = find_patch(cpu);
941 if (!p)
942 return;
943
944 mc = p->data;
945
946 rev = get_patch_level();
947 if (rev < mc->hdr.patch_id) {
948 if (__apply_microcode_amd(mc, &rev, p->size))
949 pr_info_once("reload revision: 0x%08x\n", rev);
950 }
951}
952
953static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
954{
955 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
956 struct ucode_patch *p;
957
958 csig->sig = cpuid_eax(0x00000001);
959 csig->rev = get_patch_level();
960
961 /*
962 * a patch could have been loaded early, set uci->mc so that
963 * mc_bp_resume() can call apply_microcode()
964 */
965 p = find_patch(cpu);
966 if (p && (p->patch_id == csig->rev))
967 uci->mc = p->data;
968
969 return 0;
970}
971
972static enum ucode_state apply_microcode_amd(int cpu)
973{
974 struct cpuinfo_x86 *c = &cpu_data(cpu);
975 struct microcode_amd *mc_amd;
976 struct ucode_cpu_info *uci;
977 struct ucode_patch *p;
978 enum ucode_state ret;
979 u32 rev;
980
981 BUG_ON(raw_smp_processor_id() != cpu);
982
983 uci = ucode_cpu_info + cpu;
984
985 p = find_patch(cpu);
986 if (!p)
987 return UCODE_NFOUND;
988
989 rev = uci->cpu_sig.rev;
990
991 mc_amd = p->data;
992 uci->mc = p->data;
993
994 /* need to apply patch? */
995 if (rev > mc_amd->hdr.patch_id) {
996 ret = UCODE_OK;
997 goto out;
998 }
999
1000 if (!__apply_microcode_amd(mc_amd, &rev, p->size)) {
1001 pr_err("CPU%d: update failed for patch_level=0x%08x\n",
1002 cpu, mc_amd->hdr.patch_id);
1003 return UCODE_ERROR;
1004 }
1005
1006 rev = mc_amd->hdr.patch_id;
1007 ret = UCODE_UPDATED;
1008
1009out:
1010 uci->cpu_sig.rev = rev;
1011 c->microcode = rev;
1012
1013 /* Update boot_cpu_data's revision too, if we're on the BSP: */
1014 if (c->cpu_index == boot_cpu_data.cpu_index)
1015 boot_cpu_data.microcode = rev;
1016
1017 return ret;
1018}
1019
1020void load_ucode_amd_ap(unsigned int cpuid_1_eax)
1021{
1022 unsigned int cpu = smp_processor_id();
1023
1024 ucode_cpu_info[cpu].cpu_sig.sig = cpuid_1_eax;
1025 apply_microcode_amd(cpu);
1026}
1027
1028static size_t install_equiv_cpu_table(const u8 *buf, size_t buf_size)
1029{
1030 u32 equiv_tbl_len;
1031 const u32 *hdr;
1032
1033 if (!verify_equivalence_table(buf, buf_size))
1034 return 0;
1035
1036 hdr = (const u32 *)buf;
1037 equiv_tbl_len = hdr[2];
1038
1039 /* Zen and newer do not need an equivalence table. */
1040 if (x86_family(bsp_cpuid_1_eax) >= 0x17)
1041 goto out;
1042
1043 equiv_table.entry = vmalloc(equiv_tbl_len);
1044 if (!equiv_table.entry) {
1045 pr_err("failed to allocate equivalent CPU table\n");
1046 return 0;
1047 }
1048
1049 memcpy(equiv_table.entry, buf + CONTAINER_HDR_SZ, equiv_tbl_len);
1050 equiv_table.num_entries = equiv_tbl_len / sizeof(struct equiv_cpu_entry);
1051
1052out:
1053 /* add header length */
1054 return equiv_tbl_len + CONTAINER_HDR_SZ;
1055}
1056
1057static void free_equiv_cpu_table(void)
1058{
1059 if (x86_family(bsp_cpuid_1_eax) >= 0x17)
1060 return;
1061
1062 vfree(equiv_table.entry);
1063 memset(&equiv_table, 0, sizeof(equiv_table));
1064}
1065
1066static void cleanup(void)
1067{
1068 free_equiv_cpu_table();
1069 free_cache();
1070}
1071
1072/*
1073 * Return a non-negative value even if some of the checks failed so that
1074 * we can skip over the next patch. If we return a negative value, we
1075 * signal a grave error like a memory allocation has failed and the
1076 * driver cannot continue functioning normally. In such cases, we tear
1077 * down everything we've used up so far and exit.
1078 */
1079static int verify_and_add_patch(u8 family, u8 *fw, unsigned int leftover,
1080 unsigned int *patch_size)
1081{
1082 struct microcode_header_amd *mc_hdr;
1083 struct ucode_patch *patch;
1084 u16 proc_id;
1085 int ret;
1086
1087 ret = verify_patch(fw, leftover, patch_size);
1088 if (ret)
1089 return ret;
1090
1091 patch = kzalloc_obj(*patch);
1092 if (!patch) {
1093 pr_err("Patch allocation failure.\n");
1094 return -EINVAL;
1095 }
1096
1097 patch->data = kmemdup(fw + SECTION_HDR_SIZE, *patch_size, GFP_KERNEL);
1098 if (!patch->data) {
1099 pr_err("Patch data allocation failure.\n");
1100 kfree(patch);
1101 return -EINVAL;
1102 }
1103 patch->size = *patch_size;
1104
1105 mc_hdr = (struct microcode_header_amd *)(fw + SECTION_HDR_SIZE);
1106 proc_id = mc_hdr->processor_rev_id;
1107
1108 INIT_LIST_HEAD(&patch->plist);
1109 patch->patch_id = mc_hdr->patch_id;
1110 patch->equiv_cpu = proc_id;
1111
1112 ucode_dbg("%s: Adding patch_id: 0x%08x, proc_id: 0x%04x\n",
1113 __func__, patch->patch_id, proc_id);
1114
1115 /* ... and add to cache. */
1116 update_cache(patch);
1117
1118 return 0;
1119}
1120
1121/* Scan the blob in @data and add microcode patches to the cache. */
1122static enum ucode_state __load_microcode_amd(u8 family, const u8 *data, size_t size)
1123{
1124 u8 *fw = (u8 *)data;
1125 size_t offset;
1126
1127 offset = install_equiv_cpu_table(data, size);
1128 if (!offset)
1129 return UCODE_ERROR;
1130
1131 fw += offset;
1132 size -= offset;
1133
1134 if (*(u32 *)fw != UCODE_UCODE_TYPE) {
1135 pr_err("invalid type field in container file section header\n");
1136 free_equiv_cpu_table();
1137 return UCODE_ERROR;
1138 }
1139
1140 while (size > 0) {
1141 unsigned int crnt_size = 0;
1142 int ret;
1143
1144 ret = verify_and_add_patch(family, fw, size, &crnt_size);
1145 if (ret < 0)
1146 return UCODE_ERROR;
1147
1148 fw += crnt_size + SECTION_HDR_SIZE;
1149 size -= (crnt_size + SECTION_HDR_SIZE);
1150 }
1151
1152 return UCODE_OK;
1153}
1154
1155static enum ucode_state _load_microcode_amd(u8 family, const u8 *data, size_t size)
1156{
1157 enum ucode_state ret;
1158
1159 /* free old equiv table */
1160 free_equiv_cpu_table();
1161
1162 ret = __load_microcode_amd(family, data, size);
1163 if (ret != UCODE_OK)
1164 cleanup();
1165
1166 return ret;
1167}
1168
1169static enum ucode_state load_microcode_amd(u8 family, const u8 *data, size_t size)
1170{
1171 struct cpuinfo_x86 *c;
1172 unsigned int nid, cpu;
1173 struct ucode_patch *p;
1174 enum ucode_state ret;
1175
1176 ret = _load_microcode_amd(family, data, size);
1177 if (ret != UCODE_OK)
1178 return ret;
1179
1180 for_each_node_with_cpus(nid) {
1181 cpu = cpumask_first(cpumask_of_node(nid));
1182 c = &cpu_data(cpu);
1183
1184 p = find_patch(cpu);
1185 if (!p)
1186 continue;
1187
1188 if (c->microcode >= p->patch_id)
1189 continue;
1190
1191 ret = UCODE_NEW;
1192 }
1193
1194 return ret;
1195}
1196
1197static int __init save_microcode_in_initrd(void)
1198{
1199 struct cpuinfo_x86 *c = &boot_cpu_data;
1200 struct cont_desc desc = { 0 };
1201 unsigned int cpuid_1_eax;
1202 enum ucode_state ret;
1203 struct cpio_data cp;
1204
1205 if (microcode_loader_disabled() || c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10)
1206 return 0;
1207
1208 cpuid_1_eax = native_cpuid_eax(1);
1209
1210 if (!find_blobs_in_containers(&cp))
1211 return -EINVAL;
1212
1213 scan_containers(cp.data, cp.size, &desc);
1214 if (!desc.mc)
1215 return -EINVAL;
1216
1217 ret = _load_microcode_amd(x86_family(cpuid_1_eax), desc.data, desc.size);
1218 if (ret > UCODE_UPDATED)
1219 return -EINVAL;
1220
1221 return 0;
1222}
1223early_initcall(save_microcode_in_initrd);
1224
1225/*
1226 * AMD microcode firmware naming convention, up to family 15h they are in
1227 * the legacy file:
1228 *
1229 * amd-ucode/microcode_amd.bin
1230 *
1231 * This legacy file is always smaller than 2K in size.
1232 *
1233 * Beginning with family 15h, they are in family-specific firmware files:
1234 *
1235 * amd-ucode/microcode_amd_fam15h.bin
1236 * amd-ucode/microcode_amd_fam16h.bin
1237 * ...
1238 *
1239 * These might be larger than 2K.
1240 */
1241static enum ucode_state request_microcode_amd(int cpu, struct device *device)
1242{
1243 char fw_name[36] = "amd-ucode/microcode_amd.bin";
1244 struct cpuinfo_x86 *c = &cpu_data(cpu);
1245 enum ucode_state ret = UCODE_NFOUND;
1246 const struct firmware *fw;
1247
1248 if (force_minrev)
1249 return UCODE_NFOUND;
1250
1251 if (c->x86 >= 0x15)
1252 snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86);
1253
1254 if (request_firmware_direct(&fw, (const char *)fw_name, device)) {
1255 ucode_dbg("failed to load file %s\n", fw_name);
1256 goto out;
1257 }
1258
1259 ret = UCODE_ERROR;
1260 if (!verify_container(fw->data, fw->size))
1261 goto fw_release;
1262
1263 ret = load_microcode_amd(c->x86, fw->data, fw->size);
1264
1265 fw_release:
1266 release_firmware(fw);
1267
1268 out:
1269 return ret;
1270}
1271
1272static void microcode_fini_cpu_amd(int cpu)
1273{
1274 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
1275
1276 uci->mc = NULL;
1277}
1278
1279static void finalize_late_load_amd(int result)
1280{
1281 if (result)
1282 cleanup();
1283}
1284
1285static struct microcode_ops microcode_amd_ops = {
1286 .request_microcode_fw = request_microcode_amd,
1287 .collect_cpu_info = collect_cpu_info_amd,
1288 .apply_microcode = apply_microcode_amd,
1289 .microcode_fini_cpu = microcode_fini_cpu_amd,
1290 .finalize_late_load = finalize_late_load_amd,
1291 .nmi_safe = true,
1292};
1293
1294struct microcode_ops * __init init_amd_microcode(void)
1295{
1296 struct cpuinfo_x86 *c = &boot_cpu_data;
1297
1298 if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
1299 pr_warn("AMD CPU family 0x%x not supported\n", c->x86);
1300 return NULL;
1301 }
1302 return &microcode_amd_ops;
1303}
1304
1305void __exit exit_amd_microcode(void)
1306{
1307 cleanup();
1308}