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1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _ASM_X86_RESCTRL_INTERNAL_H
3#define _ASM_X86_RESCTRL_INTERNAL_H
4
5#include <linux/resctrl.h>
6
7#define L3_QOS_CDP_ENABLE 0x01ULL
8
9#define L2_QOS_CDP_ENABLE 0x01ULL
10
11#define MBM_CNTR_WIDTH_BASE 24
12
13#define MBA_IS_LINEAR 0x4
14
15#define MBM_CNTR_WIDTH_OFFSET_AMD 20
16
17/* Hygon MBM counter width as an offset from MBM_CNTR_WIDTH_BASE */
18#define MBM_CNTR_WIDTH_OFFSET_HYGON 8
19
20#define RMID_VAL_ERROR BIT_ULL(63)
21
22#define RMID_VAL_UNAVAIL BIT_ULL(62)
23
24/*
25 * With the above fields in use 62 bits remain in MSR_IA32_QM_CTR for
26 * data to be returned. The counter width is discovered from the hardware
27 * as an offset from MBM_CNTR_WIDTH_BASE.
28 */
29#define MBM_CNTR_WIDTH_OFFSET_MAX (62 - MBM_CNTR_WIDTH_BASE)
30
31/**
32 * struct arch_mbm_state - values used to compute resctrl_arch_rmid_read()s
33 * return value.
34 * @chunks: Total data moved (multiply by rdt_group.mon_scale to get bytes)
35 * @prev_msr: Value of IA32_QM_CTR last time it was read for the RMID used to
36 * find this struct.
37 */
38struct arch_mbm_state {
39 u64 chunks;
40 u64 prev_msr;
41};
42
43/* Setting bit 0 in L3_QOS_EXT_CFG enables the ABMC feature. */
44#define ABMC_ENABLE_BIT 0
45
46/*
47 * Qos Event Identifiers.
48 */
49#define ABMC_EXTENDED_EVT_ID BIT(31)
50#define ABMC_EVT_ID BIT(0)
51
52/* Setting bit 1 in MSR_IA32_L3_QOS_EXT_CFG enables the SDCIAE feature. */
53#define SDCIAE_ENABLE_BIT 1
54
55/**
56 * struct rdt_hw_ctrl_domain - Arch private attributes of a set of CPUs that share
57 * a resource for a control function
58 * @d_resctrl: Properties exposed to the resctrl file system
59 * @ctrl_val: array of cache or mem ctrl values (indexed by CLOSID)
60 *
61 * Members of this structure are accessed via helpers that provide abstraction.
62 */
63struct rdt_hw_ctrl_domain {
64 struct rdt_ctrl_domain d_resctrl;
65 u32 *ctrl_val;
66};
67
68/**
69 * struct rdt_hw_l3_mon_domain - Arch private attributes of a set of CPUs sharing
70 * RDT_RESOURCE_L3 monitoring
71 * @d_resctrl: Properties exposed to the resctrl file system
72 * @arch_mbm_states: Per-event pointer to the MBM event's saved state.
73 * An MBM event's state is an array of struct arch_mbm_state
74 * indexed by RMID on x86.
75 *
76 * Members of this structure are accessed via helpers that provide abstraction.
77 */
78struct rdt_hw_l3_mon_domain {
79 struct rdt_l3_mon_domain d_resctrl;
80 struct arch_mbm_state *arch_mbm_states[QOS_NUM_L3_MBM_EVENTS];
81};
82
83static inline struct rdt_hw_ctrl_domain *resctrl_to_arch_ctrl_dom(struct rdt_ctrl_domain *r)
84{
85 return container_of(r, struct rdt_hw_ctrl_domain, d_resctrl);
86}
87
88static inline struct rdt_hw_l3_mon_domain *resctrl_to_arch_mon_dom(struct rdt_l3_mon_domain *r)
89{
90 return container_of(r, struct rdt_hw_l3_mon_domain, d_resctrl);
91}
92
93/**
94 * struct rdt_perf_pkg_mon_domain - CPUs sharing an package scoped resctrl monitor resource
95 * @hdr: common header for different domain types
96 */
97struct rdt_perf_pkg_mon_domain {
98 struct rdt_domain_hdr hdr;
99};
100
101/**
102 * struct msr_param - set a range of MSRs from a domain
103 * @res: The resource to use
104 * @dom: The domain to update
105 * @low: Beginning index from base MSR
106 * @high: End index
107 */
108struct msr_param {
109 struct rdt_resource *res;
110 struct rdt_ctrl_domain *dom;
111 u32 low;
112 u32 high;
113};
114
115/**
116 * struct rdt_hw_resource - arch private attributes of a resctrl resource
117 * @r_resctrl: Attributes of the resource used directly by resctrl.
118 * @num_closid: Maximum number of closid this hardware can support,
119 * regardless of CDP. This is exposed via
120 * resctrl_arch_get_num_closid() to avoid confusion
121 * with struct resctrl_schema's property of the same name,
122 * which has been corrected for features like CDP.
123 * @msr_base: Base MSR address for CBMs
124 * @msr_update: Function pointer to update QOS MSRs
125 * @mon_scale: cqm counter * mon_scale = occupancy in bytes
126 * @mbm_width: Monitor width, to detect and correct for overflow.
127 * @cdp_enabled: CDP state of this resource
128 * @mbm_cntr_assign_enabled: ABMC feature is enabled
129 * @sdciae_enabled: SDCIAE feature (backing "io_alloc") is enabled.
130 *
131 * Members of this structure are either private to the architecture
132 * e.g. mbm_width, or accessed via helpers that provide abstraction. e.g.
133 * msr_update and msr_base.
134 */
135struct rdt_hw_resource {
136 struct rdt_resource r_resctrl;
137 u32 num_closid;
138 unsigned int msr_base;
139 void (*msr_update)(struct msr_param *m);
140 unsigned int mon_scale;
141 unsigned int mbm_width;
142 bool cdp_enabled;
143 bool mbm_cntr_assign_enabled;
144 bool sdciae_enabled;
145};
146
147static inline struct rdt_hw_resource *resctrl_to_arch_res(struct rdt_resource *r)
148{
149 return container_of(r, struct rdt_hw_resource, r_resctrl);
150}
151
152extern struct rdt_hw_resource rdt_resources_all[];
153
154void arch_mon_domain_online(struct rdt_resource *r, struct rdt_l3_mon_domain *d);
155
156/* CPUID.(EAX=10H, ECX=ResID=1).EAX */
157union cpuid_0x10_1_eax {
158 struct {
159 unsigned int cbm_len:5;
160 } split;
161 unsigned int full;
162};
163
164/* CPUID.(EAX=10H, ECX=ResID=3).EAX */
165union cpuid_0x10_3_eax {
166 struct {
167 unsigned int max_delay:12;
168 } split;
169 unsigned int full;
170};
171
172/* CPUID.(EAX=10H, ECX=ResID).ECX */
173union cpuid_0x10_x_ecx {
174 struct {
175 unsigned int reserved:3;
176 unsigned int noncont:1;
177 } split;
178 unsigned int full;
179};
180
181/* CPUID.(EAX=10H, ECX=ResID).EDX */
182union cpuid_0x10_x_edx {
183 struct {
184 unsigned int cos_max:16;
185 } split;
186 unsigned int full;
187};
188
189/*
190 * ABMC counters are configured by writing to MSR_IA32_L3_QOS_ABMC_CFG.
191 *
192 * @bw_type : Event configuration that represents the memory
193 * transactions being tracked by the @cntr_id.
194 * @bw_src : Bandwidth source (RMID or CLOSID).
195 * @reserved1 : Reserved.
196 * @is_clos : @bw_src field is a CLOSID (not an RMID).
197 * @cntr_id : Counter identifier.
198 * @reserved : Reserved.
199 * @cntr_en : Counting enable bit.
200 * @cfg_en : Configuration enable bit.
201 *
202 * Configuration and counting:
203 * Counter can be configured across multiple writes to MSR. Configuration
204 * is applied only when @cfg_en = 1. Counter @cntr_id is reset when the
205 * configuration is applied.
206 * @cfg_en = 1, @cntr_en = 0 : Apply @cntr_id configuration but do not
207 * count events.
208 * @cfg_en = 1, @cntr_en = 1 : Apply @cntr_id configuration and start
209 * counting events.
210 */
211union l3_qos_abmc_cfg {
212 struct {
213 unsigned long bw_type :32,
214 bw_src :12,
215 reserved1: 3,
216 is_clos : 1,
217 cntr_id : 5,
218 reserved : 9,
219 cntr_en : 1,
220 cfg_en : 1;
221 } split;
222 unsigned long full;
223};
224
225void rdt_ctrl_update(void *arg);
226
227int rdt_get_l3_mon_config(struct rdt_resource *r);
228
229bool rdt_cpu_has(int flag);
230
231void __init intel_rdt_mbm_apply_quirk(void);
232
233void rdt_domain_reconfigure_cdp(struct rdt_resource *r);
234void resctrl_arch_mbm_cntr_assign_set_one(struct rdt_resource *r);
235
236#ifdef CONFIG_X86_CPU_RESCTRL_INTEL_AET
237bool intel_aet_get_events(void);
238void __exit intel_aet_exit(void);
239int intel_aet_read_event(int domid, u32 rmid, void *arch_priv, u64 *val);
240void intel_aet_mon_domain_setup(int cpu, int id, struct rdt_resource *r,
241 struct list_head *add_pos);
242bool intel_handle_aet_option(bool force_off, char *tok);
243#else
244static inline bool intel_aet_get_events(void) { return false; }
245static inline void __exit intel_aet_exit(void) { }
246static inline int intel_aet_read_event(int domid, u32 rmid, void *arch_priv, u64 *val)
247{
248 return -EINVAL;
249}
250
251static inline void intel_aet_mon_domain_setup(int cpu, int id, struct rdt_resource *r,
252 struct list_head *add_pos) { }
253static inline bool intel_handle_aet_option(bool force_off, char *tok) { return false; }
254#endif
255
256#endif /* _ASM_X86_RESCTRL_INTERNAL_H */