| 1 | /* SPDX-License-Identifier: GPL-2.0-only */
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| 2 | /*
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| 3 | *
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| 4 | * verify_cpu.S - Code for cpu long mode and SSE verification. This
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| 5 | * code has been borrowed from boot/setup.S and was introduced by
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| 6 | * Andi Kleen.
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| 7 | *
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| 8 | * Copyright (c) 2007 Andi Kleen (ak@suse.de)
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| 9 | * Copyright (c) 2007 Eric Biederman (ebiederm@xmission.com)
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| 10 | * Copyright (c) 2007 Vivek Goyal (vgoyal@in.ibm.com)
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| 11 | * Copyright (c) 2010 Kees Cook (kees.cook@canonical.com)
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| 12 | *
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| 13 | * This is a common code for verification whether CPU supports
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| 14 | * long mode and SSE or not. It is not called directly instead this
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| 15 | * file is included at various places and compiled in that context.
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| 16 | * This file is expected to run in 32bit code. Currently:
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| 17 | *
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| 18 | * arch/x86/boot/compressed/head_64.S: Boot cpu verification
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| 19 | * arch/x86/kernel/trampoline_64.S: secondary processor verification
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| 20 | * arch/x86/kernel/head_32.S: processor startup
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| 21 | *
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| 22 | * verify_cpu, returns the status of longmode and SSE in register %eax.
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| 23 | * 0: Success 1: Failure
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| 24 | *
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| 25 | * On Intel, the XD_DISABLE flag will be cleared as a side-effect.
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| 26 | *
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| 27 | * The caller needs to check for the error code and take the action
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| 28 | * appropriately. Either display a message or halt.
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| 29 | */
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| 30 |
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| 31 | |
| 32 | |
| 33 | |
| 34 |
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| 35 | |
| 36 | (REQUIRED_MASK0 & ((1<<(X86_FEATURE_XMM & 31)) | (1<<(X86_FEATURE_XMM2 & 31))))
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| 37 |
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| 38 | SYM_FUNC_START_LOCAL(verify_cpu)
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| 39 | pushf |
| 40 | push $0 |
| 41 | popf
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| 42 |
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| 43 | |
| 44 | pushfl |
| 45 | popl %eax
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| 46 | movl %eax,%ebx
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| 47 | xorl $0x200000,%eax
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| 48 | pushl %eax
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| 49 | popfl
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| 50 | pushfl
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| 51 | popl %eax
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| 52 | cmpl %eax,%ebx
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| 53 | jz .Lverify_cpu_no_longmode |
| 54 | |
| 55 |
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| 56 | movl $0x0,%eax |
| 57 | cpuid
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| 58 | cmpl $0x1,%eax
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| 59 | jb .Lverify_cpu_no_longmode |
| 60 |
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| 61 | xor %di,%di
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| 62 | cmpl $0x68747541,%ebx |
| 63 | jnz .Lverify_cpu_noamd
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| 64 | cmpl $0x69746e65,%edx
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| 65 | jnz .Lverify_cpu_noamd
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| 66 | cmpl $0x444d4163,%ecx
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| 67 | jnz .Lverify_cpu_noamd
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| 68 | mov $1,%di |
| 69 | jmp .Lverify_cpu_check
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| 70 |
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| 71 | .Lverify_cpu_noamd:
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| 72 | cmpl $0x756e6547,%ebx |
| 73 | jnz .Lverify_cpu_check
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| 74 | cmpl $0x49656e69,%edx
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| 75 | jnz .Lverify_cpu_check
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| 76 | cmpl $0x6c65746e,%ecx
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| 77 | jnz .Lverify_cpu_check
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| 78 |
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| 79 | |
| 80 | |
| 81 | movl $0x1, %eax |
| 82 | cpuid
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| 83 | movl %eax, %ecx
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| 84 |
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| 85 | andl $0x0ff00f00, %eax |
| 86 | shrl $8, %eax
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| 87 | cmpl $6, %eax
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| 88 | ja .Lverify_cpu_clear_xd |
| 89 | jb .Lverify_cpu_check |
| 90 |
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| 91 | andl $0x000f00f0, %ecx |
| 92 | shrl $4, %ecx
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| 93 | cmpl $0xd, %ecx
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| 94 | jb .Lverify_cpu_check |
| 95 |
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| 96 | .Lverify_cpu_clear_xd:
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| 97 | movl $MSR_IA32_MISC_ENABLE, %ecx
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| 98 | rdmsr
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| 99 | btrl $2, %edx |
| 100 | jnc .Lverify_cpu_check |
| 101 | wrmsr
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| 102 |
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| 103 | .Lverify_cpu_check:
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| 104 | movl $0x1,%eax |
| 105 | cpuid
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| 106 | andl $REQUIRED_MASK0,%edx
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| 107 | xorl $REQUIRED_MASK0,%edx
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| 108 | jnz .Lverify_cpu_no_longmode
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| 109 |
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| 110 | movl $0x80000000,%eax |
| 111 | cpuid
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| 112 | cmpl $0x80000001,%eax
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| 113 | jb .Lverify_cpu_no_longmode |
| 114 |
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| 115 | movl $0x80000001,%eax |
| 116 | cpuid
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| 117 | andl $REQUIRED_MASK1,%edx
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| 118 | xorl $REQUIRED_MASK1,%edx
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| 119 | jnz .Lverify_cpu_no_longmode
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| 120 |
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| 121 | .Lverify_cpu_sse_test:
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| 122 | movl $1,%eax
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| 123 | cpuid
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| 124 | andl $SSE_MASK,%edx
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| 125 | cmpl $SSE_MASK,%edx
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| 126 | je .Lverify_cpu_sse_ok
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| 127 | test %di,%di
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| 128 | jz .Lverify_cpu_no_longmode |
| 129 | movl $MSR_K7_HWCR,%ecx
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| 130 | rdmsr
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| 131 | btr $15,%eax |
| 132 | wrmsr
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| 133 | xor %di,%di |
| 134 | jmp .Lverify_cpu_sse_test |
| 135 |
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| 136 | .Lverify_cpu_no_longmode:
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| 137 | popf |
| 138 | movl $1,%eax
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| 139 | RET
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| 140 | .Lverify_cpu_sse_ok:
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| 141 | popf |
| 142 | xorl %eax, %eax
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| 143 | RET
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| 144 | SYM_FUNC_END(verify_cpu)
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