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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Precise Delay Loops for i386
4 *
5 * Copyright (C) 1993 Linus Torvalds
6 * Copyright (C) 1997 Martin Mares <[email protected]>
7 * Copyright (C) 2008 Jiri Hladky <hladky _dot_ jiri _at_ gmail _dot_ com>
8 *
9 * The __delay function must _NOT_ be inlined as its execution time
10 * depends wildly on alignment on many x86 processors. The additional
11 * jump magic is needed to get the timing stable on all the CPU's
12 * we have to worry about.
13 */
14
15#include <linux/export.h>
16#include <linux/sched.h>
17#include <linux/preempt.h>
18#include <linux/delay.h>
19
20#include <asm/processor.h>
21#include <asm/timer.h>
22#include <asm/mwait.h>
23
24#ifdef CONFIG_SMP
25# include <asm/smp.h>
26#endif
27
28static void delay_loop(u64 __loops);
29
30/*
31 * Calibration and selection of the delay mechanism happens only once
32 * during boot.
33 */
34static void (*delay_fn)(u64) __ro_after_init = delay_loop;
35static void (*delay_halt_fn)(u64 start, u64 cycles) __ro_after_init;
36
37/* simple loop based delay: */
38static void delay_loop(u64 __loops)
39{
40 unsigned long loops = (unsigned long)__loops;
41
42 asm volatile(
43 " test %0,%0 \n"
44 " jz 3f \n"
45 " jmp 1f \n"
46
47 ".align 16 \n"
48 "1: jmp 2f \n"
49
50 ".align 16 \n"
51 "2: dec %0 \n"
52 " jnz 2b \n"
53 "3: dec %0 \n"
54
55 : "+a" (loops)
56 :
57 );
58}
59
60/* TSC based delay: */
61static void delay_tsc(u64 cycles)
62{
63 u64 bclock, now;
64 int cpu;
65
66 preempt_disable();
67 cpu = smp_processor_id();
68 bclock = rdtsc_ordered();
69 for (;;) {
70 now = rdtsc_ordered();
71 if ((now - bclock) >= cycles)
72 break;
73
74 /* Allow RT tasks to run */
75 preempt_enable();
76 native_pause();
77 preempt_disable();
78
79 /*
80 * It is possible that we moved to another CPU, and
81 * since TSC's are per-cpu we need to calculate
82 * that. The delay must guarantee that we wait "at
83 * least" the amount of time. Being moved to another
84 * CPU could make the wait longer but we just need to
85 * make sure we waited long enough. Rebalance the
86 * counter for this CPU.
87 */
88 if (unlikely(cpu != smp_processor_id())) {
89 cycles -= (now - bclock);
90 cpu = smp_processor_id();
91 bclock = rdtsc_ordered();
92 }
93 }
94 preempt_enable();
95}
96
97/*
98 * On Intel the TPAUSE instruction waits until any of:
99 * 1) the TSC counter exceeds the value provided in EDX:EAX
100 * 2) global timeout in IA32_UMWAIT_CONTROL is exceeded
101 * 3) an external interrupt occurs
102 */
103static void delay_halt_tpause(u64 start, u64 cycles)
104{
105 u64 until = start + cycles;
106 u32 eax, edx;
107
108 eax = lower_32_bits(until);
109 edx = upper_32_bits(until);
110
111 /*
112 * Hard code the deeper (C0.2) sleep state because exit latency is
113 * small compared to the "microseconds" that usleep() will delay.
114 */
115 __tpause(TPAUSE_C02_STATE, edx, eax);
116}
117
118/*
119 * On some AMD platforms, MWAITX has a configurable 32-bit timer, that
120 * counts with TSC frequency. The input value is the number of TSC cycles
121 * to wait. MWAITX will also exit when the timer expires.
122 */
123static void delay_halt_mwaitx(u64 unused, u64 cycles)
124{
125 u64 delay;
126
127 delay = min_t(u64, MWAITX_MAX_WAIT_CYCLES, cycles);
128 /*
129 * Use cpu_tss_rw as a cacheline-aligned, seldom accessed per-cpu
130 * variable as the monitor target.
131 */
132 __monitorx(raw_cpu_ptr(&cpu_tss_rw), 0, 0);
133
134 /*
135 * AMD, like Intel, supports the EAX hint and EAX=0xf means, do not
136 * enter any deep C-state and we use it here in delay() to minimize
137 * wakeup latency.
138 */
139 __mwaitx(MWAITX_DISABLE_CSTATES, delay, MWAITX_ECX_TIMER_ENABLE);
140}
141
142/*
143 * Call a vendor specific function to delay for a given amount of time. Because
144 * these functions may return earlier than requested, check for actual elapsed
145 * time and call again until done.
146 */
147static void delay_halt(u64 __cycles)
148{
149 u64 start, end, cycles = __cycles;
150
151 /*
152 * Timer value of 0 causes MWAITX to wait indefinitely, unless there
153 * is a store on the memory monitored by MONITORX.
154 */
155 if (!cycles)
156 return;
157
158 start = rdtsc_ordered();
159
160 for (;;) {
161 delay_halt_fn(start, cycles);
162 end = rdtsc_ordered();
163
164 if (cycles <= end - start)
165 break;
166
167 cycles -= end - start;
168 start = end;
169 }
170}
171
172void __init use_tsc_delay(void)
173{
174 if (delay_fn == delay_loop)
175 delay_fn = delay_tsc;
176}
177
178void __init use_tpause_delay(void)
179{
180 delay_halt_fn = delay_halt_tpause;
181 delay_fn = delay_halt;
182}
183
184void use_mwaitx_delay(void)
185{
186 delay_halt_fn = delay_halt_mwaitx;
187 delay_fn = delay_halt;
188}
189
190bool delay_read_timer(unsigned long *timer_val)
191{
192 if (delay_fn == delay_tsc) {
193 *timer_val = rdtsc();
194 return true;
195 }
196 return false;
197}
198
199void __delay(unsigned long loops)
200{
201 delay_fn(loops);
202}
203EXPORT_SYMBOL(__delay);
204
205noinline void __const_udelay(unsigned long xloops)
206{
207 unsigned long lpj = this_cpu_read(cpu_info.loops_per_jiffy) ? : loops_per_jiffy;
208 int d0;
209
210 xloops *= 4;
211 asm("mull %%edx"
212 :"=d" (xloops), "=&a" (d0)
213 :"1" (xloops), "0" (lpj * (HZ / 4)));
214
215 __delay(++xloops);
216}
217EXPORT_SYMBOL(__const_udelay);
218
219void __udelay(unsigned long usecs)
220{
221 __const_udelay(usecs * 0x000010c7); /* 2**32 / 1000000 (rounded up) */
222}
223EXPORT_SYMBOL(__udelay);
224
225void __ndelay(unsigned long nsecs)
226{
227 __const_udelay(nsecs * 0x00005); /* 2**32 / 1000000000 (rounded up) */
228}
229EXPORT_SYMBOL(__ndelay);