| 1 | |
| 2 | |
| 3 | * linux/arch/xtensa/kernel/irq.c
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| 4 | *
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| 5 | * Xtensa built-in interrupt controller and some generic functions copied
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| 6 | * from i386.
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| 7 | *
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| 8 | * Copyright (C) 2002 - 2013 Tensilica, Inc.
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| 9 | * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
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| 10 | *
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| 11 | *
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| 12 | * Chris Zankel <[email protected]>
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| 13 | * Kevin Chea
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| 14 | *
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| 15 |
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| 16 |
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| 17 | #include <linux/module.h>
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| 18 | #include <linux/seq_file.h>
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| 19 | #include <linux/interrupt.h>
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| 20 | #include <linux/irq.h>
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| 21 | #include <linux/kernel_stat.h>
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| 22 | #include <linux/irqchip.h>
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| 23 | #include <linux/irqchip/xtensa-mx.h>
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| 24 | #include <linux/irqchip/xtensa-pic.h>
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| 25 | #include <linux/irqdomain.h>
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| 26 | #include <linux/of.h>
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| 27 |
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| 28 | #include <asm/mxregs.h>
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| 29 | #include <linux/uaccess.h>
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| 30 | #include <asm/platform.h>
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| 31 | #include <asm/traps.h>
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| 32 |
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| 33 | DECLARE_PER_CPU(unsigned long, nmi_count);
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| 34 |
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| 35 | asmlinkage void do_IRQ(int hwirq, struct pt_regs *regs)
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| 36 | {
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| 37 | #ifdef CONFIG_DEBUG_STACKOVERFLOW
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| 38 |
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| 39 | {
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| 40 | unsigned long sp = current_stack_pointer;
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| 41 |
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| 42 | sp &= THREAD_SIZE - 1;
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| 43 |
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| 44 | if (unlikely(sp < (sizeof(thread_info) + 1024)))
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| 45 | printk("Stack overflow in do_IRQ: %ld\n",
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| 46 | sp - sizeof(struct thread_info));
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| 47 | }
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| 48 | #endif
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| 49 | generic_handle_domain_irq(NULL, hwirq);
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| 50 | }
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| 51 |
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| 52 | int arch_show_interrupts(struct seq_file *p, int prec)
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| 53 | {
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| 54 | unsigned cpu __maybe_unused;
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| 55 | #ifdef CONFIG_SMP
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| 56 | show_ipi_list(p, prec);
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| 57 | #endif
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| 58 | #if XTENSA_FAKE_NMI
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| 59 | seq_printf(p, "%*s:", prec, "NMI");
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| 60 | for_each_online_cpu(cpu)
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| 61 | seq_printf(p, " %10lu", per_cpu(nmi_count, cpu));
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| 62 | seq_puts(p, " Non-maskable interrupts\n");
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| 63 | #endif
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| 64 | return 0;
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| 65 | }
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| 66 |
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| 67 | int xtensa_irq_domain_xlate(const u32 *intspec, unsigned int intsize,
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| 68 | unsigned long int_irq, unsigned long ext_irq,
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| 69 | unsigned long *out_hwirq, unsigned int *out_type)
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| 70 | {
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| 71 | if (WARN_ON(intsize < 1 || intsize > 2))
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| 72 | return -EINVAL;
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| 73 | if (intsize == 2 && intspec[1] == 1) {
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| 74 | int_irq = xtensa_map_ext_irq(ext_irq);
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| 75 | if (int_irq < XCHAL_NUM_INTERRUPTS)
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| 76 | *out_hwirq = int_irq;
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| 77 | else
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| 78 | return -EINVAL;
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| 79 | } else {
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| 80 | *out_hwirq = int_irq;
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| 81 | }
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| 82 | *out_type = IRQ_TYPE_NONE;
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| 83 | return 0;
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| 84 | }
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| 85 |
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| 86 | int xtensa_irq_map(struct irq_domain *d, unsigned int irq,
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| 87 | irq_hw_number_t hw)
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| 88 | {
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| 89 | struct irq_chip *irq_chip = d->host_data;
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| 90 | u32 mask = 1 << hw;
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| 91 |
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| 92 | if (mask & XCHAL_INTTYPE_MASK_SOFTWARE) {
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| 93 | irq_set_chip_and_handler_name(irq, irq_chip,
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| 94 | handle_simple_irq, "level");
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| 95 | irq_set_status_flags(irq, IRQ_LEVEL);
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| 96 | } else if (mask & XCHAL_INTTYPE_MASK_EXTERN_EDGE) {
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| 97 | irq_set_chip_and_handler_name(irq, irq_chip,
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| 98 | handle_edge_irq, "edge");
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| 99 | irq_clear_status_flags(irq, IRQ_LEVEL);
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| 100 | } else if (mask & XCHAL_INTTYPE_MASK_EXTERN_LEVEL) {
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| 101 | irq_set_chip_and_handler_name(irq, irq_chip,
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| 102 | handle_level_irq, "level");
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| 103 | irq_set_status_flags(irq, IRQ_LEVEL);
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| 104 | } else if (mask & XCHAL_INTTYPE_MASK_TIMER) {
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| 105 | irq_set_chip_and_handler_name(irq, irq_chip,
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| 106 | handle_percpu_irq, "timer");
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| 107 | irq_clear_status_flags(irq, IRQ_LEVEL);
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| 108 | #ifdef XCHAL_INTTYPE_MASK_PROFILING
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| 109 | } else if (mask & XCHAL_INTTYPE_MASK_PROFILING) {
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| 110 | irq_set_chip_and_handler_name(irq, irq_chip,
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| 111 | handle_percpu_irq, "profiling");
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| 112 | irq_set_status_flags(irq, IRQ_LEVEL);
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| 113 | #endif
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| 114 | } else {
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| 115 |
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| 116 | irq_set_chip_and_handler_name(irq, irq_chip,
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| 117 | handle_level_irq, "level");
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| 118 | irq_set_status_flags(irq, IRQ_LEVEL);
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| 119 | }
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| 120 | return 0;
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| 121 | }
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| 122 |
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| 123 | unsigned xtensa_map_ext_irq(unsigned ext_irq)
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| 124 | {
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| 125 | unsigned mask = XCHAL_INTTYPE_MASK_EXTERN_EDGE |
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| 126 | XCHAL_INTTYPE_MASK_EXTERN_LEVEL;
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| 127 | unsigned i;
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| 128 |
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| 129 | for (i = 0; mask; ++i, mask >>= 1) {
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| 130 | if ((mask & 1) && ext_irq-- == 0)
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| 131 | return i;
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| 132 | }
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| 133 | return XCHAL_NUM_INTERRUPTS;
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| 134 | }
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| 135 |
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| 136 | unsigned xtensa_get_ext_irq_no(unsigned irq)
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| 137 | {
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| 138 | unsigned mask = (XCHAL_INTTYPE_MASK_EXTERN_EDGE |
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| 139 | XCHAL_INTTYPE_MASK_EXTERN_LEVEL) &
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| 140 | ((1u << irq) - 1);
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| 141 | return hweight32(mask);
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| 142 | }
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| 143 |
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| 144 | void __init init_IRQ(void)
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| 145 | {
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| 146 | #ifdef CONFIG_USE_OF
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| 147 | irqchip_init();
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| 148 | #else
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| 149 | #ifdef CONFIG_HAVE_SMP
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| 150 | xtensa_mx_init_legacy(NULL);
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| 151 | #else
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| 152 | xtensa_pic_init_legacy(NULL);
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| 153 | #endif
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| 154 | #endif
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| 155 |
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| 156 | #ifdef CONFIG_SMP
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| 157 | ipi_init();
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| 158 | #endif
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| 159 | }
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| 160 |
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| 161 | #ifdef CONFIG_HOTPLUG_CPU
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| 162 | |
| 163 | * The CPU has been marked offline. Migrate IRQs off this CPU. If
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| 164 | * the affinity settings do not allow other CPUs, force them onto any
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| 165 | * available CPU.
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| 166 |
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| 167 | void migrate_irqs(void)
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| 168 | {
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| 169 | unsigned int i, cpu = smp_processor_id();
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| 170 |
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| 171 | for_each_active_irq(i) {
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| 172 | struct irq_data *data = irq_get_irq_data(i);
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| 173 | const struct cpumask *mask;
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| 174 | unsigned int newcpu;
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| 175 |
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| 176 | if (irqd_is_per_cpu(data))
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| 177 | continue;
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| 178 |
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| 179 | mask = irq_data_get_affinity_mask(data);
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| 180 | if (!cpumask_test_cpu(cpu, mask))
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| 181 | continue;
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| 182 |
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| 183 | newcpu = cpumask_any_and(mask, cpu_online_mask);
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| 184 |
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| 185 | if (newcpu >= nr_cpu_ids) {
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| 186 | pr_info_ratelimited("IRQ%u no longer affine to CPU%u\n",
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| 187 | i, cpu);
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| 188 |
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| 189 | irq_set_affinity(i, cpu_all_mask);
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| 190 | } else {
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| 191 | irq_set_affinity(i, mask);
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| 192 | }
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| 193 | }
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| 194 | }
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| 195 | #endif
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