| 1 | /*
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| 2 | * Xtensa Secondary Processors startup code.
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| 3 | *
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| 4 | * This file is subject to the terms and conditions of the GNU General Public
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| 5 | * License. See the file "COPYING" in the main directory of this archive
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| 6 | * for more details.
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| 7 | *
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| 8 | * Copyright (C) 2001 - 2013 Tensilica Inc.
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| 9 | *
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| 10 | * Joe Taylor <joe@tensilica.com>
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| 11 | * Chris Zankel <chris@zankel.net>
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| 12 | * Marc Gauthier <marc@tensilica.com, marc@alumni.uwaterloo.ca>
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| 13 | * Pete Delaney <piet@tensilica.com>
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| 14 | */
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| 15 |
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| 16 | |
| 17 |
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| 18 | |
| 19 | |
| 20 | |
| 21 | |
| 22 |
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| 23 |
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| 24 | .section .SecondaryResetVector.text, "ax"
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| 25 |
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| 26 |
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| 27 | ENTRY(_SecondaryResetVector)
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| 28 | _j _SetupOCD
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| 29 |
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| 30 | .begin no-absolute-literals
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| 31 | .literal_position
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| 32 |
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| 33 | _SetupOCD:
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| 34 | /*
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| 35 | * Initialize WB, WS, and clear PS.EXCM (to allow loop instructions).
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| 36 | * Set Interrupt Level just below XCHAL_DEBUGLEVEL to allow
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| 37 | * xt-gdb to single step via DEBUG exceptions received directly
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| 38 | * by ocd.
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| 39 | */
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| 40 | |
| 41 | movi a1, 1
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| 42 | movi a0, 0
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| 43 | wsr a1, windowstart
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| 44 | wsr a0, windowbase
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| 45 | rsync
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| 46 | |
| 47 |
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| 48 | movi a1, LOCKLEVEL
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| 49 | wsr a1, ps
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| 50 | rsync
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| 51 |
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| 52 | _SetupMMU:
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| 53 | |
| 54 | initialize_mmu
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| 55 | |
| 56 |
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| 57 | /*
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| 58 | * Start Secondary Processors with NULL pointer to boot params.
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| 59 | */
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| 60 | movi a2, 0 |
| 61 | movi a3, _startup
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| 62 | jx a3
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| 63 |
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| 64 | .end no-absolute-literals
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