| 1 | |
| 2 | |
| 3 | * libata-sff.c - helper library for PCI IDE BMDMA
|
| 4 | *
|
| 5 | * Copyright 2003-2006 Red Hat, Inc. All rights reserved.
|
| 6 | * Copyright 2003-2006 Jeff Garzik
|
| 7 | *
|
| 8 | * libata documentation is available via 'make {ps|pdf}docs',
|
| 9 | * as Documentation/driver-api/libata.rst
|
| 10 | *
|
| 11 | * Hardware documentation available from http://www.t13.org/ and
|
| 12 | * http://www.sata-io.org/
|
| 13 |
|
| 14 |
|
| 15 | #include <linux/kernel.h>
|
| 16 | #include <linux/gfp.h>
|
| 17 | #include <linux/pci.h>
|
| 18 | #include <linux/module.h>
|
| 19 | #include <linux/libata.h>
|
| 20 | #include <linux/highmem.h>
|
| 21 | #include <trace/events/libata.h>
|
| 22 | #include "libata.h"
|
| 23 |
|
| 24 | static struct workqueue_struct *ata_sff_wq;
|
| 25 |
|
| 26 | const struct ata_port_operations ata_sff_port_ops = {
|
| 27 | .inherits = &ata_base_port_ops,
|
| 28 |
|
| 29 | .qc_issue = ata_sff_qc_issue,
|
| 30 | .qc_fill_rtf = ata_sff_qc_fill_rtf,
|
| 31 |
|
| 32 | .freeze = ata_sff_freeze,
|
| 33 | .thaw = ata_sff_thaw,
|
| 34 | .reset.prereset = ata_sff_prereset,
|
| 35 | .reset.softreset = ata_sff_softreset,
|
| 36 | .reset.hardreset = sata_sff_hardreset,
|
| 37 | .reset.postreset = ata_sff_postreset,
|
| 38 | .error_handler = ata_sff_error_handler,
|
| 39 |
|
| 40 | .sff_dev_select = ata_sff_dev_select,
|
| 41 | .sff_check_status = ata_sff_check_status,
|
| 42 | .sff_tf_load = ata_sff_tf_load,
|
| 43 | .sff_tf_read = ata_sff_tf_read,
|
| 44 | .sff_exec_command = ata_sff_exec_command,
|
| 45 | .sff_data_xfer = ata_sff_data_xfer,
|
| 46 | .sff_drain_fifo = ata_sff_drain_fifo,
|
| 47 |
|
| 48 | .lost_interrupt = ata_sff_lost_interrupt,
|
| 49 | };
|
| 50 | EXPORT_SYMBOL_GPL(ata_sff_port_ops);
|
| 51 |
|
| 52 | |
| 53 | * ata_sff_check_status - Read device status reg & clear interrupt
|
| 54 | * @ap: port where the device is
|
| 55 | *
|
| 56 | * Reads ATA taskfile status register for currently-selected device
|
| 57 | * and return its value. This also clears pending interrupts
|
| 58 | * from this device
|
| 59 | *
|
| 60 | * LOCKING:
|
| 61 | * Inherited from caller.
|
| 62 |
|
| 63 | u8 ata_sff_check_status(struct ata_port *ap)
|
| 64 | {
|
| 65 | return ioread8(ap->ioaddr.status_addr);
|
| 66 | }
|
| 67 | EXPORT_SYMBOL_GPL(ata_sff_check_status);
|
| 68 |
|
| 69 | |
| 70 | * ata_sff_altstatus - Read device alternate status reg
|
| 71 | * @ap: port where the device is
|
| 72 | * @status: pointer to a status value
|
| 73 | *
|
| 74 | * Reads ATA alternate status register for currently-selected device
|
| 75 | * and return its value.
|
| 76 | *
|
| 77 | * RETURN:
|
| 78 | * true if the register exists, false if not.
|
| 79 | *
|
| 80 | * LOCKING:
|
| 81 | * Inherited from caller.
|
| 82 |
|
| 83 | static bool ata_sff_altstatus(struct ata_port *ap, u8 *status)
|
| 84 | {
|
| 85 | u8 tmp;
|
| 86 |
|
| 87 | if (ap->ops->sff_check_altstatus) {
|
| 88 | tmp = ap->ops->sff_check_altstatus(ap);
|
| 89 | goto read;
|
| 90 | }
|
| 91 | if (ap->ioaddr.altstatus_addr) {
|
| 92 | tmp = ioread8(ap->ioaddr.altstatus_addr);
|
| 93 | goto read;
|
| 94 | }
|
| 95 | return false;
|
| 96 |
|
| 97 | read:
|
| 98 | if (status)
|
| 99 | *status = tmp;
|
| 100 | return true;
|
| 101 | }
|
| 102 |
|
| 103 | |
| 104 | * ata_sff_irq_status - Check if the device is busy
|
| 105 | * @ap: port where the device is
|
| 106 | *
|
| 107 | * Determine if the port is currently busy. Uses altstatus
|
| 108 | * if available in order to avoid clearing shared IRQ status
|
| 109 | * when finding an IRQ source. Non ctl capable devices don't
|
| 110 | * share interrupt lines fortunately for us.
|
| 111 | *
|
| 112 | * LOCKING:
|
| 113 | * Inherited from caller.
|
| 114 |
|
| 115 | static u8 ata_sff_irq_status(struct ata_port *ap)
|
| 116 | {
|
| 117 | u8 status;
|
| 118 |
|
| 119 |
|
| 120 | if (ata_sff_altstatus(ap, &status) && (status & ATA_BUSY))
|
| 121 | return status;
|
| 122 |
|
| 123 | status = ap->ops->sff_check_status(ap);
|
| 124 | return status;
|
| 125 | }
|
| 126 |
|
| 127 | |
| 128 | * ata_sff_sync - Flush writes
|
| 129 | * @ap: Port to wait for.
|
| 130 | *
|
| 131 | * CAUTION:
|
| 132 | * If we have an mmio device with no ctl and no altstatus
|
| 133 | * method this will fail. No such devices are known to exist.
|
| 134 | *
|
| 135 | * LOCKING:
|
| 136 | * Inherited from caller.
|
| 137 |
|
| 138 |
|
| 139 | static void ata_sff_sync(struct ata_port *ap)
|
| 140 | {
|
| 141 | ata_sff_altstatus(ap, NULL);
|
| 142 | }
|
| 143 |
|
| 144 | |
| 145 | * ata_sff_pause - Flush writes and wait 400nS
|
| 146 | * @ap: Port to pause for.
|
| 147 | *
|
| 148 | * CAUTION:
|
| 149 | * If we have an mmio device with no ctl and no altstatus
|
| 150 | * method this will fail. No such devices are known to exist.
|
| 151 | *
|
| 152 | * LOCKING:
|
| 153 | * Inherited from caller.
|
| 154 |
|
| 155 |
|
| 156 | void ata_sff_pause(struct ata_port *ap)
|
| 157 | {
|
| 158 | ata_sff_sync(ap);
|
| 159 | ndelay(400);
|
| 160 | }
|
| 161 | EXPORT_SYMBOL_GPL(ata_sff_pause);
|
| 162 |
|
| 163 | |
| 164 | * ata_sff_dma_pause - Pause before commencing DMA
|
| 165 | * @ap: Port to pause for.
|
| 166 | *
|
| 167 | * Perform I/O fencing and ensure sufficient cycle delays occur
|
| 168 | * for the HDMA1:0 transition
|
| 169 |
|
| 170 |
|
| 171 | void ata_sff_dma_pause(struct ata_port *ap)
|
| 172 | {
|
| 173 | |
| 174 | * An altstatus read will cause the needed delay without
|
| 175 | * messing up the IRQ status
|
| 176 |
|
| 177 | if (ata_sff_altstatus(ap, NULL))
|
| 178 | return;
|
| 179 | |
| 180 | we never violate the HDMA1:0 transition timing and risk
|
| 181 | corruption.
|
| 182 | BUG();
|
| 183 | }
|
| 184 | EXPORT_SYMBOL_GPL(ata_sff_dma_pause);
|
| 185 |
|
| 186 | static int ata_sff_check_ready(struct ata_link *link)
|
| 187 | {
|
| 188 | u8 status = link->ap->ops->sff_check_status(link->ap);
|
| 189 |
|
| 190 | return ata_check_ready(status);
|
| 191 | }
|
| 192 |
|
| 193 | |
| 194 | * ata_sff_wait_ready - sleep until BSY clears, or timeout
|
| 195 | * @link: SFF link to wait ready status for
|
| 196 | * @deadline: deadline jiffies for the operation
|
| 197 | *
|
| 198 | * Sleep until ATA Status register bit BSY clears, or timeout
|
| 199 | * occurs.
|
| 200 | *
|
| 201 | * LOCKING:
|
| 202 | * Kernel thread context (may sleep).
|
| 203 | *
|
| 204 | * RETURNS:
|
| 205 | * 0 on success, -errno otherwise.
|
| 206 |
|
| 207 | int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline)
|
| 208 | {
|
| 209 | return ata_wait_ready(link, deadline, ata_sff_check_ready);
|
| 210 | }
|
| 211 | EXPORT_SYMBOL_GPL(ata_sff_wait_ready);
|
| 212 |
|
| 213 | |
| 214 | * ata_sff_set_devctl - Write device control reg
|
| 215 | * @ap: port where the device is
|
| 216 | * @ctl: value to write
|
| 217 | *
|
| 218 | * Writes ATA device control register.
|
| 219 | *
|
| 220 | * RETURN:
|
| 221 | * true if the register exists, false if not.
|
| 222 | *
|
| 223 | * LOCKING:
|
| 224 | * Inherited from caller.
|
| 225 |
|
| 226 | static bool ata_sff_set_devctl(struct ata_port *ap, u8 ctl)
|
| 227 | {
|
| 228 | if (ap->ops->sff_set_devctl) {
|
| 229 | ap->ops->sff_set_devctl(ap, ctl);
|
| 230 | return true;
|
| 231 | }
|
| 232 | if (ap->ioaddr.ctl_addr) {
|
| 233 | iowrite8(ctl, ap->ioaddr.ctl_addr);
|
| 234 | return true;
|
| 235 | }
|
| 236 |
|
| 237 | return false;
|
| 238 | }
|
| 239 |
|
| 240 | |
| 241 | * ata_sff_dev_select - Select device 0/1 on ATA bus
|
| 242 | * @ap: ATA channel to manipulate
|
| 243 | * @device: ATA device (numbered from zero) to select
|
| 244 | *
|
| 245 | * Use the method defined in the ATA specification to
|
| 246 | * make either device 0, or device 1, active on the
|
| 247 | * ATA channel. Works with both PIO and MMIO.
|
| 248 | *
|
| 249 | * May be used as the dev_select() entry in ata_port_operations.
|
| 250 | *
|
| 251 | * LOCKING:
|
| 252 | * caller.
|
| 253 |
|
| 254 | void ata_sff_dev_select(struct ata_port *ap, unsigned int device)
|
| 255 | {
|
| 256 | u8 tmp;
|
| 257 |
|
| 258 | if (device == 0)
|
| 259 | tmp = ATA_DEVICE_OBS;
|
| 260 | else
|
| 261 | tmp = ATA_DEVICE_OBS | ATA_DEV1;
|
| 262 |
|
| 263 | iowrite8(tmp, ap->ioaddr.device_addr);
|
| 264 | ata_sff_pause(ap);
|
| 265 | }
|
| 266 | EXPORT_SYMBOL_GPL(ata_sff_dev_select);
|
| 267 |
|
| 268 | |
| 269 | * ata_dev_select - Select device 0/1 on ATA bus
|
| 270 | * @ap: ATA channel to manipulate
|
| 271 | * @device: ATA device (numbered from zero) to select
|
| 272 | * @wait: non-zero to wait for Status register BSY bit to clear
|
| 273 | * @can_sleep: non-zero if context allows sleeping
|
| 274 | *
|
| 275 | * Use the method defined in the ATA specification to
|
| 276 | * make either device 0, or device 1, active on the
|
| 277 | * ATA channel.
|
| 278 | *
|
| 279 | * This is a high-level version of ata_sff_dev_select(), which
|
| 280 | * additionally provides the services of inserting the proper
|
| 281 | * pauses and status polling, where needed.
|
| 282 | *
|
| 283 | * LOCKING:
|
| 284 | * caller.
|
| 285 |
|
| 286 | static void ata_dev_select(struct ata_port *ap, unsigned int device,
|
| 287 | unsigned int wait, unsigned int can_sleep)
|
| 288 | {
|
| 289 | if (wait)
|
| 290 | ata_wait_idle(ap);
|
| 291 |
|
| 292 | ap->ops->sff_dev_select(ap, device);
|
| 293 |
|
| 294 | if (wait) {
|
| 295 | if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI)
|
| 296 | ata_msleep(ap, 150);
|
| 297 | ata_wait_idle(ap);
|
| 298 | }
|
| 299 | }
|
| 300 |
|
| 301 | |
| 302 | * ata_sff_irq_on - Enable interrupts on a port.
|
| 303 | * @ap: Port on which interrupts are enabled.
|
| 304 | *
|
| 305 | * Enable interrupts on a legacy IDE device using MMIO or PIO,
|
| 306 | * wait for idle, clear any pending interrupts.
|
| 307 | *
|
| 308 | * Note: may NOT be used as the sff_irq_on() entry in
|
| 309 | * ata_port_operations.
|
| 310 | *
|
| 311 | * LOCKING:
|
| 312 | * Inherited from caller.
|
| 313 |
|
| 314 | void ata_sff_irq_on(struct ata_port *ap)
|
| 315 | {
|
| 316 | if (ap->ops->sff_irq_on) {
|
| 317 | ap->ops->sff_irq_on(ap);
|
| 318 | return;
|
| 319 | }
|
| 320 |
|
| 321 | ap->ctl &= ~ATA_NIEN;
|
| 322 | ap->last_ctl = ap->ctl;
|
| 323 |
|
| 324 | ata_sff_set_devctl(ap, ap->ctl);
|
| 325 | ata_wait_idle(ap);
|
| 326 |
|
| 327 | if (ap->ops->sff_irq_clear)
|
| 328 | ap->ops->sff_irq_clear(ap);
|
| 329 | }
|
| 330 | EXPORT_SYMBOL_GPL(ata_sff_irq_on);
|
| 331 |
|
| 332 | |
| 333 | * ata_sff_tf_load - send taskfile registers to host controller
|
| 334 | * @ap: Port to which output is sent
|
| 335 | * @tf: ATA taskfile register set
|
| 336 | *
|
| 337 | * Outputs ATA taskfile to standard ATA host controller.
|
| 338 | *
|
| 339 | * LOCKING:
|
| 340 | * Inherited from caller.
|
| 341 |
|
| 342 | void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
|
| 343 | {
|
| 344 | struct ata_ioports *ioaddr = &ap->ioaddr;
|
| 345 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
|
| 346 |
|
| 347 | if (tf->ctl != ap->last_ctl) {
|
| 348 | if (ioaddr->ctl_addr)
|
| 349 | iowrite8(tf->ctl, ioaddr->ctl_addr);
|
| 350 | ap->last_ctl = tf->ctl;
|
| 351 | ata_wait_idle(ap);
|
| 352 | }
|
| 353 |
|
| 354 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
|
| 355 | WARN_ON_ONCE(!ioaddr->ctl_addr);
|
| 356 | iowrite8(tf->hob_feature, ioaddr->feature_addr);
|
| 357 | iowrite8(tf->hob_nsect, ioaddr->nsect_addr);
|
| 358 | iowrite8(tf->hob_lbal, ioaddr->lbal_addr);
|
| 359 | iowrite8(tf->hob_lbam, ioaddr->lbam_addr);
|
| 360 | iowrite8(tf->hob_lbah, ioaddr->lbah_addr);
|
| 361 | }
|
| 362 |
|
| 363 | if (is_addr) {
|
| 364 | iowrite8(tf->feature, ioaddr->feature_addr);
|
| 365 | iowrite8(tf->nsect, ioaddr->nsect_addr);
|
| 366 | iowrite8(tf->lbal, ioaddr->lbal_addr);
|
| 367 | iowrite8(tf->lbam, ioaddr->lbam_addr);
|
| 368 | iowrite8(tf->lbah, ioaddr->lbah_addr);
|
| 369 | }
|
| 370 |
|
| 371 | if (tf->flags & ATA_TFLAG_DEVICE)
|
| 372 | iowrite8(tf->device, ioaddr->device_addr);
|
| 373 |
|
| 374 | ata_wait_idle(ap);
|
| 375 | }
|
| 376 | EXPORT_SYMBOL_GPL(ata_sff_tf_load);
|
| 377 |
|
| 378 | |
| 379 | * ata_sff_tf_read - input device's ATA taskfile shadow registers
|
| 380 | * @ap: Port from which input is read
|
| 381 | * @tf: ATA taskfile register set for storing input
|
| 382 | *
|
| 383 | * Reads ATA taskfile registers for currently-selected device
|
| 384 | * into @tf. Assumes the device has a fully SFF compliant task file
|
| 385 | * layout and behaviour. If you device does not (eg has a different
|
| 386 | * status method) then you will need to provide a replacement tf_read
|
| 387 | *
|
| 388 | * LOCKING:
|
| 389 | * Inherited from caller.
|
| 390 |
|
| 391 | void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
|
| 392 | {
|
| 393 | struct ata_ioports *ioaddr = &ap->ioaddr;
|
| 394 |
|
| 395 | tf->status = ata_sff_check_status(ap);
|
| 396 | tf->error = ioread8(ioaddr->error_addr);
|
| 397 | tf->nsect = ioread8(ioaddr->nsect_addr);
|
| 398 | tf->lbal = ioread8(ioaddr->lbal_addr);
|
| 399 | tf->lbam = ioread8(ioaddr->lbam_addr);
|
| 400 | tf->lbah = ioread8(ioaddr->lbah_addr);
|
| 401 | tf->device = ioread8(ioaddr->device_addr);
|
| 402 |
|
| 403 | if (tf->flags & ATA_TFLAG_LBA48) {
|
| 404 | if (likely(ioaddr->ctl_addr)) {
|
| 405 | iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
|
| 406 | tf->hob_feature = ioread8(ioaddr->error_addr);
|
| 407 | tf->hob_nsect = ioread8(ioaddr->nsect_addr);
|
| 408 | tf->hob_lbal = ioread8(ioaddr->lbal_addr);
|
| 409 | tf->hob_lbam = ioread8(ioaddr->lbam_addr);
|
| 410 | tf->hob_lbah = ioread8(ioaddr->lbah_addr);
|
| 411 | iowrite8(tf->ctl, ioaddr->ctl_addr);
|
| 412 | ap->last_ctl = tf->ctl;
|
| 413 | } else
|
| 414 | WARN_ON_ONCE(1);
|
| 415 | }
|
| 416 | }
|
| 417 | EXPORT_SYMBOL_GPL(ata_sff_tf_read);
|
| 418 |
|
| 419 | |
| 420 | * ata_sff_exec_command - issue ATA command to host controller
|
| 421 | * @ap: port to which command is being issued
|
| 422 | * @tf: ATA taskfile register set
|
| 423 | *
|
| 424 | * Issues ATA command, with proper synchronization with interrupt
|
| 425 | * handler / other threads.
|
| 426 | *
|
| 427 | * LOCKING:
|
| 428 | * spin_lock_irqsave(host lock)
|
| 429 |
|
| 430 | void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
|
| 431 | {
|
| 432 | iowrite8(tf->command, ap->ioaddr.command_addr);
|
| 433 | ata_sff_pause(ap);
|
| 434 | }
|
| 435 | EXPORT_SYMBOL_GPL(ata_sff_exec_command);
|
| 436 |
|
| 437 | |
| 438 | * ata_tf_to_host - issue ATA taskfile to host controller
|
| 439 | * @ap: port to which command is being issued
|
| 440 | * @tf: ATA taskfile register set
|
| 441 | * @tag: tag of the associated command
|
| 442 | *
|
| 443 | * Issues ATA taskfile register set to ATA host controller,
|
| 444 | * with proper synchronization with interrupt handler and
|
| 445 | * other threads.
|
| 446 | *
|
| 447 | * LOCKING:
|
| 448 | * spin_lock_irqsave(host lock)
|
| 449 |
|
| 450 | static inline void ata_tf_to_host(struct ata_port *ap,
|
| 451 | const struct ata_taskfile *tf,
|
| 452 | unsigned int tag)
|
| 453 | {
|
| 454 | trace_ata_tf_load(ap, tf);
|
| 455 | ap->ops->sff_tf_load(ap, tf);
|
| 456 | trace_ata_exec_command(ap, tf, tag);
|
| 457 | ap->ops->sff_exec_command(ap, tf);
|
| 458 | }
|
| 459 |
|
| 460 | |
| 461 | * ata_sff_data_xfer - Transfer data by PIO
|
| 462 | * @qc: queued command
|
| 463 | * @buf: data buffer
|
| 464 | * @buflen: buffer length
|
| 465 | * @rw: read/write
|
| 466 | *
|
| 467 | * Transfer data from/to the device data register by PIO.
|
| 468 | *
|
| 469 | * LOCKING:
|
| 470 | * Inherited from caller.
|
| 471 | *
|
| 472 | * RETURNS:
|
| 473 | * Bytes consumed.
|
| 474 |
|
| 475 | unsigned int ata_sff_data_xfer(struct ata_queued_cmd *qc, unsigned char *buf,
|
| 476 | unsigned int buflen, int rw)
|
| 477 | {
|
| 478 | struct ata_port *ap = qc->dev->link->ap;
|
| 479 | void __iomem *data_addr = ap->ioaddr.data_addr;
|
| 480 | unsigned int words = buflen >> 1;
|
| 481 |
|
| 482 |
|
| 483 | if (rw == READ)
|
| 484 | ioread16_rep(data_addr, buf, words);
|
| 485 | else
|
| 486 | iowrite16_rep(data_addr, buf, words);
|
| 487 |
|
| 488 |
|
| 489 | if (unlikely(buflen & 0x01)) {
|
| 490 | unsigned char pad[2] = { };
|
| 491 |
|
| 492 |
|
| 493 | buf += buflen - 1;
|
| 494 |
|
| 495 | |
| 496 | * Use io*16_rep() accessors here as well to avoid pointlessly
|
| 497 | * swapping bytes to and from on the big endian machines...
|
| 498 |
|
| 499 | if (rw == READ) {
|
| 500 | ioread16_rep(data_addr, pad, 1);
|
| 501 | *buf = pad[0];
|
| 502 | } else {
|
| 503 | pad[0] = *buf;
|
| 504 | iowrite16_rep(data_addr, pad, 1);
|
| 505 | }
|
| 506 | words++;
|
| 507 | }
|
| 508 |
|
| 509 | return words << 1;
|
| 510 | }
|
| 511 | EXPORT_SYMBOL_GPL(ata_sff_data_xfer);
|
| 512 |
|
| 513 | |
| 514 | * ata_sff_data_xfer32 - Transfer data by PIO
|
| 515 | * @qc: queued command
|
| 516 | * @buf: data buffer
|
| 517 | * @buflen: buffer length
|
| 518 | * @rw: read/write
|
| 519 | *
|
| 520 | * Transfer data from/to the device data register by PIO using 32bit
|
| 521 | * I/O operations.
|
| 522 | *
|
| 523 | * LOCKING:
|
| 524 | * Inherited from caller.
|
| 525 | *
|
| 526 | * RETURNS:
|
| 527 | * Bytes consumed.
|
| 528 |
|
| 529 |
|
| 530 | unsigned int ata_sff_data_xfer32(struct ata_queued_cmd *qc, unsigned char *buf,
|
| 531 | unsigned int buflen, int rw)
|
| 532 | {
|
| 533 | struct ata_device *dev = qc->dev;
|
| 534 | struct ata_port *ap = dev->link->ap;
|
| 535 | void __iomem *data_addr = ap->ioaddr.data_addr;
|
| 536 | unsigned int words = buflen >> 2;
|
| 537 | int slop = buflen & 3;
|
| 538 |
|
| 539 | if (!(ap->pflags & ATA_PFLAG_PIO32))
|
| 540 | return ata_sff_data_xfer(qc, buf, buflen, rw);
|
| 541 |
|
| 542 |
|
| 543 | if (rw == READ)
|
| 544 | ioread32_rep(data_addr, buf, words);
|
| 545 | else
|
| 546 | iowrite32_rep(data_addr, buf, words);
|
| 547 |
|
| 548 |
|
| 549 | if (unlikely(slop)) {
|
| 550 | unsigned char pad[4] = { };
|
| 551 |
|
| 552 |
|
| 553 | buf += buflen - slop;
|
| 554 |
|
| 555 | |
| 556 | * Use io*_rep() accessors here as well to avoid pointlessly
|
| 557 | * swapping bytes to and from on the big endian machines...
|
| 558 |
|
| 559 | if (rw == READ) {
|
| 560 | if (slop < 3)
|
| 561 | ioread16_rep(data_addr, pad, 1);
|
| 562 | else
|
| 563 | ioread32_rep(data_addr, pad, 1);
|
| 564 | memcpy(buf, pad, slop);
|
| 565 | } else {
|
| 566 | memcpy(pad, buf, slop);
|
| 567 | if (slop < 3)
|
| 568 | iowrite16_rep(data_addr, pad, 1);
|
| 569 | else
|
| 570 | iowrite32_rep(data_addr, pad, 1);
|
| 571 | }
|
| 572 | }
|
| 573 | return (buflen + 1) & ~1;
|
| 574 | }
|
| 575 | EXPORT_SYMBOL_GPL(ata_sff_data_xfer32);
|
| 576 |
|
| 577 | static void ata_pio_xfer(struct ata_queued_cmd *qc, struct page *page,
|
| 578 | unsigned int offset, size_t xfer_size)
|
| 579 | {
|
| 580 | bool do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
|
| 581 | unsigned char *buf;
|
| 582 |
|
| 583 | buf = kmap_atomic(page);
|
| 584 | qc->ap->ops->sff_data_xfer(qc, buf + offset, xfer_size, do_write);
|
| 585 | kunmap_atomic(buf);
|
| 586 |
|
| 587 | if (!do_write && !PageSlab(page))
|
| 588 | flush_dcache_page(page);
|
| 589 | }
|
| 590 |
|
| 591 | |
| 592 | * ata_pio_sector - Transfer a sector of data.
|
| 593 | * @qc: Command on going
|
| 594 | *
|
| 595 | * Transfer qc->sect_size bytes of data from/to the ATA device.
|
| 596 | *
|
| 597 | * LOCKING:
|
| 598 | * Inherited from caller.
|
| 599 |
|
| 600 | static void ata_pio_sector(struct ata_queued_cmd *qc)
|
| 601 | {
|
| 602 | struct ata_port *ap = qc->ap;
|
| 603 | struct page *page;
|
| 604 | unsigned int offset, count;
|
| 605 |
|
| 606 | if (!qc->cursg) {
|
| 607 | qc->curbytes = qc->nbytes;
|
| 608 | return;
|
| 609 | }
|
| 610 | if (qc->curbytes == qc->nbytes - qc->sect_size)
|
| 611 | ap->hsm_task_state = HSM_ST_LAST;
|
| 612 |
|
| 613 | page = sg_page(qc->cursg);
|
| 614 | offset = qc->cursg->offset + qc->cursg_ofs;
|
| 615 |
|
| 616 |
|
| 617 | page += offset >> PAGE_SHIFT;
|
| 618 | offset %= PAGE_SIZE;
|
| 619 |
|
| 620 |
|
| 621 | count = min(qc->cursg->length - qc->cursg_ofs, qc->sect_size);
|
| 622 |
|
| 623 | trace_ata_sff_pio_transfer_data(qc, offset, count);
|
| 624 |
|
| 625 | |
| 626 | * Split the transfer when it splits a page boundary. Note that the
|
| 627 | * split still has to be dword aligned like all ATA data transfers.
|
| 628 |
|
| 629 | WARN_ON_ONCE(offset % 4);
|
| 630 | if (offset + count > PAGE_SIZE) {
|
| 631 | unsigned int split_len = PAGE_SIZE - offset;
|
| 632 |
|
| 633 | ata_pio_xfer(qc, page, offset, split_len);
|
| 634 | ata_pio_xfer(qc, page + 1, 0, count - split_len);
|
| 635 | } else {
|
| 636 | ata_pio_xfer(qc, page, offset, count);
|
| 637 | }
|
| 638 |
|
| 639 | qc->curbytes += count;
|
| 640 | qc->cursg_ofs += count;
|
| 641 |
|
| 642 | if (qc->cursg_ofs == qc->cursg->length) {
|
| 643 | qc->cursg = sg_next(qc->cursg);
|
| 644 | if (!qc->cursg)
|
| 645 | ap->hsm_task_state = HSM_ST_LAST;
|
| 646 | qc->cursg_ofs = 0;
|
| 647 | }
|
| 648 | }
|
| 649 |
|
| 650 | |
| 651 | * ata_pio_sectors - Transfer one or many sectors.
|
| 652 | * @qc: Command on going
|
| 653 | *
|
| 654 | * Transfer one or many sectors of data from/to the
|
| 655 | * ATA device for the DRQ request.
|
| 656 | *
|
| 657 | * LOCKING:
|
| 658 | * Inherited from caller.
|
| 659 |
|
| 660 | static void ata_pio_sectors(struct ata_queued_cmd *qc)
|
| 661 | {
|
| 662 | if (is_multi_taskfile(&qc->tf)) {
|
| 663 |
|
| 664 | unsigned int nsect;
|
| 665 |
|
| 666 | WARN_ON_ONCE(qc->dev->multi_count == 0);
|
| 667 |
|
| 668 | nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size,
|
| 669 | qc->dev->multi_count);
|
| 670 | while (nsect--)
|
| 671 | ata_pio_sector(qc);
|
| 672 | } else
|
| 673 | ata_pio_sector(qc);
|
| 674 |
|
| 675 | ata_sff_sync(qc->ap);
|
| 676 | }
|
| 677 |
|
| 678 | |
| 679 | * atapi_send_cdb - Write CDB bytes to hardware
|
| 680 | * @ap: Port to which ATAPI device is attached.
|
| 681 | * @qc: Taskfile currently active
|
| 682 | *
|
| 683 | * When device has indicated its readiness to accept
|
| 684 | * a CDB, this function is called. Send the CDB.
|
| 685 | *
|
| 686 | * LOCKING:
|
| 687 | * caller.
|
| 688 |
|
| 689 | static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
|
| 690 | {
|
| 691 |
|
| 692 | trace_atapi_send_cdb(qc, 0, qc->dev->cdb_len);
|
| 693 | WARN_ON_ONCE(qc->dev->cdb_len < 12);
|
| 694 |
|
| 695 | ap->ops->sff_data_xfer(qc, qc->cdb, qc->dev->cdb_len, 1);
|
| 696 | ata_sff_sync(ap);
|
| 697 | |
| 698 | or is bmdma_start guaranteed to do it ?
|
| 699 | switch (qc->tf.protocol) {
|
| 700 | case ATAPI_PROT_PIO:
|
| 701 | ap->hsm_task_state = HSM_ST;
|
| 702 | break;
|
| 703 | case ATAPI_PROT_NODATA:
|
| 704 | ap->hsm_task_state = HSM_ST_LAST;
|
| 705 | break;
|
| 706 | #ifdef CONFIG_ATA_BMDMA
|
| 707 | case ATAPI_PROT_DMA:
|
| 708 | ap->hsm_task_state = HSM_ST_LAST;
|
| 709 |
|
| 710 | trace_ata_bmdma_start(ap, &qc->tf, qc->tag);
|
| 711 | ap->ops->bmdma_start(qc);
|
| 712 | break;
|
| 713 | #endif
|
| 714 | default:
|
| 715 | BUG();
|
| 716 | }
|
| 717 | }
|
| 718 |
|
| 719 | |
| 720 | * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
|
| 721 | * @qc: Command on going
|
| 722 | * @bytes: number of bytes
|
| 723 | *
|
| 724 | * Transfer data from/to the ATAPI device.
|
| 725 | *
|
| 726 | * LOCKING:
|
| 727 | * Inherited from caller.
|
| 728 | *
|
| 729 |
|
| 730 | static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
|
| 731 | {
|
| 732 | int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ;
|
| 733 | struct ata_port *ap = qc->ap;
|
| 734 | struct ata_device *dev = qc->dev;
|
| 735 | struct ata_eh_info *ehi = &dev->link->eh_info;
|
| 736 | struct scatterlist *sg;
|
| 737 | struct page *page;
|
| 738 | unsigned char *buf;
|
| 739 | unsigned int offset, count, consumed;
|
| 740 |
|
| 741 | next_sg:
|
| 742 | sg = qc->cursg;
|
| 743 | if (unlikely(!sg)) {
|
| 744 | ata_ehi_push_desc(ehi, "unexpected or too much trailing data "
|
| 745 | "buf=%u cur=%u bytes=%u",
|
| 746 | qc->nbytes, qc->curbytes, bytes);
|
| 747 | return -1;
|
| 748 | }
|
| 749 |
|
| 750 | page = sg_page(sg);
|
| 751 | offset = sg->offset + qc->cursg_ofs;
|
| 752 |
|
| 753 |
|
| 754 | page += offset >> PAGE_SHIFT;
|
| 755 | offset %= PAGE_SIZE;
|
| 756 |
|
| 757 |
|
| 758 | count = min(sg->length - qc->cursg_ofs, bytes);
|
| 759 |
|
| 760 |
|
| 761 | count = min(count, (unsigned int)PAGE_SIZE - offset);
|
| 762 |
|
| 763 | trace_atapi_pio_transfer_data(qc, offset, count);
|
| 764 |
|
| 765 |
|
| 766 | buf = kmap_atomic(page);
|
| 767 | consumed = ap->ops->sff_data_xfer(qc, buf + offset, count, rw);
|
| 768 | kunmap_atomic(buf);
|
| 769 |
|
| 770 | bytes -= min(bytes, consumed);
|
| 771 | qc->curbytes += count;
|
| 772 | qc->cursg_ofs += count;
|
| 773 |
|
| 774 | if (qc->cursg_ofs == sg->length) {
|
| 775 | qc->cursg = sg_next(qc->cursg);
|
| 776 | qc->cursg_ofs = 0;
|
| 777 | }
|
| 778 |
|
| 779 | |
| 780 | * There used to be a WARN_ON_ONCE(qc->cursg && count != consumed);
|
| 781 | * Unfortunately __atapi_pio_bytes doesn't know enough to do the WARN
|
| 782 | * check correctly as it doesn't know if it is the last request being
|
| 783 | * made. Somebody should implement a proper sanity check.
|
| 784 |
|
| 785 | if (bytes)
|
| 786 | goto next_sg;
|
| 787 | return 0;
|
| 788 | }
|
| 789 |
|
| 790 | |
| 791 | * atapi_pio_bytes - Transfer data from/to the ATAPI device.
|
| 792 | * @qc: Command on going
|
| 793 | *
|
| 794 | * Transfer Transfer data from/to the ATAPI device.
|
| 795 | *
|
| 796 | * LOCKING:
|
| 797 | * Inherited from caller.
|
| 798 |
|
| 799 | static void atapi_pio_bytes(struct ata_queued_cmd *qc)
|
| 800 | {
|
| 801 | struct ata_port *ap = qc->ap;
|
| 802 | struct ata_device *dev = qc->dev;
|
| 803 | struct ata_eh_info *ehi = &dev->link->eh_info;
|
| 804 | unsigned int ireason, bc_lo, bc_hi, bytes;
|
| 805 | int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
|
| 806 |
|
| 807 | |
| 808 | * here to save some kernel stack usage.
|
| 809 | * For normal completion, qc->result_tf is not relevant. For
|
| 810 | * error, qc->result_tf is later overwritten by ata_qc_complete().
|
| 811 | * So, the correctness of qc->result_tf is not affected.
|
| 812 |
|
| 813 | ap->ops->sff_tf_read(ap, &qc->result_tf);
|
| 814 | ireason = qc->result_tf.nsect;
|
| 815 | bc_lo = qc->result_tf.lbam;
|
| 816 | bc_hi = qc->result_tf.lbah;
|
| 817 | bytes = (bc_hi << 8) | bc_lo;
|
| 818 |
|
| 819 |
|
| 820 | if (unlikely(ireason & ATAPI_COD))
|
| 821 | goto atapi_check;
|
| 822 |
|
| 823 |
|
| 824 | i_write = ((ireason & ATAPI_IO) == 0) ? 1 : 0;
|
| 825 | if (unlikely(do_write != i_write))
|
| 826 | goto atapi_check;
|
| 827 |
|
| 828 | if (unlikely(!bytes))
|
| 829 | goto atapi_check;
|
| 830 |
|
| 831 | if (unlikely(__atapi_pio_bytes(qc, bytes)))
|
| 832 | goto err_out;
|
| 833 | ata_sff_sync(ap);
|
| 834 |
|
| 835 | return;
|
| 836 |
|
| 837 | atapi_check:
|
| 838 | ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)",
|
| 839 | ireason, bytes);
|
| 840 | err_out:
|
| 841 | qc->err_mask |= AC_ERR_HSM;
|
| 842 | ap->hsm_task_state = HSM_ST_ERR;
|
| 843 | }
|
| 844 |
|
| 845 | |
| 846 | * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue.
|
| 847 | * @ap: the target ata_port
|
| 848 | * @qc: qc on going
|
| 849 | *
|
| 850 | * RETURNS:
|
| 851 | * 1 if ok in workqueue, 0 otherwise.
|
| 852 |
|
| 853 | static inline int ata_hsm_ok_in_wq(struct ata_port *ap,
|
| 854 | struct ata_queued_cmd *qc)
|
| 855 | {
|
| 856 | if (qc->tf.flags & ATA_TFLAG_POLLING)
|
| 857 | return 1;
|
| 858 |
|
| 859 | if (ap->hsm_task_state == HSM_ST_FIRST) {
|
| 860 | if (qc->tf.protocol == ATA_PROT_PIO &&
|
| 861 | (qc->tf.flags & ATA_TFLAG_WRITE))
|
| 862 | return 1;
|
| 863 |
|
| 864 | if (ata_is_atapi(qc->tf.protocol) &&
|
| 865 | !(qc->dev->flags & ATA_DFLAG_CDB_INTR))
|
| 866 | return 1;
|
| 867 | }
|
| 868 |
|
| 869 | return 0;
|
| 870 | }
|
| 871 |
|
| 872 | |
| 873 | * ata_hsm_qc_complete - finish a qc running on standard HSM
|
| 874 | * @qc: Command to complete
|
| 875 | * @in_wq: 1 if called from workqueue, 0 otherwise
|
| 876 | *
|
| 877 | * Finish @qc which is running on standard HSM.
|
| 878 | *
|
| 879 | * LOCKING:
|
| 880 | * If @in_wq is zero, spin_lock_irqsave(host lock).
|
| 881 | * Otherwise, none on entry and grabs host lock.
|
| 882 |
|
| 883 | static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
|
| 884 | {
|
| 885 | struct ata_port *ap = qc->ap;
|
| 886 |
|
| 887 | if (in_wq) {
|
| 888 |
|
| 889 | qc = ata_qc_from_tag(ap, qc->tag);
|
| 890 | if (qc) {
|
| 891 | if (likely(!(qc->err_mask & AC_ERR_HSM))) {
|
| 892 | ata_sff_irq_on(ap);
|
| 893 | ata_qc_complete(qc);
|
| 894 | } else
|
| 895 | ata_port_freeze(ap);
|
| 896 | }
|
| 897 | } else {
|
| 898 | if (likely(!(qc->err_mask & AC_ERR_HSM)))
|
| 899 | ata_qc_complete(qc);
|
| 900 | else
|
| 901 | ata_port_freeze(ap);
|
| 902 | }
|
| 903 | }
|
| 904 |
|
| 905 | |
| 906 | * ata_sff_hsm_move - move the HSM to the next state.
|
| 907 | * @ap: the target ata_port
|
| 908 | * @qc: qc on going
|
| 909 | * @status: current device status
|
| 910 | * @in_wq: 1 if called from workqueue, 0 otherwise
|
| 911 | *
|
| 912 | * RETURNS:
|
| 913 | * 1 when poll next status needed, 0 otherwise.
|
| 914 |
|
| 915 | int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
|
| 916 | u8 status, int in_wq)
|
| 917 | {
|
| 918 | struct ata_link *link = qc->dev->link;
|
| 919 | struct ata_eh_info *ehi = &link->eh_info;
|
| 920 | int poll_next;
|
| 921 |
|
| 922 | lockdep_assert_held(ap->lock);
|
| 923 |
|
| 924 | WARN_ON_ONCE((qc->flags & ATA_QCFLAG_ACTIVE) == 0);
|
| 925 |
|
| 926 | |
| 927 | * like DMA polling into the workqueue. Notice that
|
| 928 | * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING).
|
| 929 |
|
| 930 | WARN_ON_ONCE(in_wq != ata_hsm_ok_in_wq(ap, qc));
|
| 931 |
|
| 932 | fsm_start:
|
| 933 | trace_ata_sff_hsm_state(qc, status);
|
| 934 |
|
| 935 | switch (ap->hsm_task_state) {
|
| 936 | case HSM_ST_FIRST:
|
| 937 |
|
| 938 |
|
| 939 | |
| 940 | * sending the data. Otherwise, interrupt handler
|
| 941 | * takes over after sending the data.
|
| 942 |
|
| 943 | poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
|
| 944 |
|
| 945 |
|
| 946 | if (unlikely((status & ATA_DRQ) == 0)) {
|
| 947 |
|
| 948 | if (likely(status & (ATA_ERR | ATA_DF)))
|
| 949 |
|
| 950 | qc->err_mask |= AC_ERR_DEV;
|
| 951 | else {
|
| 952 |
|
| 953 | ata_ehi_push_desc(ehi,
|
| 954 | "ST_FIRST: !(DRQ|ERR|DF)");
|
| 955 | qc->err_mask |= AC_ERR_HSM;
|
| 956 | }
|
| 957 |
|
| 958 | ap->hsm_task_state = HSM_ST_ERR;
|
| 959 | goto fsm_start;
|
| 960 | }
|
| 961 |
|
| 962 | |
| 963 | * when it finds something wrong.
|
| 964 | * We ignore DRQ here and stop the HSM by
|
| 965 | * changing hsm_task_state to HSM_ST_ERR and
|
| 966 | * let the EH abort the command or reset the device.
|
| 967 |
|
| 968 | if (unlikely(status & (ATA_ERR | ATA_DF))) {
|
| 969 | |
| 970 | * when doing the next command (mostly request sense).
|
| 971 | * We ignore ERR here to workaround and proceed sending
|
| 972 | * the CDB.
|
| 973 |
|
| 974 | if (!(qc->dev->quirks & ATA_QUIRK_STUCK_ERR)) {
|
| 975 | ata_ehi_push_desc(ehi, "ST_FIRST: "
|
| 976 | "DRQ=1 with device error, "
|
| 977 | "dev_stat 0x%X", status);
|
| 978 | qc->err_mask |= AC_ERR_HSM;
|
| 979 | ap->hsm_task_state = HSM_ST_ERR;
|
| 980 | goto fsm_start;
|
| 981 | }
|
| 982 | }
|
| 983 |
|
| 984 | if (qc->tf.protocol == ATA_PROT_PIO) {
|
| 985 | |
| 986 | * send first data block.
|
| 987 |
|
| 988 |
|
| 989 | |
| 990 | * to HSM_ST_LAST. so, the state is changed here
|
| 991 | * before ata_pio_sectors().
|
| 992 |
|
| 993 | ap->hsm_task_state = HSM_ST;
|
| 994 | ata_pio_sectors(qc);
|
| 995 | } else
|
| 996 |
|
| 997 | atapi_send_cdb(ap, qc);
|
| 998 |
|
| 999 | |
| 1000 | * otherwise, interrupt handler takes over from here.
|
| 1001 |
|
| 1002 | break;
|
| 1003 |
|
| 1004 | case HSM_ST:
|
| 1005 |
|
| 1006 | if (qc->tf.protocol == ATAPI_PROT_PIO) {
|
| 1007 |
|
| 1008 | if ((status & ATA_DRQ) == 0) {
|
| 1009 | |
| 1010 | * Device error will be tagged in HSM_ST_LAST.
|
| 1011 |
|
| 1012 | ap->hsm_task_state = HSM_ST_LAST;
|
| 1013 | goto fsm_start;
|
| 1014 | }
|
| 1015 |
|
| 1016 | |
| 1017 | * when it finds something wrong.
|
| 1018 | * We ignore DRQ here and stop the HSM by
|
| 1019 | * changing hsm_task_state to HSM_ST_ERR and
|
| 1020 | * let the EH abort the command or reset the device.
|
| 1021 |
|
| 1022 | if (unlikely(status & (ATA_ERR | ATA_DF))) {
|
| 1023 | ata_ehi_push_desc(ehi, "ST-ATAPI: "
|
| 1024 | "DRQ=1 with device error, "
|
| 1025 | "dev_stat 0x%X", status);
|
| 1026 | qc->err_mask |= AC_ERR_HSM;
|
| 1027 | ap->hsm_task_state = HSM_ST_ERR;
|
| 1028 | goto fsm_start;
|
| 1029 | }
|
| 1030 |
|
| 1031 | atapi_pio_bytes(qc);
|
| 1032 |
|
| 1033 | if (unlikely(ap->hsm_task_state == HSM_ST_ERR))
|
| 1034 |
|
| 1035 | goto fsm_start;
|
| 1036 |
|
| 1037 | } else {
|
| 1038 |
|
| 1039 | if (unlikely((status & ATA_DRQ) == 0)) {
|
| 1040 |
|
| 1041 | if (likely(status & (ATA_ERR | ATA_DF))) {
|
| 1042 |
|
| 1043 | qc->err_mask |= AC_ERR_DEV;
|
| 1044 |
|
| 1045 | |
| 1046 | * IDENTIFY, it's likely a phantom
|
| 1047 | * device. Mark hint.
|
| 1048 |
|
| 1049 | if (qc->dev->quirks &
|
| 1050 | ATA_QUIRK_DIAGNOSTIC)
|
| 1051 | qc->err_mask |=
|
| 1052 | AC_ERR_NODEV_HINT;
|
| 1053 | } else {
|
| 1054 | |
| 1055 | * Phantom devices also trigger this
|
| 1056 | * condition. Mark hint.
|
| 1057 |
|
| 1058 | ata_ehi_push_desc(ehi, "ST-ATA: "
|
| 1059 | "DRQ=0 without device error, "
|
| 1060 | "dev_stat 0x%X", status);
|
| 1061 | qc->err_mask |= AC_ERR_HSM |
|
| 1062 | AC_ERR_NODEV_HINT;
|
| 1063 | }
|
| 1064 |
|
| 1065 | ap->hsm_task_state = HSM_ST_ERR;
|
| 1066 | goto fsm_start;
|
| 1067 | }
|
| 1068 |
|
| 1069 | |
| 1070 | * data transfer (DRQ=1) alone with ERR=1.
|
| 1071 | * We respect DRQ here and transfer one
|
| 1072 | * block of junk data before changing the
|
| 1073 | * hsm_task_state to HSM_ST_ERR.
|
| 1074 | *
|
| 1075 | * For PIO writes, ERR=1 DRQ=1 doesn't make
|
| 1076 | * sense since the data block has been
|
| 1077 | * transferred to the device.
|
| 1078 |
|
| 1079 | if (unlikely(status & (ATA_ERR | ATA_DF))) {
|
| 1080 |
|
| 1081 | qc->err_mask |= AC_ERR_DEV;
|
| 1082 |
|
| 1083 | if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
|
| 1084 | ata_pio_sectors(qc);
|
| 1085 | status = ata_wait_idle(ap);
|
| 1086 | }
|
| 1087 |
|
| 1088 | if (status & (ATA_BUSY | ATA_DRQ)) {
|
| 1089 | ata_ehi_push_desc(ehi, "ST-ATA: "
|
| 1090 | "BUSY|DRQ persists on ERR|DF, "
|
| 1091 | "dev_stat 0x%X", status);
|
| 1092 | qc->err_mask |= AC_ERR_HSM;
|
| 1093 | }
|
| 1094 |
|
| 1095 | |
| 1096 | * status register stuck at 0x7f and
|
| 1097 | * lbal/m/h at zero which makes it
|
| 1098 | * pass all other presence detection
|
| 1099 | * mechanisms we have. Set NODEV_HINT
|
| 1100 | * for it. Kernel bz#7241.
|
| 1101 |
|
| 1102 | if (status == 0x7f)
|
| 1103 | qc->err_mask |= AC_ERR_NODEV_HINT;
|
| 1104 |
|
| 1105 | |
| 1106 | * state to HSM_ST_LAST. so, the state
|
| 1107 | * is changed after ata_pio_sectors().
|
| 1108 |
|
| 1109 | ap->hsm_task_state = HSM_ST_ERR;
|
| 1110 | goto fsm_start;
|
| 1111 | }
|
| 1112 |
|
| 1113 | ata_pio_sectors(qc);
|
| 1114 |
|
| 1115 | if (ap->hsm_task_state == HSM_ST_LAST &&
|
| 1116 | (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
|
| 1117 | status = ata_sff_busy_wait(ap,
|
| 1118 | ATA_BUSY | ATA_DRQ, 10);
|
| 1119 | if (status != 0xff &&
|
| 1120 | (status & (ATA_BUSY | ATA_DRQ))) {
|
| 1121 | qc->tf.flags |= ATA_TFLAG_POLLING;
|
| 1122 | ata_sff_queue_pio_task(link, 0);
|
| 1123 | return 0;
|
| 1124 | }
|
| 1125 | goto fsm_start;
|
| 1126 | }
|
| 1127 | }
|
| 1128 |
|
| 1129 | poll_next = 1;
|
| 1130 | break;
|
| 1131 |
|
| 1132 | case HSM_ST_LAST:
|
| 1133 | if (unlikely(!ata_ok(status))) {
|
| 1134 | qc->err_mask |= __ac_err_mask(status);
|
| 1135 | ap->hsm_task_state = HSM_ST_ERR;
|
| 1136 | goto fsm_start;
|
| 1137 | }
|
| 1138 |
|
| 1139 |
|
| 1140 | trace_ata_sff_hsm_command_complete(qc, status);
|
| 1141 |
|
| 1142 | WARN_ON_ONCE(qc->err_mask & (AC_ERR_DEV | AC_ERR_HSM));
|
| 1143 |
|
| 1144 | ap->hsm_task_state = HSM_ST_IDLE;
|
| 1145 |
|
| 1146 |
|
| 1147 | ata_hsm_qc_complete(qc, in_wq);
|
| 1148 |
|
| 1149 | poll_next = 0;
|
| 1150 | break;
|
| 1151 |
|
| 1152 | case HSM_ST_ERR:
|
| 1153 | ap->hsm_task_state = HSM_ST_IDLE;
|
| 1154 |
|
| 1155 |
|
| 1156 | ata_hsm_qc_complete(qc, in_wq);
|
| 1157 |
|
| 1158 | poll_next = 0;
|
| 1159 | break;
|
| 1160 | default:
|
| 1161 | poll_next = 0;
|
| 1162 | WARN(true, "ata%d: SFF host state machine in invalid state %d",
|
| 1163 | ap->print_id, ap->hsm_task_state);
|
| 1164 | }
|
| 1165 |
|
| 1166 | return poll_next;
|
| 1167 | }
|
| 1168 | EXPORT_SYMBOL_GPL(ata_sff_hsm_move);
|
| 1169 |
|
| 1170 | void ata_sff_queue_work(struct work_struct *work)
|
| 1171 | {
|
| 1172 | queue_work(ata_sff_wq, work);
|
| 1173 | }
|
| 1174 | EXPORT_SYMBOL_GPL(ata_sff_queue_work);
|
| 1175 |
|
| 1176 | void ata_sff_queue_delayed_work(struct delayed_work *dwork, unsigned long delay)
|
| 1177 | {
|
| 1178 | queue_delayed_work(ata_sff_wq, dwork, delay);
|
| 1179 | }
|
| 1180 | EXPORT_SYMBOL_GPL(ata_sff_queue_delayed_work);
|
| 1181 |
|
| 1182 | void ata_sff_queue_pio_task(struct ata_link *link, unsigned long delay)
|
| 1183 | {
|
| 1184 | struct ata_port *ap = link->ap;
|
| 1185 |
|
| 1186 | WARN_ON((ap->sff_pio_task_link != NULL) &&
|
| 1187 | (ap->sff_pio_task_link != link));
|
| 1188 | ap->sff_pio_task_link = link;
|
| 1189 |
|
| 1190 |
|
| 1191 | ata_sff_queue_delayed_work(&ap->sff_pio_task, msecs_to_jiffies(delay));
|
| 1192 | }
|
| 1193 | EXPORT_SYMBOL_GPL(ata_sff_queue_pio_task);
|
| 1194 |
|
| 1195 | void ata_sff_flush_pio_task(struct ata_port *ap)
|
| 1196 | {
|
| 1197 | trace_ata_sff_flush_pio_task(ap);
|
| 1198 |
|
| 1199 | cancel_delayed_work_sync(&ap->sff_pio_task);
|
| 1200 |
|
| 1201 | |
| 1202 | * We wanna reset the HSM state to IDLE. If we do so without
|
| 1203 | * grabbing the port lock, critical sections protected by it which
|
| 1204 | * expect the HSM state to stay stable may get surprised. For
|
| 1205 | * example, we may set IDLE in between the time
|
| 1206 | * __ata_sff_port_intr() checks for HSM_ST_IDLE and before it calls
|
| 1207 | * ata_sff_hsm_move() causing ata_sff_hsm_move() to BUG().
|
| 1208 |
|
| 1209 | spin_lock_irq(ap->lock);
|
| 1210 | ap->hsm_task_state = HSM_ST_IDLE;
|
| 1211 | spin_unlock_irq(ap->lock);
|
| 1212 |
|
| 1213 | ap->sff_pio_task_link = NULL;
|
| 1214 | }
|
| 1215 |
|
| 1216 | static void ata_sff_pio_task(struct work_struct *work)
|
| 1217 | {
|
| 1218 | struct ata_port *ap =
|
| 1219 | container_of(work, struct ata_port, sff_pio_task.work);
|
| 1220 | struct ata_link *link = ap->sff_pio_task_link;
|
| 1221 | struct ata_queued_cmd *qc;
|
| 1222 | u8 status, wait_mask;
|
| 1223 | int poll_next;
|
| 1224 |
|
| 1225 | spin_lock_irq(ap->lock);
|
| 1226 |
|
| 1227 | BUG_ON(ap->sff_pio_task_link == NULL);
|
| 1228 |
|
| 1229 | qc = ata_qc_from_tag(ap, link->active_tag);
|
| 1230 | if (!qc) {
|
| 1231 | ap->sff_pio_task_link = NULL;
|
| 1232 | goto out_unlock;
|
| 1233 | }
|
| 1234 |
|
| 1235 | fsm_start:
|
| 1236 | WARN_ON_ONCE(ap->hsm_task_state == HSM_ST_IDLE);
|
| 1237 |
|
| 1238 | wait_mask = ATA_BUSY;
|
| 1239 | if (ap->hsm_task_state == HSM_ST_LAST)
|
| 1240 | wait_mask |= ATA_DRQ;
|
| 1241 |
|
| 1242 | |
| 1243 | * This is purely heuristic. This is a fast path.
|
| 1244 | * Sometimes when we enter, BSY will be cleared in
|
| 1245 | * a chk-status or two. If not, the drive is probably seeking
|
| 1246 | * or something. Snooze for a couple msecs, then
|
| 1247 | * chk-status again. If still busy, queue delayed work.
|
| 1248 |
|
| 1249 | status = ata_sff_busy_wait(ap, wait_mask, 5);
|
| 1250 | if (status & wait_mask) {
|
| 1251 | spin_unlock_irq(ap->lock);
|
| 1252 | ata_msleep(ap, 2);
|
| 1253 | spin_lock_irq(ap->lock);
|
| 1254 |
|
| 1255 | status = ata_sff_busy_wait(ap, wait_mask, 10);
|
| 1256 | if (status & wait_mask) {
|
| 1257 | ata_sff_queue_pio_task(link, ATA_SHORT_PAUSE);
|
| 1258 | goto out_unlock;
|
| 1259 | }
|
| 1260 | }
|
| 1261 |
|
| 1262 | |
| 1263 | * hsm_move() may trigger another command to be processed.
|
| 1264 | * clean the link beforehand.
|
| 1265 |
|
| 1266 | ap->sff_pio_task_link = NULL;
|
| 1267 |
|
| 1268 | poll_next = ata_sff_hsm_move(ap, qc, status, 1);
|
| 1269 |
|
| 1270 | |
| 1271 | * may be running at this point.
|
| 1272 |
|
| 1273 | if (poll_next)
|
| 1274 | goto fsm_start;
|
| 1275 | out_unlock:
|
| 1276 | spin_unlock_irq(ap->lock);
|
| 1277 | }
|
| 1278 |
|
| 1279 | |
| 1280 | * ata_sff_qc_issue - issue taskfile to a SFF controller
|
| 1281 | * @qc: command to issue to device
|
| 1282 | *
|
| 1283 | * This function issues a PIO or NODATA command to a SFF
|
| 1284 | * controller.
|
| 1285 | *
|
| 1286 | * LOCKING:
|
| 1287 | * spin_lock_irqsave(host lock)
|
| 1288 | *
|
| 1289 | * RETURNS:
|
| 1290 | * Zero on success, AC_ERR_* mask on failure
|
| 1291 |
|
| 1292 | unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc)
|
| 1293 | {
|
| 1294 | struct ata_port *ap = qc->ap;
|
| 1295 | struct ata_link *link = qc->dev->link;
|
| 1296 |
|
| 1297 | |
| 1298 | * interrupt driven pio and atapi CDB interrupt.
|
| 1299 |
|
| 1300 | if (ap->flags & ATA_FLAG_PIO_POLLING)
|
| 1301 | qc->tf.flags |= ATA_TFLAG_POLLING;
|
| 1302 |
|
| 1303 |
|
| 1304 | ata_dev_select(ap, qc->dev->devno, 1, 0);
|
| 1305 |
|
| 1306 |
|
| 1307 | switch (qc->tf.protocol) {
|
| 1308 | case ATA_PROT_NODATA:
|
| 1309 | if (qc->tf.flags & ATA_TFLAG_POLLING)
|
| 1310 | ata_qc_set_polling(qc);
|
| 1311 |
|
| 1312 | ata_tf_to_host(ap, &qc->tf, qc->tag);
|
| 1313 | ap->hsm_task_state = HSM_ST_LAST;
|
| 1314 |
|
| 1315 | if (qc->tf.flags & ATA_TFLAG_POLLING)
|
| 1316 | ata_sff_queue_pio_task(link, 0);
|
| 1317 |
|
| 1318 | break;
|
| 1319 |
|
| 1320 | case ATA_PROT_PIO:
|
| 1321 | if (qc->tf.flags & ATA_TFLAG_POLLING)
|
| 1322 | ata_qc_set_polling(qc);
|
| 1323 |
|
| 1324 | ata_tf_to_host(ap, &qc->tf, qc->tag);
|
| 1325 |
|
| 1326 | if (qc->tf.flags & ATA_TFLAG_WRITE) {
|
| 1327 |
|
| 1328 | ap->hsm_task_state = HSM_ST_FIRST;
|
| 1329 | ata_sff_queue_pio_task(link, 0);
|
| 1330 |
|
| 1331 | |
| 1332 | * ata_sff_pio_task() codepath.
|
| 1333 |
|
| 1334 | } else {
|
| 1335 |
|
| 1336 | ap->hsm_task_state = HSM_ST;
|
| 1337 |
|
| 1338 | if (qc->tf.flags & ATA_TFLAG_POLLING)
|
| 1339 | ata_sff_queue_pio_task(link, 0);
|
| 1340 |
|
| 1341 | |
| 1342 | * rest. otherwise, interrupt handler takes
|
| 1343 | * over from here.
|
| 1344 |
|
| 1345 | }
|
| 1346 |
|
| 1347 | break;
|
| 1348 |
|
| 1349 | case ATAPI_PROT_PIO:
|
| 1350 | case ATAPI_PROT_NODATA:
|
| 1351 | if (qc->tf.flags & ATA_TFLAG_POLLING)
|
| 1352 | ata_qc_set_polling(qc);
|
| 1353 |
|
| 1354 | ata_tf_to_host(ap, &qc->tf, qc->tag);
|
| 1355 |
|
| 1356 | ap->hsm_task_state = HSM_ST_FIRST;
|
| 1357 |
|
| 1358 |
|
| 1359 | if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) ||
|
| 1360 | (qc->tf.flags & ATA_TFLAG_POLLING))
|
| 1361 | ata_sff_queue_pio_task(link, 0);
|
| 1362 | break;
|
| 1363 |
|
| 1364 | default:
|
| 1365 | return AC_ERR_SYSTEM;
|
| 1366 | }
|
| 1367 |
|
| 1368 | return 0;
|
| 1369 | }
|
| 1370 | EXPORT_SYMBOL_GPL(ata_sff_qc_issue);
|
| 1371 |
|
| 1372 | |
| 1373 | * ata_sff_qc_fill_rtf - fill result TF using ->sff_tf_read
|
| 1374 | * @qc: qc to fill result TF for
|
| 1375 | *
|
| 1376 | * @qc is finished and result TF needs to be filled. Fill it
|
| 1377 | * using ->sff_tf_read.
|
| 1378 | *
|
| 1379 | * LOCKING:
|
| 1380 | * spin_lock_irqsave(host lock)
|
| 1381 |
|
| 1382 | void ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc)
|
| 1383 | {
|
| 1384 | qc->ap->ops->sff_tf_read(qc->ap, &qc->result_tf);
|
| 1385 | }
|
| 1386 | EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf);
|
| 1387 |
|
| 1388 | static unsigned int ata_sff_idle_irq(struct ata_port *ap)
|
| 1389 | {
|
| 1390 | ap->stats.idle_irq++;
|
| 1391 |
|
| 1392 | #ifdef ATA_IRQ_TRAP
|
| 1393 | if ((ap->stats.idle_irq % 1000) == 0) {
|
| 1394 | ap->ops->sff_check_status(ap);
|
| 1395 | if (ap->ops->sff_irq_clear)
|
| 1396 | ap->ops->sff_irq_clear(ap);
|
| 1397 | ata_port_warn(ap, "irq trap\n");
|
| 1398 | return 1;
|
| 1399 | }
|
| 1400 | #endif
|
| 1401 | return 0;
|
| 1402 | }
|
| 1403 |
|
| 1404 | static unsigned int __ata_sff_port_intr(struct ata_port *ap,
|
| 1405 | struct ata_queued_cmd *qc,
|
| 1406 | bool hsmv_on_idle)
|
| 1407 | {
|
| 1408 | u8 status;
|
| 1409 |
|
| 1410 | trace_ata_sff_port_intr(qc, hsmv_on_idle);
|
| 1411 |
|
| 1412 |
|
| 1413 | switch (ap->hsm_task_state) {
|
| 1414 | case HSM_ST_FIRST:
|
| 1415 | |
| 1416 | * at this state when ready to receive CDB.
|
| 1417 |
|
| 1418 |
|
| 1419 | |
| 1420 | * The flag was turned on only for atapi devices. No
|
| 1421 | * need to check ata_is_atapi(qc->tf.protocol) again.
|
| 1422 |
|
| 1423 | if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
|
| 1424 | return ata_sff_idle_irq(ap);
|
| 1425 | break;
|
| 1426 | case HSM_ST_IDLE:
|
| 1427 | return ata_sff_idle_irq(ap);
|
| 1428 | default:
|
| 1429 | break;
|
| 1430 | }
|
| 1431 |
|
| 1432 |
|
| 1433 | status = ata_sff_irq_status(ap);
|
| 1434 | if (status & ATA_BUSY) {
|
| 1435 | if (hsmv_on_idle) {
|
| 1436 |
|
| 1437 | qc->err_mask |= AC_ERR_HSM;
|
| 1438 | ap->hsm_task_state = HSM_ST_ERR;
|
| 1439 | } else
|
| 1440 | return ata_sff_idle_irq(ap);
|
| 1441 | }
|
| 1442 |
|
| 1443 |
|
| 1444 | if (ap->ops->sff_irq_clear)
|
| 1445 | ap->ops->sff_irq_clear(ap);
|
| 1446 |
|
| 1447 | ata_sff_hsm_move(ap, qc, status, 0);
|
| 1448 |
|
| 1449 | return 1;
|
| 1450 | }
|
| 1451 |
|
| 1452 | |
| 1453 | * ata_sff_port_intr - Handle SFF port interrupt
|
| 1454 | * @ap: Port on which interrupt arrived (possibly...)
|
| 1455 | * @qc: Taskfile currently active in engine
|
| 1456 | *
|
| 1457 | * Handle port interrupt for given queued command.
|
| 1458 | *
|
| 1459 | * LOCKING:
|
| 1460 | * spin_lock_irqsave(host lock)
|
| 1461 | *
|
| 1462 | * RETURNS:
|
| 1463 | * One if interrupt was handled, zero if not (shared irq).
|
| 1464 |
|
| 1465 | unsigned int ata_sff_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
|
| 1466 | {
|
| 1467 | return __ata_sff_port_intr(ap, qc, false);
|
| 1468 | }
|
| 1469 | EXPORT_SYMBOL_GPL(ata_sff_port_intr);
|
| 1470 |
|
| 1471 | static inline irqreturn_t __ata_sff_interrupt(int irq, void *dev_instance,
|
| 1472 | unsigned int (*port_intr)(struct ata_port *, struct ata_queued_cmd *))
|
| 1473 | {
|
| 1474 | struct ata_host *host = dev_instance;
|
| 1475 | bool retried = false;
|
| 1476 | unsigned int i;
|
| 1477 | unsigned int handled, idle, polling;
|
| 1478 | unsigned long flags;
|
| 1479 |
|
| 1480 |
|
| 1481 | spin_lock_irqsave(&host->lock, flags);
|
| 1482 |
|
| 1483 | retry:
|
| 1484 | handled = idle = polling = 0;
|
| 1485 | for (i = 0; i < host->n_ports; i++) {
|
| 1486 | struct ata_port *ap = host->ports[i];
|
| 1487 | struct ata_queued_cmd *qc;
|
| 1488 |
|
| 1489 | qc = ata_qc_from_tag(ap, ap->link.active_tag);
|
| 1490 | if (qc) {
|
| 1491 | if (!(qc->tf.flags & ATA_TFLAG_POLLING))
|
| 1492 | handled |= port_intr(ap, qc);
|
| 1493 | else
|
| 1494 | polling |= 1 << i;
|
| 1495 | } else
|
| 1496 | idle |= 1 << i;
|
| 1497 | }
|
| 1498 |
|
| 1499 | |
| 1500 | * If no port was expecting IRQ but the controller is actually
|
| 1501 | * asserting IRQ line, nobody cared will ensue. Check IRQ
|
| 1502 | * pending status if available and clear spurious IRQ.
|
| 1503 |
|
| 1504 | if (!handled && !retried) {
|
| 1505 | bool retry = false;
|
| 1506 |
|
| 1507 | for (i = 0; i < host->n_ports; i++) {
|
| 1508 | struct ata_port *ap = host->ports[i];
|
| 1509 |
|
| 1510 | if (polling & (1 << i))
|
| 1511 | continue;
|
| 1512 |
|
| 1513 | if (!ap->ops->sff_irq_check ||
|
| 1514 | !ap->ops->sff_irq_check(ap))
|
| 1515 | continue;
|
| 1516 |
|
| 1517 | if (idle & (1 << i)) {
|
| 1518 | ap->ops->sff_check_status(ap);
|
| 1519 | if (ap->ops->sff_irq_clear)
|
| 1520 | ap->ops->sff_irq_clear(ap);
|
| 1521 | } else {
|
| 1522 |
|
| 1523 | if (!(ap->ops->sff_check_status(ap) & ATA_BUSY))
|
| 1524 | retry |= true;
|
| 1525 | |
| 1526 | * With command in flight, we can't do
|
| 1527 | * sff_irq_clear() w/o racing with completion.
|
| 1528 |
|
| 1529 | }
|
| 1530 | }
|
| 1531 |
|
| 1532 | if (retry) {
|
| 1533 | retried = true;
|
| 1534 | goto retry;
|
| 1535 | }
|
| 1536 | }
|
| 1537 |
|
| 1538 | spin_unlock_irqrestore(&host->lock, flags);
|
| 1539 |
|
| 1540 | return IRQ_RETVAL(handled);
|
| 1541 | }
|
| 1542 |
|
| 1543 | |
| 1544 | * ata_sff_interrupt - Default SFF ATA host interrupt handler
|
| 1545 | * @irq: irq line (unused)
|
| 1546 | * @dev_instance: pointer to our ata_host information structure
|
| 1547 | *
|
| 1548 | * Default interrupt handler for PCI IDE devices. Calls
|
| 1549 | * ata_sff_port_intr() for each port that is not disabled.
|
| 1550 | *
|
| 1551 | * LOCKING:
|
| 1552 | * Obtains host lock during operation.
|
| 1553 | *
|
| 1554 | * RETURNS:
|
| 1555 | * IRQ_NONE or IRQ_HANDLED.
|
| 1556 |
|
| 1557 | irqreturn_t ata_sff_interrupt(int irq, void *dev_instance)
|
| 1558 | {
|
| 1559 | return __ata_sff_interrupt(irq, dev_instance, ata_sff_port_intr);
|
| 1560 | }
|
| 1561 | EXPORT_SYMBOL_GPL(ata_sff_interrupt);
|
| 1562 |
|
| 1563 | |
| 1564 | * ata_sff_lost_interrupt - Check for an apparent lost interrupt
|
| 1565 | * @ap: port that appears to have timed out
|
| 1566 | *
|
| 1567 | * Called from the libata error handlers when the core code suspects
|
| 1568 | * an interrupt has been lost. If it has complete anything we can and
|
| 1569 | * then return. Interface must support altstatus for this faster
|
| 1570 | * recovery to occur.
|
| 1571 | *
|
| 1572 | * Locking:
|
| 1573 | * Caller holds host lock
|
| 1574 |
|
| 1575 |
|
| 1576 | void ata_sff_lost_interrupt(struct ata_port *ap)
|
| 1577 | {
|
| 1578 | u8 status = 0;
|
| 1579 | struct ata_queued_cmd *qc;
|
| 1580 |
|
| 1581 |
|
| 1582 | qc = ata_qc_from_tag(ap, ap->link.active_tag);
|
| 1583 |
|
| 1584 | if (!qc || qc->tf.flags & ATA_TFLAG_POLLING)
|
| 1585 | return;
|
| 1586 | |
| 1587 | isn't a lost IRQ but is still in progress
|
| 1588 | if (WARN_ON_ONCE(!ata_sff_altstatus(ap, &status)))
|
| 1589 | return;
|
| 1590 | if (status & ATA_BUSY)
|
| 1591 | return;
|
| 1592 |
|
| 1593 | |
| 1594 | no interrupt.
|
| 1595 | ata_port_warn(ap, "lost interrupt (Status 0x%x)\n", status);
|
| 1596 | |
| 1597 | lost
|
| 1598 | ata_sff_port_intr(ap, qc);
|
| 1599 | }
|
| 1600 | EXPORT_SYMBOL_GPL(ata_sff_lost_interrupt);
|
| 1601 |
|
| 1602 | |
| 1603 | * ata_sff_freeze - Freeze SFF controller port
|
| 1604 | * @ap: port to freeze
|
| 1605 | *
|
| 1606 | * Freeze SFF controller port.
|
| 1607 | *
|
| 1608 | * LOCKING:
|
| 1609 | * Inherited from caller.
|
| 1610 |
|
| 1611 | void ata_sff_freeze(struct ata_port *ap)
|
| 1612 | {
|
| 1613 | ap->ctl |= ATA_NIEN;
|
| 1614 | ap->last_ctl = ap->ctl;
|
| 1615 |
|
| 1616 | ata_sff_set_devctl(ap, ap->ctl);
|
| 1617 |
|
| 1618 | |
| 1619 | * ATA_NIEN manipulation. Also, many controllers fail to mask
|
| 1620 | * previously pending IRQ on ATA_NIEN assertion. Clear it.
|
| 1621 |
|
| 1622 | ap->ops->sff_check_status(ap);
|
| 1623 |
|
| 1624 | if (ap->ops->sff_irq_clear)
|
| 1625 | ap->ops->sff_irq_clear(ap);
|
| 1626 | }
|
| 1627 | EXPORT_SYMBOL_GPL(ata_sff_freeze);
|
| 1628 |
|
| 1629 | |
| 1630 | * ata_sff_thaw - Thaw SFF controller port
|
| 1631 | * @ap: port to thaw
|
| 1632 | *
|
| 1633 | * Thaw SFF controller port.
|
| 1634 | *
|
| 1635 | * LOCKING:
|
| 1636 | * Inherited from caller.
|
| 1637 |
|
| 1638 | void ata_sff_thaw(struct ata_port *ap)
|
| 1639 | {
|
| 1640 |
|
| 1641 | ap->ops->sff_check_status(ap);
|
| 1642 | if (ap->ops->sff_irq_clear)
|
| 1643 | ap->ops->sff_irq_clear(ap);
|
| 1644 | ata_sff_irq_on(ap);
|
| 1645 | }
|
| 1646 | EXPORT_SYMBOL_GPL(ata_sff_thaw);
|
| 1647 |
|
| 1648 | |
| 1649 | * ata_sff_prereset - prepare SFF link for reset
|
| 1650 | * @link: SFF link to be reset
|
| 1651 | * @deadline: deadline jiffies for the operation
|
| 1652 | *
|
| 1653 | * SFF link @link is about to be reset. Initialize it. It first
|
| 1654 | * calls ata_std_prereset() and wait for !BSY if the port is
|
| 1655 | * being softreset.
|
| 1656 | *
|
| 1657 | * LOCKING:
|
| 1658 | * Kernel thread context (may sleep)
|
| 1659 | *
|
| 1660 | * RETURNS:
|
| 1661 | * Always 0.
|
| 1662 |
|
| 1663 | int ata_sff_prereset(struct ata_link *link, unsigned long deadline)
|
| 1664 | {
|
| 1665 | struct ata_eh_context *ehc = &link->eh_context;
|
| 1666 | int rc;
|
| 1667 |
|
| 1668 |
|
| 1669 | ata_std_prereset(link, deadline);
|
| 1670 |
|
| 1671 |
|
| 1672 | if (ehc->i.action & ATA_EH_HARDRESET)
|
| 1673 | return 0;
|
| 1674 |
|
| 1675 |
|
| 1676 | if (!ata_link_offline(link)) {
|
| 1677 | rc = ata_sff_wait_ready(link, deadline);
|
| 1678 | if (rc && rc != -ENODEV) {
|
| 1679 | ata_link_warn(link,
|
| 1680 | "device not ready (errno=%d), forcing hardreset\n",
|
| 1681 | rc);
|
| 1682 | ehc->i.action |= ATA_EH_HARDRESET;
|
| 1683 | }
|
| 1684 | }
|
| 1685 |
|
| 1686 | return 0;
|
| 1687 | }
|
| 1688 | EXPORT_SYMBOL_GPL(ata_sff_prereset);
|
| 1689 |
|
| 1690 | |
| 1691 | * ata_devchk - PATA device presence detection
|
| 1692 | * @ap: ATA channel to examine
|
| 1693 | * @device: Device to examine (starting at zero)
|
| 1694 | *
|
| 1695 | * This technique was originally described in
|
| 1696 | * Hale Landis's ATADRVR (www.ata-atapi.com), and
|
| 1697 | * later found its way into the ATA/ATAPI spec.
|
| 1698 | *
|
| 1699 | * Write a pattern to the ATA shadow registers,
|
| 1700 | * and if a device is present, it will respond by
|
| 1701 | * correctly storing and echoing back the
|
| 1702 | * ATA shadow register contents.
|
| 1703 | *
|
| 1704 | * RETURN:
|
| 1705 | * true if device is present, false if not.
|
| 1706 | *
|
| 1707 | * LOCKING:
|
| 1708 | * caller.
|
| 1709 |
|
| 1710 | static bool ata_devchk(struct ata_port *ap, unsigned int device)
|
| 1711 | {
|
| 1712 | struct ata_ioports *ioaddr = &ap->ioaddr;
|
| 1713 | u8 nsect, lbal;
|
| 1714 |
|
| 1715 | ap->ops->sff_dev_select(ap, device);
|
| 1716 |
|
| 1717 | iowrite8(0x55, ioaddr->nsect_addr);
|
| 1718 | iowrite8(0xaa, ioaddr->lbal_addr);
|
| 1719 |
|
| 1720 | iowrite8(0xaa, ioaddr->nsect_addr);
|
| 1721 | iowrite8(0x55, ioaddr->lbal_addr);
|
| 1722 |
|
| 1723 | iowrite8(0x55, ioaddr->nsect_addr);
|
| 1724 | iowrite8(0xaa, ioaddr->lbal_addr);
|
| 1725 |
|
| 1726 | nsect = ioread8(ioaddr->nsect_addr);
|
| 1727 | lbal = ioread8(ioaddr->lbal_addr);
|
| 1728 |
|
| 1729 | if ((nsect == 0x55) && (lbal == 0xaa))
|
| 1730 | return true;
|
| 1731 |
|
| 1732 | return false;
|
| 1733 | }
|
| 1734 |
|
| 1735 | |
| 1736 | * ata_sff_dev_classify - Parse returned ATA device signature
|
| 1737 | * @dev: ATA device to classify (starting at zero)
|
| 1738 | * @present: device seems present
|
| 1739 | * @r_err: Value of error register on completion
|
| 1740 | *
|
| 1741 | * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
|
| 1742 | * an ATA/ATAPI-defined set of values is placed in the ATA
|
| 1743 | * shadow registers, indicating the results of device detection
|
| 1744 | * and diagnostics.
|
| 1745 | *
|
| 1746 | * Select the ATA device, and read the values from the ATA shadow
|
| 1747 | * registers. Then parse according to the Error register value,
|
| 1748 | * and the spec-defined values examined by ata_dev_classify().
|
| 1749 | *
|
| 1750 | * LOCKING:
|
| 1751 | * caller.
|
| 1752 | *
|
| 1753 | * RETURNS:
|
| 1754 | * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
|
| 1755 |
|
| 1756 | unsigned int ata_sff_dev_classify(struct ata_device *dev, int present,
|
| 1757 | u8 *r_err)
|
| 1758 | {
|
| 1759 | struct ata_port *ap = dev->link->ap;
|
| 1760 | struct ata_taskfile tf;
|
| 1761 | unsigned int class;
|
| 1762 | u8 err;
|
| 1763 |
|
| 1764 | ap->ops->sff_dev_select(ap, dev->devno);
|
| 1765 |
|
| 1766 | memset(&tf, 0, sizeof(tf));
|
| 1767 |
|
| 1768 | ap->ops->sff_tf_read(ap, &tf);
|
| 1769 | err = tf.error;
|
| 1770 | if (r_err)
|
| 1771 | *r_err = err;
|
| 1772 |
|
| 1773 |
|
| 1774 | if (err == 0)
|
| 1775 |
|
| 1776 | dev->quirks |= ATA_QUIRK_DIAGNOSTIC;
|
| 1777 | else if (err == 1)
|
| 1778 | ;
|
| 1779 | else if ((dev->devno == 0) && (err == 0x81))
|
| 1780 | ;
|
| 1781 | else
|
| 1782 | return ATA_DEV_NONE;
|
| 1783 |
|
| 1784 |
|
| 1785 | class = ata_port_classify(ap, &tf);
|
| 1786 | switch (class) {
|
| 1787 | case ATA_DEV_UNKNOWN:
|
| 1788 | |
| 1789 | * If the device failed diagnostic, it's likely to
|
| 1790 | * have reported incorrect device signature too.
|
| 1791 | * Assume ATA device if the device seems present but
|
| 1792 | * device signature is invalid with diagnostic
|
| 1793 | * failure.
|
| 1794 |
|
| 1795 | if (present && (dev->quirks & ATA_QUIRK_DIAGNOSTIC))
|
| 1796 | class = ATA_DEV_ATA;
|
| 1797 | else
|
| 1798 | class = ATA_DEV_NONE;
|
| 1799 | break;
|
| 1800 | case ATA_DEV_ATA:
|
| 1801 | if (ap->ops->sff_check_status(ap) == 0)
|
| 1802 | class = ATA_DEV_NONE;
|
| 1803 | break;
|
| 1804 | }
|
| 1805 | return class;
|
| 1806 | }
|
| 1807 | EXPORT_SYMBOL_GPL(ata_sff_dev_classify);
|
| 1808 |
|
| 1809 | |
| 1810 | * ata_sff_wait_after_reset - wait for devices to become ready after reset
|
| 1811 | * @link: SFF link which is just reset
|
| 1812 | * @devmask: mask of present devices
|
| 1813 | * @deadline: deadline jiffies for the operation
|
| 1814 | *
|
| 1815 | * Wait devices attached to SFF @link to become ready after
|
| 1816 | * reset. It contains preceding 150ms wait to avoid accessing TF
|
| 1817 | * status register too early.
|
| 1818 | *
|
| 1819 | * LOCKING:
|
| 1820 | * Kernel thread context (may sleep).
|
| 1821 | *
|
| 1822 | * RETURNS:
|
| 1823 | * 0 on success, -ENODEV if some or all of devices in @devmask
|
| 1824 | * don't seem to exist. -errno on other errors.
|
| 1825 |
|
| 1826 | int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask,
|
| 1827 | unsigned long deadline)
|
| 1828 | {
|
| 1829 | struct ata_port *ap = link->ap;
|
| 1830 | struct ata_ioports *ioaddr = &ap->ioaddr;
|
| 1831 | unsigned int dev0 = devmask & (1 << 0);
|
| 1832 | unsigned int dev1 = devmask & (1 << 1);
|
| 1833 | int rc, ret = 0;
|
| 1834 |
|
| 1835 | ata_msleep(ap, ATA_WAIT_AFTER_RESET);
|
| 1836 |
|
| 1837 |
|
| 1838 | rc = ata_sff_wait_ready(link, deadline);
|
| 1839 | |
| 1840 | * and TF status is 0xff, bail out on it too.
|
| 1841 |
|
| 1842 | if (rc)
|
| 1843 | return rc;
|
| 1844 |
|
| 1845 | |
| 1846 | * access briefly, then wait for BSY to clear.
|
| 1847 |
|
| 1848 | if (dev1) {
|
| 1849 | int i;
|
| 1850 |
|
| 1851 | ap->ops->sff_dev_select(ap, 1);
|
| 1852 |
|
| 1853 | |
| 1854 | * to set nsect/lbal after reset, so don't waste too
|
| 1855 | * much time on it. We're gonna wait for !BSY anyway.
|
| 1856 |
|
| 1857 | for (i = 0; i < 2; i++) {
|
| 1858 | u8 nsect, lbal;
|
| 1859 |
|
| 1860 | nsect = ioread8(ioaddr->nsect_addr);
|
| 1861 | lbal = ioread8(ioaddr->lbal_addr);
|
| 1862 | if ((nsect == 1) && (lbal == 1))
|
| 1863 | break;
|
| 1864 | ata_msleep(ap, 50);
|
| 1865 | }
|
| 1866 |
|
| 1867 | rc = ata_sff_wait_ready(link, deadline);
|
| 1868 | if (rc) {
|
| 1869 | if (rc != -ENODEV)
|
| 1870 | return rc;
|
| 1871 | ret = rc;
|
| 1872 | }
|
| 1873 | }
|
| 1874 |
|
| 1875 |
|
| 1876 | ap->ops->sff_dev_select(ap, 0);
|
| 1877 | if (dev1)
|
| 1878 | ap->ops->sff_dev_select(ap, 1);
|
| 1879 | if (dev0)
|
| 1880 | ap->ops->sff_dev_select(ap, 0);
|
| 1881 |
|
| 1882 | return ret;
|
| 1883 | }
|
| 1884 | EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset);
|
| 1885 |
|
| 1886 | static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask,
|
| 1887 | unsigned long deadline)
|
| 1888 | {
|
| 1889 | struct ata_ioports *ioaddr = &ap->ioaddr;
|
| 1890 |
|
| 1891 | if (ap->ioaddr.ctl_addr) {
|
| 1892 |
|
| 1893 | iowrite8(ap->ctl, ioaddr->ctl_addr);
|
| 1894 | udelay(20);
|
| 1895 | iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
|
| 1896 | udelay(20);
|
| 1897 | iowrite8(ap->ctl, ioaddr->ctl_addr);
|
| 1898 | ap->last_ctl = ap->ctl;
|
| 1899 | }
|
| 1900 |
|
| 1901 |
|
| 1902 | return ata_sff_wait_after_reset(&ap->link, devmask, deadline);
|
| 1903 | }
|
| 1904 |
|
| 1905 | |
| 1906 | * ata_sff_softreset - reset host port via ATA SRST
|
| 1907 | * @link: ATA link to reset
|
| 1908 | * @classes: resulting classes of attached devices
|
| 1909 | * @deadline: deadline jiffies for the operation
|
| 1910 | *
|
| 1911 | * Reset host port using ATA SRST.
|
| 1912 | *
|
| 1913 | * LOCKING:
|
| 1914 | * Kernel thread context (may sleep)
|
| 1915 | *
|
| 1916 | * RETURNS:
|
| 1917 | * 0 on success, -errno otherwise.
|
| 1918 |
|
| 1919 | int ata_sff_softreset(struct ata_link *link, unsigned int *classes,
|
| 1920 | unsigned long deadline)
|
| 1921 | {
|
| 1922 | struct ata_port *ap = link->ap;
|
| 1923 | unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
|
| 1924 | unsigned int devmask = 0;
|
| 1925 | int rc;
|
| 1926 | u8 err;
|
| 1927 |
|
| 1928 |
|
| 1929 | if (ata_devchk(ap, 0))
|
| 1930 | devmask |= (1 << 0);
|
| 1931 | if (slave_possible && ata_devchk(ap, 1))
|
| 1932 | devmask |= (1 << 1);
|
| 1933 |
|
| 1934 |
|
| 1935 | ap->ops->sff_dev_select(ap, 0);
|
| 1936 |
|
| 1937 |
|
| 1938 | rc = ata_bus_softreset(ap, devmask, deadline);
|
| 1939 |
|
| 1940 | if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
|
| 1941 | ata_link_err(link, "SRST failed (errno=%d)\n", rc);
|
| 1942 | return rc;
|
| 1943 | }
|
| 1944 |
|
| 1945 |
|
| 1946 | classes[0] = ata_sff_dev_classify(&link->device[0],
|
| 1947 | devmask & (1 << 0), &err);
|
| 1948 | if (slave_possible && err != 0x81)
|
| 1949 | classes[1] = ata_sff_dev_classify(&link->device[1],
|
| 1950 | devmask & (1 << 1), &err);
|
| 1951 |
|
| 1952 | return 0;
|
| 1953 | }
|
| 1954 | EXPORT_SYMBOL_GPL(ata_sff_softreset);
|
| 1955 |
|
| 1956 | |
| 1957 | * sata_sff_hardreset - reset host port via SATA phy reset
|
| 1958 | * @link: link to reset
|
| 1959 | * @class: resulting class of attached device
|
| 1960 | * @deadline: deadline jiffies for the operation
|
| 1961 | *
|
| 1962 | * SATA phy-reset host port using DET bits of SControl register,
|
| 1963 | * wait for !BSY and classify the attached device.
|
| 1964 | *
|
| 1965 | * LOCKING:
|
| 1966 | * Kernel thread context (may sleep)
|
| 1967 | *
|
| 1968 | * RETURNS:
|
| 1969 | * 0 on success, -errno otherwise.
|
| 1970 |
|
| 1971 | int sata_sff_hardreset(struct ata_link *link, unsigned int *class,
|
| 1972 | unsigned long deadline)
|
| 1973 | {
|
| 1974 | struct ata_eh_context *ehc = &link->eh_context;
|
| 1975 | const unsigned int *timing = sata_ehc_deb_timing(ehc);
|
| 1976 | bool online;
|
| 1977 | int rc;
|
| 1978 |
|
| 1979 | rc = sata_link_hardreset(link, timing, deadline, &online,
|
| 1980 | ata_sff_check_ready);
|
| 1981 | if (online)
|
| 1982 | *class = ata_sff_dev_classify(link->device, 1, NULL);
|
| 1983 |
|
| 1984 | return rc;
|
| 1985 | }
|
| 1986 | EXPORT_SYMBOL_GPL(sata_sff_hardreset);
|
| 1987 |
|
| 1988 | |
| 1989 | * ata_sff_postreset - SFF postreset callback
|
| 1990 | * @link: the target SFF ata_link
|
| 1991 | * @classes: classes of attached devices
|
| 1992 | *
|
| 1993 | * This function is invoked after a successful reset. It first
|
| 1994 | * calls ata_std_postreset() and performs SFF specific postreset
|
| 1995 | * processing.
|
| 1996 | *
|
| 1997 | * LOCKING:
|
| 1998 | * Kernel thread context (may sleep)
|
| 1999 |
|
| 2000 | void ata_sff_postreset(struct ata_link *link, unsigned int *classes)
|
| 2001 | {
|
| 2002 | struct ata_port *ap = link->ap;
|
| 2003 |
|
| 2004 | ata_std_postreset(link, classes);
|
| 2005 |
|
| 2006 |
|
| 2007 | if (classes[0] != ATA_DEV_NONE)
|
| 2008 | ap->ops->sff_dev_select(ap, 1);
|
| 2009 | if (classes[1] != ATA_DEV_NONE)
|
| 2010 | ap->ops->sff_dev_select(ap, 0);
|
| 2011 |
|
| 2012 |
|
| 2013 | if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE)
|
| 2014 | return;
|
| 2015 |
|
| 2016 |
|
| 2017 | if (ata_sff_set_devctl(ap, ap->ctl))
|
| 2018 | ap->last_ctl = ap->ctl;
|
| 2019 | }
|
| 2020 | EXPORT_SYMBOL_GPL(ata_sff_postreset);
|
| 2021 |
|
| 2022 | |
| 2023 | * ata_sff_drain_fifo - Stock FIFO drain logic for SFF controllers
|
| 2024 | * @qc: command
|
| 2025 | *
|
| 2026 | * Drain the FIFO and device of any stuck data following a command
|
| 2027 | * failing to complete. In some cases this is necessary before a
|
| 2028 | * reset will recover the device.
|
| 2029 | *
|
| 2030 |
|
| 2031 |
|
| 2032 | void ata_sff_drain_fifo(struct ata_queued_cmd *qc)
|
| 2033 | {
|
| 2034 | int count;
|
| 2035 | struct ata_port *ap;
|
| 2036 |
|
| 2037 |
|
| 2038 | if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE)
|
| 2039 | return;
|
| 2040 |
|
| 2041 | ap = qc->ap;
|
| 2042 |
|
| 2043 | for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ)
|
| 2044 | && count < 65536; count += 2)
|
| 2045 | ioread16(ap->ioaddr.data_addr);
|
| 2046 |
|
| 2047 | if (count)
|
| 2048 | ata_port_dbg(ap, "drained %d bytes to clear DRQ\n", count);
|
| 2049 |
|
| 2050 | }
|
| 2051 | EXPORT_SYMBOL_GPL(ata_sff_drain_fifo);
|
| 2052 |
|
| 2053 | |
| 2054 | * ata_sff_error_handler - Stock error handler for SFF controller
|
| 2055 | * @ap: port to handle error for
|
| 2056 | *
|
| 2057 | * Stock error handler for SFF controller. It can handle both
|
| 2058 | * PATA and SATA controllers. Many controllers should be able to
|
| 2059 | * use this EH as-is or with some added handling before and
|
| 2060 | * after.
|
| 2061 | *
|
| 2062 | * LOCKING:
|
| 2063 | * Kernel thread context (may sleep)
|
| 2064 |
|
| 2065 | void ata_sff_error_handler(struct ata_port *ap)
|
| 2066 | __must_hold(&ap->host->eh_mutex)
|
| 2067 | {
|
| 2068 | struct ata_queued_cmd *qc;
|
| 2069 | unsigned long flags;
|
| 2070 |
|
| 2071 | qc = __ata_qc_from_tag(ap, ap->link.active_tag);
|
| 2072 | if (qc && !(qc->flags & ATA_QCFLAG_EH))
|
| 2073 | qc = NULL;
|
| 2074 |
|
| 2075 | spin_lock_irqsave(ap->lock, flags);
|
| 2076 |
|
| 2077 | |
| 2078 | * We *MUST* do FIFO draining before we issue a reset as
|
| 2079 | * several devices helpfully clear their internal state and
|
| 2080 | * will lock solid if we touch the data port post reset. Pass
|
| 2081 | * qc in case anyone wants to do different PIO/DMA recovery or
|
| 2082 | * has per command fixups
|
| 2083 |
|
| 2084 | if (ap->ops->sff_drain_fifo)
|
| 2085 | ap->ops->sff_drain_fifo(qc);
|
| 2086 |
|
| 2087 | spin_unlock_irqrestore(ap->lock, flags);
|
| 2088 |
|
| 2089 | ata_std_error_handler(ap);
|
| 2090 | }
|
| 2091 | EXPORT_SYMBOL_GPL(ata_sff_error_handler);
|
| 2092 |
|
| 2093 | |
| 2094 | * ata_sff_std_ports - initialize ioaddr with standard port offsets.
|
| 2095 | * @ioaddr: IO address structure to be initialized
|
| 2096 | *
|
| 2097 | * Utility function which initializes data_addr, error_addr,
|
| 2098 | * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
|
| 2099 | * device_addr, status_addr, and command_addr to standard offsets
|
| 2100 | * relative to cmd_addr.
|
| 2101 | *
|
| 2102 | * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
|
| 2103 |
|
| 2104 | void ata_sff_std_ports(struct ata_ioports *ioaddr)
|
| 2105 | {
|
| 2106 | ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
|
| 2107 | ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
|
| 2108 | ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
|
| 2109 | ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
|
| 2110 | ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
|
| 2111 | ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
|
| 2112 | ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
|
| 2113 | ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
|
| 2114 | ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
|
| 2115 | ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
|
| 2116 | }
|
| 2117 | EXPORT_SYMBOL_GPL(ata_sff_std_ports);
|
| 2118 |
|
| 2119 | #ifdef CONFIG_PCI
|
| 2120 |
|
| 2121 | static bool ata_resources_present(struct pci_dev *pdev, int port)
|
| 2122 | {
|
| 2123 | int i;
|
| 2124 |
|
| 2125 |
|
| 2126 | port *= 2;
|
| 2127 | for (i = 0; i < 2; i++) {
|
| 2128 | if (pci_resource_start(pdev, port + i) == 0 ||
|
| 2129 | pci_resource_len(pdev, port + i) == 0)
|
| 2130 | return false;
|
| 2131 | }
|
| 2132 | return true;
|
| 2133 | }
|
| 2134 |
|
| 2135 | |
| 2136 | * ata_pci_sff_init_host - acquire native PCI ATA resources and init host
|
| 2137 | * @host: target ATA host
|
| 2138 | *
|
| 2139 | * Acquire native PCI ATA resources for @host and initialize the
|
| 2140 | * first two ports of @host accordingly. Ports marked dummy are
|
| 2141 | * skipped and allocation failure makes the port dummy.
|
| 2142 | *
|
| 2143 | * Note that native PCI resources are valid even for legacy hosts
|
| 2144 | * as we fix up pdev resources array early in boot, so this
|
| 2145 | * function can be used for both native and legacy SFF hosts.
|
| 2146 | *
|
| 2147 | * LOCKING:
|
| 2148 | * Inherited from calling layer (may sleep).
|
| 2149 | *
|
| 2150 | * RETURNS:
|
| 2151 | * 0 if at least one port is initialized, -ENODEV if no port is
|
| 2152 | * available.
|
| 2153 |
|
| 2154 | int ata_pci_sff_init_host(struct ata_host *host)
|
| 2155 | {
|
| 2156 | struct device *gdev = host->dev;
|
| 2157 | struct pci_dev *pdev = to_pci_dev(gdev);
|
| 2158 | unsigned int mask = 0;
|
| 2159 | int i, rc;
|
| 2160 |
|
| 2161 |
|
| 2162 | for (i = 0; i < 2; i++) {
|
| 2163 | struct ata_port *ap = host->ports[i];
|
| 2164 | int base = i * 2;
|
| 2165 | void __iomem * const *iomap;
|
| 2166 |
|
| 2167 | if (ata_port_is_dummy(ap))
|
| 2168 | continue;
|
| 2169 |
|
| 2170 | |
| 2171 | * their unused channels this way. Disabled ports are
|
| 2172 | * made dummy.
|
| 2173 |
|
| 2174 | if (!ata_resources_present(pdev, i)) {
|
| 2175 | ap->ops = &ata_dummy_port_ops;
|
| 2176 | continue;
|
| 2177 | }
|
| 2178 |
|
| 2179 | rc = pcim_iomap_regions(pdev, 0x3 << base,
|
| 2180 | dev_driver_string(gdev));
|
| 2181 | if (rc) {
|
| 2182 | dev_warn(gdev,
|
| 2183 | "failed to request/iomap BARs for port %d (errno=%d)\n",
|
| 2184 | i, rc);
|
| 2185 | if (rc == -EBUSY)
|
| 2186 | pcim_pin_device(pdev);
|
| 2187 | ap->ops = &ata_dummy_port_ops;
|
| 2188 | continue;
|
| 2189 | }
|
| 2190 | host->iomap = iomap = pcim_iomap_table(pdev);
|
| 2191 |
|
| 2192 | ap->ioaddr.cmd_addr = iomap[base];
|
| 2193 | ap->ioaddr.altstatus_addr =
|
| 2194 | ap->ioaddr.ctl_addr = (void __iomem *)
|
| 2195 | ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS);
|
| 2196 | ata_sff_std_ports(&ap->ioaddr);
|
| 2197 |
|
| 2198 | ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx",
|
| 2199 | (unsigned long long)pci_resource_start(pdev, base),
|
| 2200 | (unsigned long long)pci_resource_start(pdev, base + 1));
|
| 2201 |
|
| 2202 | mask |= 1 << i;
|
| 2203 | }
|
| 2204 |
|
| 2205 | if (!mask) {
|
| 2206 | dev_err(gdev, "no available native port\n");
|
| 2207 | return -ENODEV;
|
| 2208 | }
|
| 2209 |
|
| 2210 | return 0;
|
| 2211 | }
|
| 2212 | EXPORT_SYMBOL_GPL(ata_pci_sff_init_host);
|
| 2213 |
|
| 2214 | |
| 2215 | * ata_pci_sff_prepare_host - helper to prepare PCI PIO-only SFF ATA host
|
| 2216 | * @pdev: target PCI device
|
| 2217 | * @ppi: array of port_info, must be enough for two ports
|
| 2218 | * @r_host: out argument for the initialized ATA host
|
| 2219 | *
|
| 2220 | * Helper to allocate PIO-only SFF ATA host for @pdev, acquire
|
| 2221 | * all PCI resources and initialize it accordingly in one go.
|
| 2222 | *
|
| 2223 | * LOCKING:
|
| 2224 | * Inherited from calling layer (may sleep).
|
| 2225 | *
|
| 2226 | * RETURNS:
|
| 2227 | * 0 on success, -errno otherwise.
|
| 2228 |
|
| 2229 | int ata_pci_sff_prepare_host(struct pci_dev *pdev,
|
| 2230 | const struct ata_port_info * const *ppi,
|
| 2231 | struct ata_host **r_host)
|
| 2232 | {
|
| 2233 | struct ata_host *host;
|
| 2234 | int rc;
|
| 2235 |
|
| 2236 | if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
|
| 2237 | return -ENOMEM;
|
| 2238 |
|
| 2239 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
|
| 2240 | if (!host) {
|
| 2241 | dev_err(&pdev->dev, "failed to allocate ATA host\n");
|
| 2242 | rc = -ENOMEM;
|
| 2243 | goto err_out;
|
| 2244 | }
|
| 2245 |
|
| 2246 | rc = ata_pci_sff_init_host(host);
|
| 2247 | if (rc)
|
| 2248 | goto err_out;
|
| 2249 |
|
| 2250 | devres_remove_group(&pdev->dev, NULL);
|
| 2251 | *r_host = host;
|
| 2252 | return 0;
|
| 2253 |
|
| 2254 | err_out:
|
| 2255 | devres_release_group(&pdev->dev, NULL);
|
| 2256 | return rc;
|
| 2257 | }
|
| 2258 | EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host);
|
| 2259 |
|
| 2260 | |
| 2261 | * ata_pci_sff_activate_host - start SFF host, request IRQ and register it
|
| 2262 | * @host: target SFF ATA host
|
| 2263 | * @irq_handler: irq_handler used when requesting IRQ(s)
|
| 2264 | * @sht: scsi_host_template to use when registering the host
|
| 2265 | *
|
| 2266 | * This is the counterpart of ata_host_activate() for SFF ATA
|
| 2267 | * hosts. This separate helper is necessary because SFF hosts
|
| 2268 | * use two separate interrupts in legacy mode.
|
| 2269 | *
|
| 2270 | * LOCKING:
|
| 2271 | * Inherited from calling layer (may sleep).
|
| 2272 | *
|
| 2273 | * RETURNS:
|
| 2274 | * 0 on success, -errno otherwise.
|
| 2275 |
|
| 2276 | int ata_pci_sff_activate_host(struct ata_host *host,
|
| 2277 | irq_handler_t irq_handler,
|
| 2278 | const struct scsi_host_template *sht)
|
| 2279 | {
|
| 2280 | struct device *dev = host->dev;
|
| 2281 | struct pci_dev *pdev = to_pci_dev(dev);
|
| 2282 | const char *drv_name = dev_driver_string(host->dev);
|
| 2283 | int legacy_mode = 0, rc;
|
| 2284 |
|
| 2285 | rc = ata_host_start(host);
|
| 2286 | if (rc)
|
| 2287 | return rc;
|
| 2288 |
|
| 2289 | if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
|
| 2290 | u8 tmp8, mask = 0;
|
| 2291 |
|
| 2292 | |
| 2293 | * ATA spec says we should use legacy mode when one
|
| 2294 | * port is in legacy mode, but disabled ports on some
|
| 2295 | * PCI hosts appear as fixed legacy ports, e.g SB600/700
|
| 2296 | * on which the secondary port is not wired, so
|
| 2297 | * ignore ports that are marked as 'dummy' during
|
| 2298 | * this check
|
| 2299 |
|
| 2300 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8);
|
| 2301 | if (!ata_port_is_dummy(host->ports[0]))
|
| 2302 | mask |= (1 << 0);
|
| 2303 | if (!ata_port_is_dummy(host->ports[1]))
|
| 2304 | mask |= (1 << 2);
|
| 2305 | if ((tmp8 & mask) != mask)
|
| 2306 | legacy_mode = 1;
|
| 2307 | }
|
| 2308 |
|
| 2309 | if (!devres_open_group(dev, NULL, GFP_KERNEL))
|
| 2310 | return -ENOMEM;
|
| 2311 |
|
| 2312 | if (!legacy_mode && pdev->irq) {
|
| 2313 | int i;
|
| 2314 |
|
| 2315 | rc = devm_request_irq(dev, pdev->irq, irq_handler,
|
| 2316 | IRQF_SHARED, drv_name, host);
|
| 2317 | if (rc)
|
| 2318 | goto out;
|
| 2319 |
|
| 2320 | for (i = 0; i < 2; i++) {
|
| 2321 | if (ata_port_is_dummy(host->ports[i]))
|
| 2322 | continue;
|
| 2323 | ata_port_desc_misc(host->ports[i], pdev->irq);
|
| 2324 | }
|
| 2325 | } else if (legacy_mode) {
|
| 2326 | if (!ata_port_is_dummy(host->ports[0])) {
|
| 2327 | rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev),
|
| 2328 | irq_handler, IRQF_SHARED,
|
| 2329 | drv_name, host);
|
| 2330 | if (rc)
|
| 2331 | goto out;
|
| 2332 |
|
| 2333 | ata_port_desc_misc(host->ports[0],
|
| 2334 | ATA_PRIMARY_IRQ(pdev));
|
| 2335 | }
|
| 2336 |
|
| 2337 | if (!ata_port_is_dummy(host->ports[1])) {
|
| 2338 | rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev),
|
| 2339 | irq_handler, IRQF_SHARED,
|
| 2340 | drv_name, host);
|
| 2341 | if (rc)
|
| 2342 | goto out;
|
| 2343 |
|
| 2344 | ata_port_desc_misc(host->ports[1],
|
| 2345 | ATA_SECONDARY_IRQ(pdev));
|
| 2346 | }
|
| 2347 | }
|
| 2348 |
|
| 2349 | rc = ata_host_register(host, sht);
|
| 2350 | out:
|
| 2351 | if (rc == 0)
|
| 2352 | devres_remove_group(dev, NULL);
|
| 2353 | else
|
| 2354 | devres_release_group(dev, NULL);
|
| 2355 |
|
| 2356 | return rc;
|
| 2357 | }
|
| 2358 | EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host);
|
| 2359 |
|
| 2360 | static const struct ata_port_info *ata_sff_find_valid_pi(
|
| 2361 | const struct ata_port_info * const *ppi)
|
| 2362 | {
|
| 2363 | int i;
|
| 2364 |
|
| 2365 |
|
| 2366 | for (i = 0; i < 2 && ppi[i]; i++)
|
| 2367 | if (ppi[i]->port_ops != &ata_dummy_port_ops)
|
| 2368 | return ppi[i];
|
| 2369 |
|
| 2370 | return NULL;
|
| 2371 | }
|
| 2372 |
|
| 2373 | static int ata_pci_init_one(struct pci_dev *pdev,
|
| 2374 | const struct ata_port_info * const *ppi,
|
| 2375 | const struct scsi_host_template *sht, void *host_priv,
|
| 2376 | int hflags, bool bmdma)
|
| 2377 | {
|
| 2378 | struct device *dev = &pdev->dev;
|
| 2379 | const struct ata_port_info *pi;
|
| 2380 | struct ata_host *host = NULL;
|
| 2381 | int rc;
|
| 2382 |
|
| 2383 | pi = ata_sff_find_valid_pi(ppi);
|
| 2384 | if (!pi) {
|
| 2385 | dev_err(&pdev->dev, "no valid port_info specified\n");
|
| 2386 | return -EINVAL;
|
| 2387 | }
|
| 2388 |
|
| 2389 | if (!devres_open_group(dev, NULL, GFP_KERNEL))
|
| 2390 | return -ENOMEM;
|
| 2391 |
|
| 2392 | rc = pcim_enable_device(pdev);
|
| 2393 | if (rc)
|
| 2394 | goto out;
|
| 2395 |
|
| 2396 | #ifdef CONFIG_ATA_BMDMA
|
| 2397 | if (bmdma)
|
| 2398 |
|
| 2399 | rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
|
| 2400 | else
|
| 2401 | #endif
|
| 2402 |
|
| 2403 | rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
|
| 2404 | if (rc)
|
| 2405 | goto out;
|
| 2406 | host->private_data = host_priv;
|
| 2407 | host->flags |= hflags;
|
| 2408 |
|
| 2409 | #ifdef CONFIG_ATA_BMDMA
|
| 2410 | if (bmdma) {
|
| 2411 | pci_set_master(pdev);
|
| 2412 | rc = ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht);
|
| 2413 | } else
|
| 2414 | #endif
|
| 2415 | rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht);
|
| 2416 | out:
|
| 2417 | if (rc == 0)
|
| 2418 | devres_remove_group(&pdev->dev, NULL);
|
| 2419 | else
|
| 2420 | devres_release_group(&pdev->dev, NULL);
|
| 2421 |
|
| 2422 | return rc;
|
| 2423 | }
|
| 2424 |
|
| 2425 | |
| 2426 | * ata_pci_sff_init_one - Initialize/register PIO-only PCI IDE controller
|
| 2427 | * @pdev: Controller to be initialized
|
| 2428 | * @ppi: array of port_info, must be enough for two ports
|
| 2429 | * @sht: scsi_host_template to use when registering the host
|
| 2430 | * @host_priv: host private_data
|
| 2431 | * @hflag: host flags
|
| 2432 | *
|
| 2433 | * This is a helper function which can be called from a driver's
|
| 2434 | * xxx_init_one() probe function if the hardware uses traditional
|
| 2435 | * IDE taskfile registers and is PIO only.
|
| 2436 | *
|
| 2437 | * ASSUMPTION:
|
| 2438 | * Nobody makes a single channel controller that appears solely as
|
| 2439 | * the secondary legacy port on PCI.
|
| 2440 | *
|
| 2441 | * LOCKING:
|
| 2442 | * Inherited from PCI layer (may sleep).
|
| 2443 | *
|
| 2444 | * RETURNS:
|
| 2445 | * Zero on success, negative on errno-based value on error.
|
| 2446 |
|
| 2447 | int ata_pci_sff_init_one(struct pci_dev *pdev,
|
| 2448 | const struct ata_port_info * const *ppi,
|
| 2449 | const struct scsi_host_template *sht, void *host_priv, int hflag)
|
| 2450 | {
|
| 2451 | return ata_pci_init_one(pdev, ppi, sht, host_priv, hflag, 0);
|
| 2452 | }
|
| 2453 | EXPORT_SYMBOL_GPL(ata_pci_sff_init_one);
|
| 2454 |
|
| 2455 | #endif
|
| 2456 |
|
| 2457 | |
| 2458 | * BMDMA support
|
| 2459 |
|
| 2460 |
|
| 2461 | #ifdef CONFIG_ATA_BMDMA
|
| 2462 |
|
| 2463 | const struct ata_port_operations ata_bmdma_port_ops = {
|
| 2464 | .inherits = &ata_sff_port_ops,
|
| 2465 |
|
| 2466 | .error_handler = ata_bmdma_error_handler,
|
| 2467 | .post_internal_cmd = ata_bmdma_post_internal_cmd,
|
| 2468 |
|
| 2469 | .qc_prep = ata_bmdma_qc_prep,
|
| 2470 | .qc_issue = ata_bmdma_qc_issue,
|
| 2471 |
|
| 2472 | .sff_irq_clear = ata_bmdma_irq_clear,
|
| 2473 | .bmdma_setup = ata_bmdma_setup,
|
| 2474 | .bmdma_start = ata_bmdma_start,
|
| 2475 | .bmdma_stop = ata_bmdma_stop,
|
| 2476 | .bmdma_status = ata_bmdma_status,
|
| 2477 |
|
| 2478 | .port_start = ata_bmdma_port_start,
|
| 2479 | };
|
| 2480 | EXPORT_SYMBOL_GPL(ata_bmdma_port_ops);
|
| 2481 |
|
| 2482 | const struct ata_port_operations ata_bmdma32_port_ops = {
|
| 2483 | .inherits = &ata_bmdma_port_ops,
|
| 2484 |
|
| 2485 | .sff_data_xfer = ata_sff_data_xfer32,
|
| 2486 | .port_start = ata_bmdma_port_start32,
|
| 2487 | };
|
| 2488 | EXPORT_SYMBOL_GPL(ata_bmdma32_port_ops);
|
| 2489 |
|
| 2490 | |
| 2491 | * ata_bmdma_fill_sg - Fill PCI IDE PRD table
|
| 2492 | * @qc: Metadata associated with taskfile to be transferred
|
| 2493 | *
|
| 2494 | * Fill PCI IDE PRD (scatter-gather) table with segments
|
| 2495 | * associated with the current disk command.
|
| 2496 | *
|
| 2497 | * LOCKING:
|
| 2498 | * spin_lock_irqsave(host lock)
|
| 2499 | *
|
| 2500 |
|
| 2501 | static void ata_bmdma_fill_sg(struct ata_queued_cmd *qc)
|
| 2502 | {
|
| 2503 | struct ata_port *ap = qc->ap;
|
| 2504 | struct ata_bmdma_prd *prd = ap->bmdma_prd;
|
| 2505 | struct scatterlist *sg;
|
| 2506 | unsigned int si, pi;
|
| 2507 |
|
| 2508 | pi = 0;
|
| 2509 | for_each_sg(qc->sg, sg, qc->n_elem, si) {
|
| 2510 | u32 addr, offset;
|
| 2511 | u32 sg_len, len;
|
| 2512 |
|
| 2513 | |
| 2514 | * Note h/w doesn't support 64-bit, so we unconditionally
|
| 2515 | * truncate dma_addr_t to u32.
|
| 2516 |
|
| 2517 | addr = (u32) sg_dma_address(sg);
|
| 2518 | sg_len = sg_dma_len(sg);
|
| 2519 |
|
| 2520 | while (sg_len) {
|
| 2521 | offset = addr & 0xffff;
|
| 2522 | len = sg_len;
|
| 2523 | if ((offset + sg_len) > 0x10000)
|
| 2524 | len = 0x10000 - offset;
|
| 2525 |
|
| 2526 | prd[pi].addr = cpu_to_le32(addr);
|
| 2527 | prd[pi].flags_len = cpu_to_le32(len & 0xffff);
|
| 2528 |
|
| 2529 | pi++;
|
| 2530 | sg_len -= len;
|
| 2531 | addr += len;
|
| 2532 | }
|
| 2533 | }
|
| 2534 |
|
| 2535 | prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
|
| 2536 | }
|
| 2537 |
|
| 2538 | |
| 2539 | * ata_bmdma_fill_sg_dumb - Fill PCI IDE PRD table
|
| 2540 | * @qc: Metadata associated with taskfile to be transferred
|
| 2541 | *
|
| 2542 | * Fill PCI IDE PRD (scatter-gather) table with segments
|
| 2543 | * associated with the current disk command. Perform the fill
|
| 2544 | * so that we avoid writing any length 64K records for
|
| 2545 | * controllers that don't follow the spec.
|
| 2546 | *
|
| 2547 | * LOCKING:
|
| 2548 | * spin_lock_irqsave(host lock)
|
| 2549 | *
|
| 2550 |
|
| 2551 | static void ata_bmdma_fill_sg_dumb(struct ata_queued_cmd *qc)
|
| 2552 | {
|
| 2553 | struct ata_port *ap = qc->ap;
|
| 2554 | struct ata_bmdma_prd *prd = ap->bmdma_prd;
|
| 2555 | struct scatterlist *sg;
|
| 2556 | unsigned int si, pi;
|
| 2557 |
|
| 2558 | pi = 0;
|
| 2559 | for_each_sg(qc->sg, sg, qc->n_elem, si) {
|
| 2560 | u32 addr, offset;
|
| 2561 | u32 sg_len, len, blen;
|
| 2562 |
|
| 2563 | |
| 2564 | * Note h/w doesn't support 64-bit, so we unconditionally
|
| 2565 | * truncate dma_addr_t to u32.
|
| 2566 |
|
| 2567 | addr = (u32) sg_dma_address(sg);
|
| 2568 | sg_len = sg_dma_len(sg);
|
| 2569 |
|
| 2570 | while (sg_len) {
|
| 2571 | offset = addr & 0xffff;
|
| 2572 | len = sg_len;
|
| 2573 | if ((offset + sg_len) > 0x10000)
|
| 2574 | len = 0x10000 - offset;
|
| 2575 |
|
| 2576 | blen = len & 0xffff;
|
| 2577 | prd[pi].addr = cpu_to_le32(addr);
|
| 2578 | if (blen == 0) {
|
| 2579 | |
| 2580 | cope with 0x0000 meaning 64K as the spec
|
| 2581 | says
|
| 2582 | prd[pi].flags_len = cpu_to_le32(0x8000);
|
| 2583 | blen = 0x8000;
|
| 2584 | prd[++pi].addr = cpu_to_le32(addr + 0x8000);
|
| 2585 | }
|
| 2586 | prd[pi].flags_len = cpu_to_le32(blen);
|
| 2587 |
|
| 2588 | pi++;
|
| 2589 | sg_len -= len;
|
| 2590 | addr += len;
|
| 2591 | }
|
| 2592 | }
|
| 2593 |
|
| 2594 | prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
|
| 2595 | }
|
| 2596 |
|
| 2597 | |
| 2598 | * ata_bmdma_qc_prep - Prepare taskfile for submission
|
| 2599 | * @qc: Metadata associated with taskfile to be prepared
|
| 2600 | *
|
| 2601 | * Prepare ATA taskfile for submission.
|
| 2602 | *
|
| 2603 | * LOCKING:
|
| 2604 | * spin_lock_irqsave(host lock)
|
| 2605 |
|
| 2606 | enum ata_completion_errors ata_bmdma_qc_prep(struct ata_queued_cmd *qc)
|
| 2607 | {
|
| 2608 | if (!(qc->flags & ATA_QCFLAG_DMAMAP))
|
| 2609 | return AC_ERR_OK;
|
| 2610 |
|
| 2611 | ata_bmdma_fill_sg(qc);
|
| 2612 |
|
| 2613 | return AC_ERR_OK;
|
| 2614 | }
|
| 2615 | EXPORT_SYMBOL_GPL(ata_bmdma_qc_prep);
|
| 2616 |
|
| 2617 | |
| 2618 | * ata_bmdma_dumb_qc_prep - Prepare taskfile for submission
|
| 2619 | * @qc: Metadata associated with taskfile to be prepared
|
| 2620 | *
|
| 2621 | * Prepare ATA taskfile for submission.
|
| 2622 | *
|
| 2623 | * LOCKING:
|
| 2624 | * spin_lock_irqsave(host lock)
|
| 2625 |
|
| 2626 | enum ata_completion_errors ata_bmdma_dumb_qc_prep(struct ata_queued_cmd *qc)
|
| 2627 | {
|
| 2628 | if (!(qc->flags & ATA_QCFLAG_DMAMAP))
|
| 2629 | return AC_ERR_OK;
|
| 2630 |
|
| 2631 | ata_bmdma_fill_sg_dumb(qc);
|
| 2632 |
|
| 2633 | return AC_ERR_OK;
|
| 2634 | }
|
| 2635 | EXPORT_SYMBOL_GPL(ata_bmdma_dumb_qc_prep);
|
| 2636 |
|
| 2637 | |
| 2638 | * ata_bmdma_qc_issue - issue taskfile to a BMDMA controller
|
| 2639 | * @qc: command to issue to device
|
| 2640 | *
|
| 2641 | * This function issues a PIO, NODATA or DMA command to a
|
| 2642 | * SFF/BMDMA controller. PIO and NODATA are handled by
|
| 2643 | * ata_sff_qc_issue().
|
| 2644 | *
|
| 2645 | * LOCKING:
|
| 2646 | * spin_lock_irqsave(host lock)
|
| 2647 | *
|
| 2648 | * RETURNS:
|
| 2649 | * Zero on success, AC_ERR_* mask on failure
|
| 2650 |
|
| 2651 | unsigned int ata_bmdma_qc_issue(struct ata_queued_cmd *qc)
|
| 2652 | {
|
| 2653 | struct ata_port *ap = qc->ap;
|
| 2654 | struct ata_link *link = qc->dev->link;
|
| 2655 |
|
| 2656 |
|
| 2657 | if (!ata_is_dma(qc->tf.protocol))
|
| 2658 | return ata_sff_qc_issue(qc);
|
| 2659 |
|
| 2660 |
|
| 2661 | ata_dev_select(ap, qc->dev->devno, 1, 0);
|
| 2662 |
|
| 2663 |
|
| 2664 | switch (qc->tf.protocol) {
|
| 2665 | case ATA_PROT_DMA:
|
| 2666 | WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
|
| 2667 |
|
| 2668 | trace_ata_tf_load(ap, &qc->tf);
|
| 2669 | ap->ops->sff_tf_load(ap, &qc->tf);
|
| 2670 | trace_ata_bmdma_setup(ap, &qc->tf, qc->tag);
|
| 2671 | ap->ops->bmdma_setup(qc);
|
| 2672 | trace_ata_bmdma_start(ap, &qc->tf, qc->tag);
|
| 2673 | ap->ops->bmdma_start(qc);
|
| 2674 | ap->hsm_task_state = HSM_ST_LAST;
|
| 2675 | break;
|
| 2676 |
|
| 2677 | case ATAPI_PROT_DMA:
|
| 2678 | WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
|
| 2679 |
|
| 2680 | trace_ata_tf_load(ap, &qc->tf);
|
| 2681 | ap->ops->sff_tf_load(ap, &qc->tf);
|
| 2682 | trace_ata_bmdma_setup(ap, &qc->tf, qc->tag);
|
| 2683 | ap->ops->bmdma_setup(qc);
|
| 2684 | ap->hsm_task_state = HSM_ST_FIRST;
|
| 2685 |
|
| 2686 |
|
| 2687 | if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
|
| 2688 | ata_sff_queue_pio_task(link, 0);
|
| 2689 | break;
|
| 2690 |
|
| 2691 | default:
|
| 2692 | WARN_ON(1);
|
| 2693 | return AC_ERR_SYSTEM;
|
| 2694 | }
|
| 2695 |
|
| 2696 | return 0;
|
| 2697 | }
|
| 2698 | EXPORT_SYMBOL_GPL(ata_bmdma_qc_issue);
|
| 2699 |
|
| 2700 | |
| 2701 | * ata_bmdma_port_intr - Handle BMDMA port interrupt
|
| 2702 | * @ap: Port on which interrupt arrived (possibly...)
|
| 2703 | * @qc: Taskfile currently active in engine
|
| 2704 | *
|
| 2705 | * Handle port interrupt for given queued command.
|
| 2706 | *
|
| 2707 | * LOCKING:
|
| 2708 | * spin_lock_irqsave(host lock)
|
| 2709 | *
|
| 2710 | * RETURNS:
|
| 2711 | * One if interrupt was handled, zero if not (shared irq).
|
| 2712 |
|
| 2713 | unsigned int ata_bmdma_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
|
| 2714 | {
|
| 2715 | struct ata_eh_info *ehi = &ap->link.eh_info;
|
| 2716 | u8 host_stat = 0;
|
| 2717 | bool bmdma_stopped = false;
|
| 2718 | unsigned int handled;
|
| 2719 |
|
| 2720 | if (ap->hsm_task_state == HSM_ST_LAST && ata_is_dma(qc->tf.protocol)) {
|
| 2721 |
|
| 2722 | host_stat = ap->ops->bmdma_status(ap);
|
| 2723 | trace_ata_bmdma_status(ap, host_stat);
|
| 2724 |
|
| 2725 |
|
| 2726 | if (!(host_stat & ATA_DMA_INTR))
|
| 2727 | return ata_sff_idle_irq(ap);
|
| 2728 |
|
| 2729 |
|
| 2730 | trace_ata_bmdma_stop(ap, &qc->tf, qc->tag);
|
| 2731 | ap->ops->bmdma_stop(qc);
|
| 2732 | bmdma_stopped = true;
|
| 2733 |
|
| 2734 | if (unlikely(host_stat & ATA_DMA_ERR)) {
|
| 2735 |
|
| 2736 | qc->err_mask |= AC_ERR_HOST_BUS;
|
| 2737 | ap->hsm_task_state = HSM_ST_ERR;
|
| 2738 | }
|
| 2739 | }
|
| 2740 |
|
| 2741 | handled = __ata_sff_port_intr(ap, qc, bmdma_stopped);
|
| 2742 |
|
| 2743 | if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol))
|
| 2744 | ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
|
| 2745 |
|
| 2746 | return handled;
|
| 2747 | }
|
| 2748 | EXPORT_SYMBOL_GPL(ata_bmdma_port_intr);
|
| 2749 |
|
| 2750 | |
| 2751 | * ata_bmdma_interrupt - Default BMDMA ATA host interrupt handler
|
| 2752 | * @irq: irq line (unused)
|
| 2753 | * @dev_instance: pointer to our ata_host information structure
|
| 2754 | *
|
| 2755 | * Default interrupt handler for PCI IDE devices. Calls
|
| 2756 | * ata_bmdma_port_intr() for each port that is not disabled.
|
| 2757 | *
|
| 2758 | * LOCKING:
|
| 2759 | * Obtains host lock during operation.
|
| 2760 | *
|
| 2761 | * RETURNS:
|
| 2762 | * IRQ_NONE or IRQ_HANDLED.
|
| 2763 |
|
| 2764 | irqreturn_t ata_bmdma_interrupt(int irq, void *dev_instance)
|
| 2765 | {
|
| 2766 | return __ata_sff_interrupt(irq, dev_instance, ata_bmdma_port_intr);
|
| 2767 | }
|
| 2768 | EXPORT_SYMBOL_GPL(ata_bmdma_interrupt);
|
| 2769 |
|
| 2770 | |
| 2771 | * ata_bmdma_error_handler - Stock error handler for BMDMA controller
|
| 2772 | * @ap: port to handle error for
|
| 2773 | *
|
| 2774 | * Stock error handler for BMDMA controller. It can handle both
|
| 2775 | * PATA and SATA controllers. Most BMDMA controllers should be
|
| 2776 | * able to use this EH as-is or with some added handling before
|
| 2777 | * and after.
|
| 2778 | *
|
| 2779 | * LOCKING:
|
| 2780 | * Kernel thread context (may sleep)
|
| 2781 |
|
| 2782 | void ata_bmdma_error_handler(struct ata_port *ap)
|
| 2783 | __must_hold(&ap->host->eh_mutex)
|
| 2784 | {
|
| 2785 | struct ata_queued_cmd *qc;
|
| 2786 | unsigned long flags;
|
| 2787 | bool thaw = false;
|
| 2788 |
|
| 2789 | qc = __ata_qc_from_tag(ap, ap->link.active_tag);
|
| 2790 | if (qc && !(qc->flags & ATA_QCFLAG_EH))
|
| 2791 | qc = NULL;
|
| 2792 |
|
| 2793 |
|
| 2794 | spin_lock_irqsave(ap->lock, flags);
|
| 2795 |
|
| 2796 | if (qc && ata_is_dma(qc->tf.protocol)) {
|
| 2797 | u8 host_stat;
|
| 2798 |
|
| 2799 | host_stat = ap->ops->bmdma_status(ap);
|
| 2800 | trace_ata_bmdma_status(ap, host_stat);
|
| 2801 |
|
| 2802 | |
| 2803 | * setting DMA_ERR bit and timing out. As it wasn't
|
| 2804 | * really a timeout event, adjust error mask and
|
| 2805 | * cancel frozen state.
|
| 2806 |
|
| 2807 | if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) {
|
| 2808 | qc->err_mask = AC_ERR_HOST_BUS;
|
| 2809 | thaw = true;
|
| 2810 | }
|
| 2811 |
|
| 2812 | trace_ata_bmdma_stop(ap, &qc->tf, qc->tag);
|
| 2813 | ap->ops->bmdma_stop(qc);
|
| 2814 |
|
| 2815 |
|
| 2816 | if (thaw) {
|
| 2817 | ap->ops->sff_check_status(ap);
|
| 2818 | if (ap->ops->sff_irq_clear)
|
| 2819 | ap->ops->sff_irq_clear(ap);
|
| 2820 | }
|
| 2821 | }
|
| 2822 |
|
| 2823 | spin_unlock_irqrestore(ap->lock, flags);
|
| 2824 |
|
| 2825 | if (thaw)
|
| 2826 | ata_eh_thaw_port(ap);
|
| 2827 |
|
| 2828 | ata_sff_error_handler(ap);
|
| 2829 | }
|
| 2830 | EXPORT_SYMBOL_GPL(ata_bmdma_error_handler);
|
| 2831 |
|
| 2832 | |
| 2833 | * ata_bmdma_post_internal_cmd - Stock post_internal_cmd for BMDMA
|
| 2834 | * @qc: internal command to clean up
|
| 2835 | *
|
| 2836 | * LOCKING:
|
| 2837 | * Kernel thread context (may sleep)
|
| 2838 |
|
| 2839 | void ata_bmdma_post_internal_cmd(struct ata_queued_cmd *qc)
|
| 2840 | {
|
| 2841 | struct ata_port *ap = qc->ap;
|
| 2842 | unsigned long flags;
|
| 2843 |
|
| 2844 | if (ata_is_dma(qc->tf.protocol)) {
|
| 2845 | spin_lock_irqsave(ap->lock, flags);
|
| 2846 | trace_ata_bmdma_stop(ap, &qc->tf, qc->tag);
|
| 2847 | ap->ops->bmdma_stop(qc);
|
| 2848 | spin_unlock_irqrestore(ap->lock, flags);
|
| 2849 | }
|
| 2850 | }
|
| 2851 | EXPORT_SYMBOL_GPL(ata_bmdma_post_internal_cmd);
|
| 2852 |
|
| 2853 | |
| 2854 | * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
|
| 2855 | * @ap: Port associated with this ATA transaction.
|
| 2856 | *
|
| 2857 | * Clear interrupt and error flags in DMA status register.
|
| 2858 | *
|
| 2859 | * May be used as the irq_clear() entry in ata_port_operations.
|
| 2860 | *
|
| 2861 | * LOCKING:
|
| 2862 | * spin_lock_irqsave(host lock)
|
| 2863 |
|
| 2864 | void ata_bmdma_irq_clear(struct ata_port *ap)
|
| 2865 | {
|
| 2866 | void __iomem *mmio = ap->ioaddr.bmdma_addr;
|
| 2867 |
|
| 2868 | if (!mmio)
|
| 2869 | return;
|
| 2870 |
|
| 2871 | iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS);
|
| 2872 | }
|
| 2873 | EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear);
|
| 2874 |
|
| 2875 | |
| 2876 | * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
|
| 2877 | * @qc: Info associated with this ATA transaction.
|
| 2878 | *
|
| 2879 | * LOCKING:
|
| 2880 | * spin_lock_irqsave(host lock)
|
| 2881 |
|
| 2882 | void ata_bmdma_setup(struct ata_queued_cmd *qc)
|
| 2883 | {
|
| 2884 | struct ata_port *ap = qc->ap;
|
| 2885 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
|
| 2886 | u8 dmactl;
|
| 2887 |
|
| 2888 |
|
| 2889 | mb();
|
| 2890 | iowrite32(ap->bmdma_prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
|
| 2891 |
|
| 2892 |
|
| 2893 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
|
| 2894 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
|
| 2895 | if (!rw)
|
| 2896 | dmactl |= ATA_DMA_WR;
|
| 2897 | iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
|
| 2898 |
|
| 2899 |
|
| 2900 | ap->ops->sff_exec_command(ap, &qc->tf);
|
| 2901 | }
|
| 2902 | EXPORT_SYMBOL_GPL(ata_bmdma_setup);
|
| 2903 |
|
| 2904 | |
| 2905 | * ata_bmdma_start - Start a PCI IDE BMDMA transaction
|
| 2906 | * @qc: Info associated with this ATA transaction.
|
| 2907 | *
|
| 2908 | * LOCKING:
|
| 2909 | * spin_lock_irqsave(host lock)
|
| 2910 |
|
| 2911 | void ata_bmdma_start(struct ata_queued_cmd *qc)
|
| 2912 | {
|
| 2913 | struct ata_port *ap = qc->ap;
|
| 2914 | u8 dmactl;
|
| 2915 |
|
| 2916 |
|
| 2917 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
|
| 2918 | iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
|
| 2919 |
|
| 2920 | |
| 2921 | * flush the mmio write. However, control also passes
|
| 2922 | * to the hardware at this point, and it will interrupt
|
| 2923 | * us when we are to resume control. So, in effect,
|
| 2924 | * we don't care when the mmio write flushes.
|
| 2925 | * Further, a read of the DMA status register _immediately_
|
| 2926 | * following the write may not be what certain flaky hardware
|
| 2927 | * is expected, so I think it is best to not add a readb()
|
| 2928 | * without first all the MMIO ATA cards/mobos.
|
| 2929 | * Or maybe I'm just being paranoid.
|
| 2930 | *
|
| 2931 | * FIXME: The posting of this write means I/O starts are
|
| 2932 | * unnecessarily delayed for MMIO
|
| 2933 |
|
| 2934 | }
|
| 2935 | EXPORT_SYMBOL_GPL(ata_bmdma_start);
|
| 2936 |
|
| 2937 | |
| 2938 | * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
|
| 2939 | * @qc: Command we are ending DMA for
|
| 2940 | *
|
| 2941 | * Clears the ATA_DMA_START flag in the dma control register
|
| 2942 | *
|
| 2943 | * May be used as the bmdma_stop() entry in ata_port_operations.
|
| 2944 | *
|
| 2945 | * LOCKING:
|
| 2946 | * spin_lock_irqsave(host lock)
|
| 2947 |
|
| 2948 | void ata_bmdma_stop(struct ata_queued_cmd *qc)
|
| 2949 | {
|
| 2950 | struct ata_port *ap = qc->ap;
|
| 2951 | void __iomem *mmio = ap->ioaddr.bmdma_addr;
|
| 2952 |
|
| 2953 |
|
| 2954 | iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
|
| 2955 | mmio + ATA_DMA_CMD);
|
| 2956 |
|
| 2957 |
|
| 2958 | ata_sff_dma_pause(ap);
|
| 2959 | }
|
| 2960 | EXPORT_SYMBOL_GPL(ata_bmdma_stop);
|
| 2961 |
|
| 2962 | |
| 2963 | * ata_bmdma_status - Read PCI IDE BMDMA status
|
| 2964 | * @ap: Port associated with this ATA transaction.
|
| 2965 | *
|
| 2966 | * Read and return BMDMA status register.
|
| 2967 | *
|
| 2968 | * May be used as the bmdma_status() entry in ata_port_operations.
|
| 2969 | *
|
| 2970 | * LOCKING:
|
| 2971 | * spin_lock_irqsave(host lock)
|
| 2972 |
|
| 2973 | u8 ata_bmdma_status(struct ata_port *ap)
|
| 2974 | {
|
| 2975 | return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
|
| 2976 | }
|
| 2977 | EXPORT_SYMBOL_GPL(ata_bmdma_status);
|
| 2978 |
|
| 2979 |
|
| 2980 | |
| 2981 | * ata_bmdma_port_start - Set port up for bmdma.
|
| 2982 | * @ap: Port to initialize
|
| 2983 | *
|
| 2984 | * Called just after data structures for each port are
|
| 2985 | * initialized. Allocates space for PRD table.
|
| 2986 | *
|
| 2987 | * May be used as the port_start() entry in ata_port_operations.
|
| 2988 | *
|
| 2989 | * LOCKING:
|
| 2990 | * Inherited from caller.
|
| 2991 |
|
| 2992 | int ata_bmdma_port_start(struct ata_port *ap)
|
| 2993 | {
|
| 2994 | if (ap->mwdma_mask || ap->udma_mask) {
|
| 2995 | ap->bmdma_prd =
|
| 2996 | dmam_alloc_coherent(ap->host->dev, ATA_PRD_TBL_SZ,
|
| 2997 | &ap->bmdma_prd_dma, GFP_KERNEL);
|
| 2998 | if (!ap->bmdma_prd)
|
| 2999 | return -ENOMEM;
|
| 3000 | }
|
| 3001 |
|
| 3002 | return 0;
|
| 3003 | }
|
| 3004 | EXPORT_SYMBOL_GPL(ata_bmdma_port_start);
|
| 3005 |
|
| 3006 | |
| 3007 | * ata_bmdma_port_start32 - Set port up for dma.
|
| 3008 | * @ap: Port to initialize
|
| 3009 | *
|
| 3010 | * Called just after data structures for each port are
|
| 3011 | * initialized. Enables 32bit PIO and allocates space for PRD
|
| 3012 | * table.
|
| 3013 | *
|
| 3014 | * May be used as the port_start() entry in ata_port_operations for
|
| 3015 | * devices that are capable of 32bit PIO.
|
| 3016 | *
|
| 3017 | * LOCKING:
|
| 3018 | * Inherited from caller.
|
| 3019 |
|
| 3020 | int ata_bmdma_port_start32(struct ata_port *ap)
|
| 3021 | {
|
| 3022 | ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
|
| 3023 | return ata_bmdma_port_start(ap);
|
| 3024 | }
|
| 3025 | EXPORT_SYMBOL_GPL(ata_bmdma_port_start32);
|
| 3026 |
|
| 3027 | #ifdef CONFIG_PCI
|
| 3028 |
|
| 3029 | |
| 3030 | * ata_pci_bmdma_clear_simplex - attempt to kick device out of simplex
|
| 3031 | * @pdev: PCI device
|
| 3032 | *
|
| 3033 | * Some PCI ATA devices report simplex mode but in fact can be told to
|
| 3034 | * enter non simplex mode. This implements the necessary logic to
|
| 3035 | * perform the task on such devices. Calling it on other devices will
|
| 3036 | * have -undefined- behaviour.
|
| 3037 |
|
| 3038 | int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev)
|
| 3039 | {
|
| 3040 | #ifdef CONFIG_HAS_IOPORT
|
| 3041 | unsigned long bmdma = pci_resource_start(pdev, 4);
|
| 3042 | u8 simplex;
|
| 3043 |
|
| 3044 | if (bmdma == 0)
|
| 3045 | return -ENOENT;
|
| 3046 |
|
| 3047 | simplex = inb(bmdma + 0x02);
|
| 3048 | outb(simplex & 0x60, bmdma + 0x02);
|
| 3049 | simplex = inb(bmdma + 0x02);
|
| 3050 | if (simplex & 0x80)
|
| 3051 | return -EOPNOTSUPP;
|
| 3052 | return 0;
|
| 3053 | #else
|
| 3054 | return -ENOENT;
|
| 3055 | #endif
|
| 3056 | }
|
| 3057 | EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex);
|
| 3058 |
|
| 3059 | static void ata_bmdma_nodma(struct ata_host *host, const char *reason)
|
| 3060 | {
|
| 3061 | int i;
|
| 3062 |
|
| 3063 | dev_err(host->dev, "BMDMA: %s, falling back to PIO\n", reason);
|
| 3064 |
|
| 3065 | for (i = 0; i < 2; i++) {
|
| 3066 | host->ports[i]->mwdma_mask = 0;
|
| 3067 | host->ports[i]->udma_mask = 0;
|
| 3068 | }
|
| 3069 | }
|
| 3070 |
|
| 3071 | |
| 3072 | * ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host
|
| 3073 | * @host: target ATA host
|
| 3074 | *
|
| 3075 | * Acquire PCI BMDMA resources and initialize @host accordingly.
|
| 3076 | *
|
| 3077 | * LOCKING:
|
| 3078 | * Inherited from calling layer (may sleep).
|
| 3079 |
|
| 3080 | void ata_pci_bmdma_init(struct ata_host *host)
|
| 3081 | {
|
| 3082 | struct device *gdev = host->dev;
|
| 3083 | struct pci_dev *pdev = to_pci_dev(gdev);
|
| 3084 | int i, rc;
|
| 3085 |
|
| 3086 |
|
| 3087 | if (pci_resource_start(pdev, 4) == 0) {
|
| 3088 | ata_bmdma_nodma(host, "BAR4 is zero");
|
| 3089 | return;
|
| 3090 | }
|
| 3091 |
|
| 3092 | |
| 3093 | * Some controllers require BMDMA region to be initialized
|
| 3094 | * even if DMA is not in use to clear IRQ status via
|
| 3095 | * ->sff_irq_clear method. Try to initialize bmdma_addr
|
| 3096 | * regardless of dma masks.
|
| 3097 |
|
| 3098 | rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
|
| 3099 | if (rc)
|
| 3100 | ata_bmdma_nodma(host, "failed to set dma mask");
|
| 3101 |
|
| 3102 |
|
| 3103 | rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev));
|
| 3104 | if (rc) {
|
| 3105 | ata_bmdma_nodma(host, "failed to request/iomap BAR4");
|
| 3106 | return;
|
| 3107 | }
|
| 3108 | host->iomap = pcim_iomap_table(pdev);
|
| 3109 |
|
| 3110 | for (i = 0; i < 2; i++) {
|
| 3111 | struct ata_port *ap = host->ports[i];
|
| 3112 | void __iomem *bmdma = host->iomap[4] + 8 * i;
|
| 3113 |
|
| 3114 | if (ata_port_is_dummy(ap))
|
| 3115 | continue;
|
| 3116 |
|
| 3117 | ap->ioaddr.bmdma_addr = bmdma;
|
| 3118 | if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) &&
|
| 3119 | (ioread8(bmdma + 2) & 0x80))
|
| 3120 | host->flags |= ATA_HOST_SIMPLEX;
|
| 3121 |
|
| 3122 | ata_port_desc(ap, "bmdma 0x%llx",
|
| 3123 | (unsigned long long)pci_resource_start(pdev, 4) + 8 * i);
|
| 3124 | }
|
| 3125 | }
|
| 3126 | EXPORT_SYMBOL_GPL(ata_pci_bmdma_init);
|
| 3127 |
|
| 3128 | |
| 3129 | * ata_pci_bmdma_prepare_host - helper to prepare PCI BMDMA ATA host
|
| 3130 | * @pdev: target PCI device
|
| 3131 | * @ppi: array of port_info, must be enough for two ports
|
| 3132 | * @r_host: out argument for the initialized ATA host
|
| 3133 | *
|
| 3134 | * Helper to allocate BMDMA ATA host for @pdev, acquire all PCI
|
| 3135 | * resources and initialize it accordingly in one go.
|
| 3136 | *
|
| 3137 | * LOCKING:
|
| 3138 | * Inherited from calling layer (may sleep).
|
| 3139 | *
|
| 3140 | * RETURNS:
|
| 3141 | * 0 on success, -errno otherwise.
|
| 3142 |
|
| 3143 | int ata_pci_bmdma_prepare_host(struct pci_dev *pdev,
|
| 3144 | const struct ata_port_info * const * ppi,
|
| 3145 | struct ata_host **r_host)
|
| 3146 | {
|
| 3147 | int rc;
|
| 3148 |
|
| 3149 | rc = ata_pci_sff_prepare_host(pdev, ppi, r_host);
|
| 3150 | if (rc)
|
| 3151 | return rc;
|
| 3152 |
|
| 3153 | ata_pci_bmdma_init(*r_host);
|
| 3154 | return 0;
|
| 3155 | }
|
| 3156 | EXPORT_SYMBOL_GPL(ata_pci_bmdma_prepare_host);
|
| 3157 |
|
| 3158 | |
| 3159 | * ata_pci_bmdma_init_one - Initialize/register BMDMA PCI IDE controller
|
| 3160 | * @pdev: Controller to be initialized
|
| 3161 | * @ppi: array of port_info, must be enough for two ports
|
| 3162 | * @sht: scsi_host_template to use when registering the host
|
| 3163 | * @host_priv: host private_data
|
| 3164 | * @hflags: host flags
|
| 3165 | *
|
| 3166 | * This function is similar to ata_pci_sff_init_one() but also
|
| 3167 | * takes care of BMDMA initialization.
|
| 3168 | *
|
| 3169 | * LOCKING:
|
| 3170 | * Inherited from PCI layer (may sleep).
|
| 3171 | *
|
| 3172 | * RETURNS:
|
| 3173 | * Zero on success, negative on errno-based value on error.
|
| 3174 |
|
| 3175 | int ata_pci_bmdma_init_one(struct pci_dev *pdev,
|
| 3176 | const struct ata_port_info * const * ppi,
|
| 3177 | const struct scsi_host_template *sht, void *host_priv,
|
| 3178 | int hflags)
|
| 3179 | {
|
| 3180 | return ata_pci_init_one(pdev, ppi, sht, host_priv, hflags, 1);
|
| 3181 | }
|
| 3182 | EXPORT_SYMBOL_GPL(ata_pci_bmdma_init_one);
|
| 3183 |
|
| 3184 | #endif
|
| 3185 | #endif
|
| 3186 |
|
| 3187 | |
| 3188 | * ata_sff_port_init - Initialize SFF/BMDMA ATA port
|
| 3189 | * @ap: Port to initialize
|
| 3190 | *
|
| 3191 | * Called on port allocation to initialize SFF/BMDMA specific
|
| 3192 | * fields.
|
| 3193 | *
|
| 3194 | * LOCKING:
|
| 3195 | * None.
|
| 3196 |
|
| 3197 | void ata_sff_port_init(struct ata_port *ap)
|
| 3198 | {
|
| 3199 | INIT_DELAYED_WORK(&ap->sff_pio_task, ata_sff_pio_task);
|
| 3200 | ap->ctl = ATA_DEVCTL_OBS;
|
| 3201 | ap->last_ctl = 0xFF;
|
| 3202 | }
|
| 3203 |
|
| 3204 | int __init ata_sff_init(void)
|
| 3205 | {
|
| 3206 | ata_sff_wq = alloc_workqueue("ata_sff", WQ_MEM_RECLAIM | WQ_PERCPU,
|
| 3207 | WQ_MAX_ACTIVE);
|
| 3208 | if (!ata_sff_wq)
|
| 3209 | return -ENOMEM;
|
| 3210 |
|
| 3211 | return 0;
|
| 3212 | }
|
| 3213 |
|
| 3214 | void ata_sff_exit(void)
|
| 3215 | {
|
| 3216 | destroy_workqueue(ata_sff_wq);
|
| 3217 | }
|