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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * ps3vram - Use extra PS3 video ram as block device.
4 *
5 * Copyright 2009 Sony Corporation
6 *
7 * Based on the MTD ps3vram driver, which is
8 * Copyright (c) 2007-2008 Jim Paris <[email protected]>
9 * Added support RSX DMA Vivien Chappelier <[email protected]>
10 */
11
12#include <linux/blkdev.h>
13#include <linux/delay.h>
14#include <linux/module.h>
15#include <linux/proc_fs.h>
16#include <linux/seq_file.h>
17#include <linux/slab.h>
18
19#include <asm/cell-regs.h>
20#include <asm/firmware.h>
21#include <asm/lv1call.h>
22#include <asm/ps3.h>
23#include <asm/ps3gpu.h>
24
25
26#define DEVICE_NAME "ps3vram"
27
28
29#define XDR_BUF_SIZE (2 * 1024 * 1024) /* XDR buffer (must be 1MiB aligned) */
30#define XDR_IOIF 0x0c000000
31
32#define FIFO_BASE XDR_IOIF
33#define FIFO_SIZE (64 * 1024)
34
35#define DMA_PAGE_SIZE (4 * 1024)
36
37#define CACHE_PAGE_SIZE (256 * 1024)
38#define CACHE_PAGE_COUNT ((XDR_BUF_SIZE - FIFO_SIZE) / CACHE_PAGE_SIZE)
39
40#define CACHE_OFFSET CACHE_PAGE_SIZE
41#define FIFO_OFFSET 0
42
43#define CTRL_PUT 0x10
44#define CTRL_GET 0x11
45#define CTRL_TOP 0x15
46
47#define UPLOAD_SUBCH 1
48#define DOWNLOAD_SUBCH 2
49
50#define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c
51#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104
52
53#define CACHE_PAGE_PRESENT 1
54#define CACHE_PAGE_DIRTY 2
55
56struct ps3vram_tag {
57 unsigned int address;
58 unsigned int flags;
59};
60
61struct ps3vram_cache {
62 unsigned int page_count;
63 unsigned int page_size;
64 struct ps3vram_tag *tags;
65 unsigned int hit;
66 unsigned int miss;
67};
68
69struct ps3vram_priv {
70 struct gendisk *gendisk;
71
72 u64 size;
73
74 u64 memory_handle;
75 u64 context_handle;
76 u32 __iomem *ctrl;
77 void __iomem *reports;
78 u8 *xdr_buf;
79
80 u32 *fifo_base;
81 u32 *fifo_ptr;
82
83 struct ps3vram_cache cache;
84
85 spinlock_t lock; /* protecting list of bios */
86 struct bio_list list;
87};
88
89
90static int ps3vram_major;
91
92#define DMA_NOTIFIER_HANDLE_BASE 0x66604200 /* first DMA notifier handle */
93#define DMA_NOTIFIER_OFFSET_BASE 0x1000 /* first DMA notifier offset */
94#define DMA_NOTIFIER_SIZE 0x40
95#define NOTIFIER 7 /* notifier used for completion report */
96
97static char *size = "256M";
98module_param(size, charp, 0);
99MODULE_PARM_DESC(size, "memory size");
100
101static u32 __iomem *ps3vram_get_notifier(void __iomem *reports, int notifier)
102{
103 return reports + DMA_NOTIFIER_OFFSET_BASE +
104 DMA_NOTIFIER_SIZE * notifier;
105}
106
107static void ps3vram_notifier_reset(struct ps3_system_bus_device *dev)
108{
109 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
110 u32 __iomem *notify = ps3vram_get_notifier(priv->reports, NOTIFIER);
111 int i;
112
113 for (i = 0; i < 4; i++)
114 iowrite32be(0xffffffff, notify + i);
115}
116
117static int ps3vram_notifier_wait(struct ps3_system_bus_device *dev,
118 unsigned int timeout_ms)
119{
120 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
121 u32 __iomem *notify = ps3vram_get_notifier(priv->reports, NOTIFIER);
122 unsigned long timeout;
123
124 for (timeout = 20; timeout; timeout--) {
125 if (!ioread32be(notify + 3))
126 return 0;
127 udelay(10);
128 }
129
130 timeout = jiffies + msecs_to_jiffies(timeout_ms);
131
132 do {
133 if (!ioread32be(notify + 3))
134 return 0;
135 msleep(1);
136 } while (time_before(jiffies, timeout));
137
138 return -ETIMEDOUT;
139}
140
141static void ps3vram_init_ring(struct ps3_system_bus_device *dev)
142{
143 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
144
145 iowrite32be(FIFO_BASE + FIFO_OFFSET, priv->ctrl + CTRL_PUT);
146 iowrite32be(FIFO_BASE + FIFO_OFFSET, priv->ctrl + CTRL_GET);
147}
148
149static int ps3vram_wait_ring(struct ps3_system_bus_device *dev,
150 unsigned int timeout_ms)
151{
152 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
153 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
154
155 do {
156 if (ioread32be(priv->ctrl + CTRL_PUT) == ioread32be(priv->ctrl + CTRL_GET))
157 return 0;
158 msleep(1);
159 } while (time_before(jiffies, timeout));
160
161 dev_warn(&dev->core, "FIFO timeout (%08x/%08x/%08x)\n",
162 ioread32be(priv->ctrl + CTRL_PUT), ioread32be(priv->ctrl + CTRL_GET),
163 ioread32be(priv->ctrl + CTRL_TOP));
164
165 return -ETIMEDOUT;
166}
167
168static void ps3vram_out_ring(struct ps3vram_priv *priv, u32 data)
169{
170 *(priv->fifo_ptr)++ = data;
171}
172
173static void ps3vram_begin_ring(struct ps3vram_priv *priv, u32 chan, u32 tag,
174 u32 size)
175{
176 ps3vram_out_ring(priv, (size << 18) | (chan << 13) | tag);
177}
178
179static void ps3vram_rewind_ring(struct ps3_system_bus_device *dev)
180{
181 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
182 int status;
183
184 ps3vram_out_ring(priv, 0x20000000 | (FIFO_BASE + FIFO_OFFSET));
185
186 iowrite32be(FIFO_BASE + FIFO_OFFSET, priv->ctrl + CTRL_PUT);
187
188 /* asking the HV for a blit will kick the FIFO */
189 status = lv1_gpu_fb_blit(priv->context_handle, 0, 0, 0, 0);
190 if (status)
191 dev_err(&dev->core, "%s: lv1_gpu_fb_blit failed %d\n",
192 __func__, status);
193
194 priv->fifo_ptr = priv->fifo_base;
195}
196
197static void ps3vram_fire_ring(struct ps3_system_bus_device *dev)
198{
199 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
200 int status;
201
202 mutex_lock(&ps3_gpu_mutex);
203
204 iowrite32be(FIFO_BASE + FIFO_OFFSET + (priv->fifo_ptr - priv->fifo_base)
205 * sizeof(u32), priv->ctrl + CTRL_PUT);
206
207 /* asking the HV for a blit will kick the FIFO */
208 status = lv1_gpu_fb_blit(priv->context_handle, 0, 0, 0, 0);
209 if (status)
210 dev_err(&dev->core, "%s: lv1_gpu_fb_blit failed %d\n",
211 __func__, status);
212
213 if ((priv->fifo_ptr - priv->fifo_base) * sizeof(u32) >
214 FIFO_SIZE - 1024) {
215 dev_dbg(&dev->core, "FIFO full, rewinding\n");
216 ps3vram_wait_ring(dev, 200);
217 ps3vram_rewind_ring(dev);
218 }
219
220 mutex_unlock(&ps3_gpu_mutex);
221}
222
223static void ps3vram_bind(struct ps3_system_bus_device *dev)
224{
225 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
226
227 ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0, 1);
228 ps3vram_out_ring(priv, 0x31337303);
229 ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x180, 3);
230 ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER);
231 ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */
232 ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */
233
234 ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0, 1);
235 ps3vram_out_ring(priv, 0x3137c0de);
236 ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x180, 3);
237 ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER);
238 ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */
239 ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */
240
241 ps3vram_fire_ring(dev);
242}
243
244static int ps3vram_upload(struct ps3_system_bus_device *dev,
245 unsigned int src_offset, unsigned int dst_offset,
246 int len, int count)
247{
248 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
249
250 ps3vram_begin_ring(priv, UPLOAD_SUBCH,
251 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
252 ps3vram_out_ring(priv, XDR_IOIF + src_offset);
253 ps3vram_out_ring(priv, dst_offset);
254 ps3vram_out_ring(priv, len);
255 ps3vram_out_ring(priv, len);
256 ps3vram_out_ring(priv, len);
257 ps3vram_out_ring(priv, count);
258 ps3vram_out_ring(priv, (1 << 8) | 1);
259 ps3vram_out_ring(priv, 0);
260
261 ps3vram_notifier_reset(dev);
262 ps3vram_begin_ring(priv, UPLOAD_SUBCH,
263 NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1);
264 ps3vram_out_ring(priv, 0);
265 ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x100, 1);
266 ps3vram_out_ring(priv, 0);
267 ps3vram_fire_ring(dev);
268 if (ps3vram_notifier_wait(dev, 200) < 0) {
269 dev_warn(&dev->core, "%s: Notifier timeout\n", __func__);
270 return -1;
271 }
272
273 return 0;
274}
275
276static int ps3vram_download(struct ps3_system_bus_device *dev,
277 unsigned int src_offset, unsigned int dst_offset,
278 int len, int count)
279{
280 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
281
282 ps3vram_begin_ring(priv, DOWNLOAD_SUBCH,
283 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
284 ps3vram_out_ring(priv, src_offset);
285 ps3vram_out_ring(priv, XDR_IOIF + dst_offset);
286 ps3vram_out_ring(priv, len);
287 ps3vram_out_ring(priv, len);
288 ps3vram_out_ring(priv, len);
289 ps3vram_out_ring(priv, count);
290 ps3vram_out_ring(priv, (1 << 8) | 1);
291 ps3vram_out_ring(priv, 0);
292
293 ps3vram_notifier_reset(dev);
294 ps3vram_begin_ring(priv, DOWNLOAD_SUBCH,
295 NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1);
296 ps3vram_out_ring(priv, 0);
297 ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x100, 1);
298 ps3vram_out_ring(priv, 0);
299 ps3vram_fire_ring(dev);
300 if (ps3vram_notifier_wait(dev, 200) < 0) {
301 dev_warn(&dev->core, "%s: Notifier timeout\n", __func__);
302 return -1;
303 }
304
305 return 0;
306}
307
308static void ps3vram_cache_evict(struct ps3_system_bus_device *dev, int entry)
309{
310 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
311 struct ps3vram_cache *cache = &priv->cache;
312
313 if (!(cache->tags[entry].flags & CACHE_PAGE_DIRTY))
314 return;
315
316 dev_dbg(&dev->core, "Flushing %d: 0x%08x\n", entry,
317 cache->tags[entry].address);
318 if (ps3vram_upload(dev, CACHE_OFFSET + entry * cache->page_size,
319 cache->tags[entry].address, DMA_PAGE_SIZE,
320 cache->page_size / DMA_PAGE_SIZE) < 0) {
321 dev_err(&dev->core,
322 "Failed to upload from 0x%x to " "0x%x size 0x%x\n",
323 entry * cache->page_size, cache->tags[entry].address,
324 cache->page_size);
325 }
326 cache->tags[entry].flags &= ~CACHE_PAGE_DIRTY;
327}
328
329static void ps3vram_cache_load(struct ps3_system_bus_device *dev, int entry,
330 unsigned int address)
331{
332 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
333 struct ps3vram_cache *cache = &priv->cache;
334
335 dev_dbg(&dev->core, "Fetching %d: 0x%08x\n", entry, address);
336 if (ps3vram_download(dev, address,
337 CACHE_OFFSET + entry * cache->page_size,
338 DMA_PAGE_SIZE,
339 cache->page_size / DMA_PAGE_SIZE) < 0) {
340 dev_err(&dev->core,
341 "Failed to download from 0x%x to 0x%x size 0x%x\n",
342 address, entry * cache->page_size, cache->page_size);
343 }
344
345 cache->tags[entry].address = address;
346 cache->tags[entry].flags |= CACHE_PAGE_PRESENT;
347}
348
349
350static void ps3vram_cache_flush(struct ps3_system_bus_device *dev)
351{
352 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
353 struct ps3vram_cache *cache = &priv->cache;
354 int i;
355
356 dev_dbg(&dev->core, "FLUSH\n");
357 for (i = 0; i < cache->page_count; i++) {
358 ps3vram_cache_evict(dev, i);
359 cache->tags[i].flags = 0;
360 }
361}
362
363static unsigned int ps3vram_cache_match(struct ps3_system_bus_device *dev,
364 loff_t address)
365{
366 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
367 struct ps3vram_cache *cache = &priv->cache;
368 unsigned int base;
369 unsigned int offset;
370 int i;
371 static int counter;
372
373 offset = (unsigned int) (address & (cache->page_size - 1));
374 base = (unsigned int) (address - offset);
375
376 /* fully associative check */
377 for (i = 0; i < cache->page_count; i++) {
378 if ((cache->tags[i].flags & CACHE_PAGE_PRESENT) &&
379 cache->tags[i].address == base) {
380 cache->hit++;
381 dev_dbg(&dev->core, "Found entry %d: 0x%08x\n", i,
382 cache->tags[i].address);
383 return i;
384 }
385 }
386
387 /* choose a random entry */
388 i = (jiffies + (counter++)) % cache->page_count;
389 dev_dbg(&dev->core, "Using entry %d\n", i);
390
391 ps3vram_cache_evict(dev, i);
392 ps3vram_cache_load(dev, i, base);
393
394 cache->miss++;
395 return i;
396}
397
398static int ps3vram_cache_init(struct ps3_system_bus_device *dev)
399{
400 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
401
402 priv->cache.page_count = CACHE_PAGE_COUNT;
403 priv->cache.page_size = CACHE_PAGE_SIZE;
404 priv->cache.tags = kzalloc_objs(struct ps3vram_tag, CACHE_PAGE_COUNT);
405 if (!priv->cache.tags)
406 return -ENOMEM;
407
408 dev_info(&dev->core, "Created ram cache: %d entries, %d KiB each\n",
409 CACHE_PAGE_COUNT, CACHE_PAGE_SIZE / 1024);
410
411 return 0;
412}
413
414static void ps3vram_cache_cleanup(struct ps3_system_bus_device *dev)
415{
416 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
417
418 ps3vram_cache_flush(dev);
419 kfree(priv->cache.tags);
420}
421
422static blk_status_t ps3vram_read(struct ps3_system_bus_device *dev, loff_t from,
423 size_t len, size_t *retlen, u_char *buf)
424{
425 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
426 unsigned int cached, count;
427
428 dev_dbg(&dev->core, "%s: from=0x%08x len=0x%zx\n", __func__,
429 (unsigned int)from, len);
430
431 if (from >= priv->size)
432 return BLK_STS_IOERR;
433
434 if (len > priv->size - from)
435 len = priv->size - from;
436
437 /* Copy from vram to buf */
438 count = len;
439 while (count) {
440 unsigned int offset, avail;
441 unsigned int entry;
442
443 offset = (unsigned int) (from & (priv->cache.page_size - 1));
444 avail = priv->cache.page_size - offset;
445
446 entry = ps3vram_cache_match(dev, from);
447 cached = CACHE_OFFSET + entry * priv->cache.page_size + offset;
448
449 dev_dbg(&dev->core, "%s: from=%08x cached=%08x offset=%08x "
450 "avail=%08x count=%08x\n", __func__,
451 (unsigned int)from, cached, offset, avail, count);
452
453 if (avail > count)
454 avail = count;
455 memcpy(buf, priv->xdr_buf + cached, avail);
456
457 buf += avail;
458 count -= avail;
459 from += avail;
460 }
461
462 *retlen = len;
463 return 0;
464}
465
466static blk_status_t ps3vram_write(struct ps3_system_bus_device *dev, loff_t to,
467 size_t len, size_t *retlen, const u_char *buf)
468{
469 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
470 unsigned int cached, count;
471
472 if (to >= priv->size)
473 return BLK_STS_IOERR;
474
475 if (len > priv->size - to)
476 len = priv->size - to;
477
478 /* Copy from buf to vram */
479 count = len;
480 while (count) {
481 unsigned int offset, avail;
482 unsigned int entry;
483
484 offset = (unsigned int) (to & (priv->cache.page_size - 1));
485 avail = priv->cache.page_size - offset;
486
487 entry = ps3vram_cache_match(dev, to);
488 cached = CACHE_OFFSET + entry * priv->cache.page_size + offset;
489
490 dev_dbg(&dev->core, "%s: to=%08x cached=%08x offset=%08x "
491 "avail=%08x count=%08x\n", __func__, (unsigned int)to,
492 cached, offset, avail, count);
493
494 if (avail > count)
495 avail = count;
496 memcpy(priv->xdr_buf + cached, buf, avail);
497
498 priv->cache.tags[entry].flags |= CACHE_PAGE_DIRTY;
499
500 buf += avail;
501 count -= avail;
502 to += avail;
503 }
504
505 *retlen = len;
506 return 0;
507}
508
509static int ps3vram_proc_show(struct seq_file *m, void *v)
510{
511 struct ps3vram_priv *priv = m->private;
512
513 seq_printf(m, "hit:%u\nmiss:%u\n", priv->cache.hit, priv->cache.miss);
514 return 0;
515}
516
517static void ps3vram_proc_init(struct ps3_system_bus_device *dev)
518{
519 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
520 struct proc_dir_entry *pde;
521
522 pde = proc_create_single_data(DEVICE_NAME, 0444, NULL,
523 ps3vram_proc_show, priv);
524 if (!pde)
525 dev_warn(&dev->core, "failed to create /proc entry\n");
526}
527
528static struct bio *ps3vram_do_bio(struct ps3_system_bus_device *dev,
529 struct bio *bio)
530{
531 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
532 int write = bio_data_dir(bio) == WRITE;
533 const char *op = write ? "write" : "read";
534 loff_t offset = bio->bi_iter.bi_sector << 9;
535 blk_status_t error = 0;
536 struct bio_vec bvec;
537 struct bvec_iter iter;
538 struct bio *next;
539
540 bio_for_each_segment(bvec, bio, iter) {
541 /* PS3 is ppc64, so we don't handle highmem */
542 char *ptr = bvec_virt(&bvec);
543 size_t len = bvec.bv_len, retlen;
544
545 dev_dbg(&dev->core, " %s %zu bytes at offset %llu\n", op,
546 len, offset);
547 if (write)
548 error = ps3vram_write(dev, offset, len, &retlen, ptr);
549 else
550 error = ps3vram_read(dev, offset, len, &retlen, ptr);
551
552 if (error) {
553 dev_err(&dev->core, "%s failed\n", op);
554 goto out;
555 }
556
557 if (retlen != len) {
558 dev_err(&dev->core, "Short %s\n", op);
559 error = BLK_STS_IOERR;
560 goto out;
561 }
562
563 offset += len;
564 }
565
566 dev_dbg(&dev->core, "%s completed\n", op);
567
568out:
569 spin_lock_irq(&priv->lock);
570 bio_list_pop(&priv->list);
571 next = bio_list_peek(&priv->list);
572 spin_unlock_irq(&priv->lock);
573
574 bio->bi_status = error;
575 bio_endio(bio);
576 return next;
577}
578
579static void ps3vram_submit_bio(struct bio *bio)
580{
581 struct ps3_system_bus_device *dev = bio->bi_bdev->bd_disk->private_data;
582 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
583 int busy;
584
585 dev_dbg(&dev->core, "%s\n", __func__);
586
587 spin_lock_irq(&priv->lock);
588 busy = !bio_list_empty(&priv->list);
589 bio_list_add(&priv->list, bio);
590 spin_unlock_irq(&priv->lock);
591
592 if (busy)
593 return;
594
595 do {
596 bio = ps3vram_do_bio(dev, bio);
597 } while (bio);
598}
599
600static const struct block_device_operations ps3vram_fops = {
601 .owner = THIS_MODULE,
602 .submit_bio = ps3vram_submit_bio,
603};
604
605static int ps3vram_probe(struct ps3_system_bus_device *dev)
606{
607 struct ps3vram_priv *priv;
608 int error, status;
609 struct gendisk *gendisk;
610 u64 ddr_size, ddr_lpar, ctrl_lpar, info_lpar, reports_lpar,
611 reports_size, xdr_lpar;
612 char *rest;
613
614 priv = kzalloc_obj(*priv);
615 if (!priv) {
616 error = -ENOMEM;
617 goto fail;
618 }
619
620 spin_lock_init(&priv->lock);
621 bio_list_init(&priv->list);
622 ps3_system_bus_set_drvdata(dev, priv);
623
624 /* Allocate XDR buffer (1MiB aligned) */
625 priv->xdr_buf = (void *)__get_free_pages(GFP_KERNEL,
626 get_order(XDR_BUF_SIZE));
627 if (priv->xdr_buf == NULL) {
628 dev_err(&dev->core, "Could not allocate XDR buffer\n");
629 error = -ENOMEM;
630 goto fail_free_priv;
631 }
632
633 /* Put FIFO at begginning of XDR buffer */
634 priv->fifo_base = (u32 *) (priv->xdr_buf + FIFO_OFFSET);
635 priv->fifo_ptr = priv->fifo_base;
636
637 /* XXX: Need to open GPU, in case ps3fb or snd_ps3 aren't loaded */
638 if (ps3_open_hv_device(dev)) {
639 dev_err(&dev->core, "ps3_open_hv_device failed\n");
640 error = -EAGAIN;
641 goto out_free_xdr_buf;
642 }
643
644 /* Request memory */
645 status = -1;
646 ddr_size = ALIGN(memparse(size, &rest), 1024*1024);
647 if (!ddr_size) {
648 dev_err(&dev->core, "Specified size is too small\n");
649 error = -EINVAL;
650 goto out_close_gpu;
651 }
652
653 while (ddr_size > 0) {
654 status = lv1_gpu_memory_allocate(ddr_size, 0, 0, 0, 0,
655 &priv->memory_handle,
656 &ddr_lpar);
657 if (!status)
658 break;
659 ddr_size -= 1024*1024;
660 }
661 if (status) {
662 dev_err(&dev->core, "lv1_gpu_memory_allocate failed %d\n",
663 status);
664 error = -ENOMEM;
665 goto out_close_gpu;
666 }
667
668 /* Request context */
669 status = lv1_gpu_context_allocate(priv->memory_handle, 0,
670 &priv->context_handle, &ctrl_lpar,
671 &info_lpar, &reports_lpar,
672 &reports_size);
673 if (status) {
674 dev_err(&dev->core, "lv1_gpu_context_allocate failed %d\n",
675 status);
676 error = -ENOMEM;
677 goto out_free_memory;
678 }
679
680 /* Map XDR buffer to RSX */
681 xdr_lpar = ps3_mm_phys_to_lpar(__pa(priv->xdr_buf));
682 status = lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF,
683 xdr_lpar, XDR_BUF_SIZE,
684 CBE_IOPTE_PP_W | CBE_IOPTE_PP_R |
685 CBE_IOPTE_M);
686 if (status) {
687 dev_err(&dev->core, "lv1_gpu_context_iomap failed %d\n",
688 status);
689 error = -ENOMEM;
690 goto out_free_context;
691 }
692
693 priv->ctrl = ioremap(ctrl_lpar, 64 * 1024);
694 if (!priv->ctrl) {
695 dev_err(&dev->core, "ioremap CTRL failed\n");
696 error = -ENOMEM;
697 goto out_unmap_context;
698 }
699
700 priv->reports = ioremap(reports_lpar, reports_size);
701 if (!priv->reports) {
702 dev_err(&dev->core, "ioremap REPORTS failed\n");
703 error = -ENOMEM;
704 goto out_unmap_ctrl;
705 }
706
707 mutex_lock(&ps3_gpu_mutex);
708 ps3vram_init_ring(dev);
709 mutex_unlock(&ps3_gpu_mutex);
710
711 priv->size = ddr_size;
712
713 ps3vram_bind(dev);
714
715 mutex_lock(&ps3_gpu_mutex);
716 error = ps3vram_wait_ring(dev, 100);
717 mutex_unlock(&ps3_gpu_mutex);
718 if (error < 0) {
719 dev_err(&dev->core, "Failed to initialize channels\n");
720 error = -ETIMEDOUT;
721 goto out_unmap_reports;
722 }
723
724 error = ps3vram_cache_init(dev);
725 if (error < 0) {
726 goto out_unmap_reports;
727 }
728
729 ps3vram_proc_init(dev);
730
731 gendisk = blk_alloc_disk(NULL, NUMA_NO_NODE);
732 if (IS_ERR(gendisk)) {
733 dev_err(&dev->core, "blk_alloc_disk failed\n");
734 error = PTR_ERR(gendisk);
735 goto out_cache_cleanup;
736 }
737
738 priv->gendisk = gendisk;
739 gendisk->major = ps3vram_major;
740 gendisk->minors = 1;
741 gendisk->flags |= GENHD_FL_NO_PART;
742 gendisk->fops = &ps3vram_fops;
743 gendisk->private_data = dev;
744 strscpy(gendisk->disk_name, DEVICE_NAME, sizeof(gendisk->disk_name));
745 set_capacity(gendisk, priv->size >> 9);
746
747 dev_info(&dev->core, "%s: Using %llu MiB of GPU memory\n",
748 gendisk->disk_name, get_capacity(gendisk) >> 11);
749
750 error = device_add_disk(&dev->core, gendisk, NULL);
751 if (error)
752 goto out_cleanup_disk;
753
754 return 0;
755
756out_cleanup_disk:
757 put_disk(gendisk);
758out_cache_cleanup:
759 remove_proc_entry(DEVICE_NAME, NULL);
760 ps3vram_cache_cleanup(dev);
761out_unmap_reports:
762 iounmap(priv->reports);
763out_unmap_ctrl:
764 iounmap(priv->ctrl);
765out_unmap_context:
766 lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF, xdr_lpar,
767 XDR_BUF_SIZE, CBE_IOPTE_M);
768out_free_context:
769 lv1_gpu_context_free(priv->context_handle);
770out_free_memory:
771 lv1_gpu_memory_free(priv->memory_handle);
772out_close_gpu:
773 ps3_close_hv_device(dev);
774out_free_xdr_buf:
775 free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE));
776fail_free_priv:
777 kfree(priv);
778 ps3_system_bus_set_drvdata(dev, NULL);
779fail:
780 return error;
781}
782
783static void ps3vram_remove(struct ps3_system_bus_device *dev)
784{
785 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
786
787 del_gendisk(priv->gendisk);
788 put_disk(priv->gendisk);
789 remove_proc_entry(DEVICE_NAME, NULL);
790 ps3vram_cache_cleanup(dev);
791 iounmap(priv->reports);
792 iounmap(priv->ctrl);
793 lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF,
794 ps3_mm_phys_to_lpar(__pa(priv->xdr_buf)),
795 XDR_BUF_SIZE, CBE_IOPTE_M);
796 lv1_gpu_context_free(priv->context_handle);
797 lv1_gpu_memory_free(priv->memory_handle);
798 ps3_close_hv_device(dev);
799 free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE));
800 kfree(priv);
801 ps3_system_bus_set_drvdata(dev, NULL);
802}
803
804static struct ps3_system_bus_driver ps3vram = {
805 .match_id = PS3_MATCH_ID_GPU,
806 .match_sub_id = PS3_MATCH_SUB_ID_GPU_RAMDISK,
807 .core.name = DEVICE_NAME,
808 .core.owner = THIS_MODULE,
809 .probe = ps3vram_probe,
810 .remove = ps3vram_remove,
811 .shutdown = ps3vram_remove,
812};
813
814
815static int __init ps3vram_init(void)
816{
817 int error;
818
819 if (!firmware_has_feature(FW_FEATURE_PS3_LV1))
820 return -ENODEV;
821
822 error = register_blkdev(0, DEVICE_NAME);
823 if (error <= 0) {
824 pr_err("%s: register_blkdev failed %d\n", DEVICE_NAME, error);
825 return error;
826 }
827 ps3vram_major = error;
828
829 pr_info("%s: registered block device major %d\n", DEVICE_NAME,
830 ps3vram_major);
831
832 error = ps3_system_bus_driver_register(&ps3vram);
833 if (error)
834 unregister_blkdev(ps3vram_major, DEVICE_NAME);
835
836 return error;
837}
838
839static void __exit ps3vram_exit(void)
840{
841 ps3_system_bus_driver_unregister(&ps3vram);
842 unregister_blkdev(ps3vram_major, DEVICE_NAME);
843}
844
845module_init(ps3vram_init);
846module_exit(ps3vram_exit);
847
848MODULE_LICENSE("GPL");
849MODULE_DESCRIPTION("PS3 Video RAM Storage Driver");
850MODULE_AUTHOR("Sony Corporation");
851MODULE_ALIAS(PS3_MODULE_ALIAS_GPU_RAMDISK);