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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 *
4 * Bluetooth support for Intel PCIe devices
5 *
6 * Copyright (C) 2024 Intel Corporation
7 */
8
9/* Control and Status Register(BTINTEL_PCIE_CSR) */
10#define BTINTEL_PCIE_CSR_BASE (0x000)
11#define BTINTEL_PCIE_CSR_FUNC_CTRL_REG (BTINTEL_PCIE_CSR_BASE + 0x024)
12#define BTINTEL_PCIE_CSR_HW_REV_REG (BTINTEL_PCIE_CSR_BASE + 0x028)
13#define BTINTEL_PCIE_CSR_RF_ID_REG (BTINTEL_PCIE_CSR_BASE + 0x09C)
14#define BTINTEL_PCIE_CSR_BOOT_STAGE_REG (BTINTEL_PCIE_CSR_BASE + 0x108)
15#define BTINTEL_PCIE_CSR_IPC_CONTROL_REG (BTINTEL_PCIE_CSR_BASE + 0x10C)
16#define BTINTEL_PCIE_CSR_IPC_STATUS_REG (BTINTEL_PCIE_CSR_BASE + 0x110)
17#define BTINTEL_PCIE_CSR_IPC_SLEEP_CTL_REG (BTINTEL_PCIE_CSR_BASE + 0x114)
18#define BTINTEL_PCIE_CSR_CI_ADDR_LSB_REG (BTINTEL_PCIE_CSR_BASE + 0x118)
19#define BTINTEL_PCIE_CSR_CI_ADDR_MSB_REG (BTINTEL_PCIE_CSR_BASE + 0x11C)
20#define BTINTEL_PCIE_CSR_IMG_RESPONSE_REG (BTINTEL_PCIE_CSR_BASE + 0x12C)
21#define BTINTEL_PCIE_CSR_MBOX_1_REG (BTINTEL_PCIE_CSR_BASE + 0x170)
22#define BTINTEL_PCIE_CSR_MBOX_2_REG (BTINTEL_PCIE_CSR_BASE + 0x174)
23#define BTINTEL_PCIE_CSR_MBOX_3_REG (BTINTEL_PCIE_CSR_BASE + 0x178)
24#define BTINTEL_PCIE_CSR_MBOX_4_REG (BTINTEL_PCIE_CSR_BASE + 0x17C)
25#define BTINTEL_PCIE_CSR_MBOX_STATUS_REG (BTINTEL_PCIE_CSR_BASE + 0x180)
26#define BTINTEL_PCIE_PRPH_DEV_ADDR_REG (BTINTEL_PCIE_CSR_BASE + 0x440)
27#define BTINTEL_PCIE_PRPH_DEV_RD_REG (BTINTEL_PCIE_CSR_BASE + 0x458)
28#define BTINTEL_PCIE_CSR_HBUS_TARG_WRPTR (BTINTEL_PCIE_CSR_BASE + 0x460)
29
30/* BTINTEL_PCIE_CSR Function Control Register */
31#define BTINTEL_PCIE_CSR_FUNC_CTRL_FUNC_ENA (BIT(0))
32#define BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_INIT (BIT(6))
33#define BTINTEL_PCIE_CSR_FUNC_CTRL_FUNC_INIT (BIT(7))
34#define BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_ACCESS_STS (BIT(20))
35
36#define BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_ACCESS_REQ (BIT(21))
37
38#define BTINTEL_PCIE_CSR_FUNC_CTRL_BUS_MASTER_STS (BIT(28))
39#define BTINTEL_PCIE_CSR_FUNC_CTRL_BUS_MASTER_DISCON (BIT(29))
40#define BTINTEL_PCIE_CSR_FUNC_CTRL_SW_RESET (BIT(31))
41
42/* Value for BTINTEL_PCIE_CSR_BOOT_STAGE register */
43#define BTINTEL_PCIE_CSR_BOOT_STAGE_ROM (BIT(0))
44#define BTINTEL_PCIE_CSR_BOOT_STAGE_IML (BIT(1))
45#define BTINTEL_PCIE_CSR_BOOT_STAGE_OPFW (BIT(2))
46#define BTINTEL_PCIE_CSR_BOOT_STAGE_ROM_LOCKDOWN (BIT(10))
47#define BTINTEL_PCIE_CSR_BOOT_STAGE_IML_LOCKDOWN (BIT(11))
48#define BTINTEL_PCIE_CSR_BOOT_STAGE_DEVICE_WARNING (BIT(12))
49#define BTINTEL_PCIE_CSR_BOOT_STAGE_ABORT_HANDLER (BIT(13))
50#define BTINTEL_PCIE_CSR_BOOT_STAGE_DEVICE_HALTED (BIT(14))
51#define BTINTEL_PCIE_CSR_BOOT_STAGE_MAC_ACCESS_ON (BIT(16))
52#define BTINTEL_PCIE_CSR_BOOT_STAGE_ALIVE (BIT(23))
53#define BTINTEL_PCIE_CSR_BOOT_STAGE_D3_STATE_READY (BIT(24))
54
55/* Registers for MSI-X */
56#define BTINTEL_PCIE_CSR_MSIX_BASE (0x2000)
57#define BTINTEL_PCIE_CSR_MSIX_FH_INT_CAUSES (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0800)
58#define BTINTEL_PCIE_CSR_MSIX_FH_INT_MASK (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0804)
59#define BTINTEL_PCIE_CSR_MSIX_HW_INT_CAUSES (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0808)
60#define BTINTEL_PCIE_CSR_MSIX_HW_INT_MASK (BTINTEL_PCIE_CSR_MSIX_BASE + 0x080C)
61#define BTINTEL_PCIE_CSR_MSIX_AUTOMASK_ST (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0810)
62#define BTINTEL_PCIE_CSR_MSIX_AUTOMASK_EN (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0814)
63#define BTINTEL_PCIE_CSR_MSIX_IVAR_BASE (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0880)
64#define BTINTEL_PCIE_CSR_MSIX_IVAR(cause) (BTINTEL_PCIE_CSR_MSIX_IVAR_BASE + (cause))
65
66/* IOSF Debug Register */
67#define BTINTEL_PCIE_DBGC_BASE_ADDR (0xf3800300)
68#define BTINTEL_PCIE_DBGC_CUR_DBGBUFF_STATUS (BTINTEL_PCIE_DBGC_BASE_ADDR + 0x1C)
69#define BTINTEL_PCIE_DBGC_DBGBUFF_WRAP_ARND (BTINTEL_PCIE_DBGC_BASE_ADDR + 0x2C)
70
71#define BTINTEL_PCIE_DBGC_BASE_ADDR_SCP (0xf0d5d500)
72#define BTINTEL_PCIE_DBGC_CUR_DBGBUFF_STATUS_SCP (BTINTEL_PCIE_DBGC_BASE_ADDR_SCP + 0x1C)
73#define BTINTEL_PCIE_DBGC_DBGBUFF_WRAP_ARND_SCP (BTINTEL_PCIE_DBGC_BASE_ADDR_SCP + 0x2C)
74
75#define BTINTEL_PCIE_DBG_IDX_BIT_MASK 0x0F
76#define BTINTEL_PCIE_DBGC_DBG_BUF_IDX(data) (((data) >> 24) & BTINTEL_PCIE_DBG_IDX_BIT_MASK)
77#define BTINTEL_PCIE_DBG_OFFSET_BIT_MASK 0xFFFFFF
78
79/* The DRAM buffer count, each buffer size, and
80 * fragment buffer size
81 */
82#define BTINTEL_PCIE_DBGC_BUFFER_COUNT 16
83#define BTINTEL_PCIE_DBGC_BUFFER_SIZE (256 * 1024) /* 256 KB */
84
85#define BTINTEL_PCIE_DBGC_FRAG_VERSION 1
86#define BTINTEL_PCIE_DBGC_FRAG_BUFFER_COUNT BTINTEL_PCIE_DBGC_BUFFER_COUNT
87
88/* Magic number(4), version(4), size of payload length(4) */
89#define BTINTEL_PCIE_DBGC_FRAG_HEADER_SIZE 12
90
91/* Num of alloc Dbg buff (4) + (LSB(4), MSB(4), Size(4)) for each buffer */
92#define BTINTEL_PCIE_DBGC_FRAG_PAYLOAD_SIZE 196
93
94/* Causes for the FH register interrupts */
95enum msix_fh_int_causes {
96 BTINTEL_PCIE_MSIX_FH_INT_CAUSES_0 = BIT(0), /* cause 0 */
97 BTINTEL_PCIE_MSIX_FH_INT_CAUSES_1 = BIT(1), /* cause 1 */
98};
99
100/* Causes for the HW register interrupts */
101enum msix_hw_int_causes {
102 BTINTEL_PCIE_MSIX_HW_INT_CAUSES_GP0 = BIT(0), /* cause 32 */
103 BTINTEL_PCIE_MSIX_HW_INT_CAUSES_GP1 = BIT(1), /* cause 33 */
104 BTINTEL_PCIE_MSIX_HW_INT_CAUSES_HWEXP = BIT(3), /* cause 35 */
105 BTINTEL_PCIE_MSIX_HW_INT_CAUSES_FWTRIG = BIT(5), /* cause 37 */
106};
107
108/* PCIe device states
109 * Host-Device interface is active
110 * Host-Device interface is inactive(as reflected by IPC_SLEEP_CONTROL_CSR_AD)
111 * Host-Device interface is inactive(as reflected by IPC_SLEEP_CONTROL_CSR_AD)
112 */
113enum {
114 BTINTEL_PCIE_STATE_D0 = 0,
115 BTINTEL_PCIE_STATE_D3_HOT = 2,
116 BTINTEL_PCIE_STATE_D3_COLD = 3,
117};
118
119enum {
120 BTINTEL_PCIE_CORE_HALTED,
121 BTINTEL_PCIE_COREDUMP_INPROGRESS,
122 BTINTEL_PCIE_FWTRIGGER_DUMP_INPROGRESS,
123 BTINTEL_PCIE_RECOVERY_IN_PROGRESS,
124 BTINTEL_PCIE_SETUP_DONE
125};
126
127enum btintel_pcie_tlv_type {
128 BTINTEL_CNVI_BT,
129 BTINTEL_WRITE_PTR,
130 BTINTEL_WRAP_CTR,
131 BTINTEL_TRIGGER_REASON,
132 BTINTEL_FW_SHA,
133 BTINTEL_CNVR_TOP,
134 BTINTEL_CNVI_TOP,
135 BTINTEL_DUMP_TIME,
136 BTINTEL_FW_BUILD,
137 BTINTEL_VENDOR,
138 BTINTEL_DRIVER,
139 BTINTEL_EVENT_TYPE,
140 BTINTEL_EVENT_ID
141};
142
143/* causes for the MBOX interrupts */
144enum msix_mbox_int_causes {
145 BTINTEL_PCIE_CSR_MBOX_STATUS_MBOX1 = BIT(0), /* cause MBOX1 */
146 BTINTEL_PCIE_CSR_MBOX_STATUS_MBOX2 = BIT(1), /* cause MBOX2 */
147 BTINTEL_PCIE_CSR_MBOX_STATUS_MBOX3 = BIT(2), /* cause MBOX3 */
148 BTINTEL_PCIE_CSR_MBOX_STATUS_MBOX4 = BIT(3), /* cause MBOX4 */
149};
150
151enum btintel_pcie_reset_type {
152 BTINTEL_PCIE_IOSF_PRR_FLR = 0,
153 BTINTEL_PCIE_IOSF_PRR_PLDR = 1,
154};
155
156#define BTINTEL_PCIE_MSIX_NON_AUTO_CLEAR_CAUSE BIT(7)
157
158/* Minimum and Maximum number of MSI-X Vector
159 * Intel Bluetooth PCIe support only 1 vector
160 */
161#define BTINTEL_PCIE_MSIX_VEC_MAX 1
162#define BTINTEL_PCIE_MSIX_VEC_MIN 1
163
164/* Default poll time for MAC access during init */
165#define BTINTEL_DEFAULT_MAC_ACCESS_TIMEOUT_US 200000
166
167/* Default interrupt timeout in msec */
168#define BTINTEL_DEFAULT_INTR_TIMEOUT_MS 3000
169
170#define BTINTEL_PCIE_DX_TRANSITION_MAX_RETRIES 3
171
172/* The number of descriptors in TX queues */
173#define BTINTEL_PCIE_TX_DESCS_COUNT 32
174
175/* The number of descriptors in RX queues */
176#define BTINTEL_PCIE_RX_DESCS_COUNT 64
177
178/* Number of Queue for TX and RX
179 * It indicates the index of the IA(Index Array)
180 */
181enum {
182 BTINTEL_PCIE_TXQ_NUM = 0,
183 BTINTEL_PCIE_RXQ_NUM = 1,
184 BTINTEL_PCIE_NUM_QUEUES = 2,
185};
186
187/* The size of DMA buffer for TX and RX in bytes */
188#define BTINTEL_PCIE_BUFFER_SIZE 4096
189
190#define BTINTEL_PCIE_TX_WAIT_TIMEOUT_MS 500
191
192/* Doorbell vector for TFD */
193#define BTINTEL_PCIE_TX_DB_VEC 0
194
195/* Doorbell vector for FRBD */
196#define BTINTEL_PCIE_RX_DB_VEC 513
197
198/* RBD buffer size mapping */
199#define BTINTEL_PCIE_RBD_SIZE_4K 0x04
200
201/*
202 * Struct for Context Information (v2)
203 *
204 * All members are write-only for host and read-only for device.
205 *
206 * @version: Version of context information
207 * @size: Size of context information
208 * @config: Config with which host wants peripheral to execute
209 * Subset of capability register published by device
210 * @addr_tr_hia: Address of TR Head Index Array
211 * @addr_tr_tia: Address of TR Tail Index Array
212 * @addr_cr_hia: Address of CR Head Index Array
213 * @addr_cr_tia: Address of CR Tail Index Array
214 * @num_tr_ia: Number of entries in TR Index Arrays
215 * @num_cr_ia: Number of entries in CR Index Arrays
216 * @rbd_siz: RBD Size { 0x4=4K }
217 * @addr_tfdq: Address of TFD Queue(tx)
218 * @addr_urbdq0: Address of URBD Queue(tx)
219 * @num_tfdq: Number of TFD in TFD Queue(tx)
220 * @num_urbdq0: Number of URBD in URBD Queue(tx)
221 * @tfdq_db_vec: Queue number of TFD
222 * @urbdq0_db_vec: Queue number of URBD
223 * @addr_frbdq: Address of FRBD Queue(rx)
224 * @addr_urbdq1: Address of URBD Queue(rx)
225 * @num_frbdq: Number of FRBD in FRBD Queue(rx)
226 * @frbdq_db_vec: Queue number of FRBD
227 * @num_urbdq1: Number of URBD in URBD Queue(rx)
228 * @urbdq_db_vec: Queue number of URBDQ1
229 * @tr_msi_vec: Transfer Ring MSI-X Vector
230 * @cr_msi_vec: Completion Ring MSI-X Vector
231 * @dbgc_addr: DBGC first fragment address
232 * @dbgc_size: DBGC buffer size
233 * @early_enable: Enarly debug enable
234 * @dbg_output_mode: Debug output mode
235 * Bit[4] DBGC O/P { 0=SRAM, 1=DRAM(not relevant for NPK) }
236 * Bit[5] DBGC I/P { 0=BDBG, 1=DBGI }
237 * Bits[6:7] DBGI O/P(relevant if bit[5] = 1)
238 * 0=BT DBGC, 1=WiFi DBGC, 2=NPK }
239 * @dbg_preset: Debug preset
240 * @ext_addr: Address of context information extension
241 * @ext_size: Size of context information part
242 *
243 * Total 38 DWords
244 */
245struct ctx_info {
246 u16 version;
247 u16 size;
248 u32 config;
249 u32 reserved_dw02;
250 u32 reserved_dw03;
251 u64 addr_tr_hia;
252 u64 addr_tr_tia;
253 u64 addr_cr_hia;
254 u64 addr_cr_tia;
255 u16 num_tr_ia;
256 u16 num_cr_ia;
257 u32 rbd_size:4,
258 reserved_dw13:28;
259 u64 addr_tfdq;
260 u64 addr_urbdq0;
261 u16 num_tfdq;
262 u16 num_urbdq0;
263 u16 tfdq_db_vec;
264 u16 urbdq0_db_vec;
265 u64 addr_frbdq;
266 u64 addr_urbdq1;
267 u16 num_frbdq;
268 u16 frbdq_db_vec;
269 u16 num_urbdq1;
270 u16 urbdq_db_vec;
271 u16 tr_msi_vec;
272 u16 cr_msi_vec;
273 u32 reserved_dw27;
274 u64 dbgc_addr;
275 u32 dbgc_size;
276 u32 early_enable:1,
277 reserved_dw31:3,
278 dbg_output_mode:4,
279 dbg_preset:8,
280 reserved2_dw31:16;
281 u64 ext_addr;
282 u32 ext_size;
283 u32 test_param;
284 u32 reserved_dw36;
285 u32 reserved_dw37;
286} __packed;
287
288/* Transfer Descriptor for TX
289 * @type: Not in use. Set to 0x0
290 * @size: Size of data in the buffer
291 * @addr: DMA Address of buffer
292 */
293struct tfd {
294 u8 type;
295 u16 size;
296 u8 reserved;
297 u64 addr;
298 u32 reserved1;
299} __packed;
300
301/* URB Descriptor for TX
302 * @tfd_index: Index of TFD in TFDQ + 1
303 * @num_txq: Queue index of TFD Queue
304 * @cmpl_count: Completion count. Always 0x01
305 * @immediate_cmpl: Immediate completion flag: Always 0x01
306 */
307struct urbd0 {
308 u32 tfd_index:16,
309 num_txq:8,
310 cmpl_count:4,
311 reserved:3,
312 immediate_cmpl:1;
313} __packed;
314
315/* FRB Descriptor for RX
316 * @tag: RX buffer tag (index of RX buffer queue)
317 * @addr: Address of buffer
318 */
319struct frbd {
320 u32 tag:16,
321 reserved:16;
322 u32 reserved2;
323 u64 addr;
324} __packed;
325
326/* URB Descriptor for RX
327 * @frbd_tag: Tag from FRBD
328 * @status: Status
329 */
330struct urbd1 {
331 u32 frbd_tag:16,
332 status:1,
333 reserved:14,
334 fixed:1;
335} __packed;
336
337/* RFH header in RX packet
338 * @packet_len: Length of the data in the buffer
339 * @rxq: RX Queue number
340 * @cmd_id: Command ID. Not in Use
341 */
342struct rfh_hdr {
343 u64 packet_len:16,
344 rxq:6,
345 reserved:10,
346 cmd_id:16,
347 reserved1:16;
348} __packed;
349
350/* Internal data buffer
351 * @data: pointer to the data buffer
352 * @p_addr: physical address of data buffer
353 */
354struct data_buf {
355 u8 *data;
356 dma_addr_t data_p_addr;
357};
358
359/* Index Array */
360struct ia {
361 dma_addr_t tr_hia_p_addr;
362 u16 *tr_hia;
363 dma_addr_t tr_tia_p_addr;
364 u16 *tr_tia;
365 dma_addr_t cr_hia_p_addr;
366 u16 *cr_hia;
367 dma_addr_t cr_tia_p_addr;
368 u16 *cr_tia;
369};
370
371/* Structure for TX Queue
372 * @count: Number of descriptors
373 * @tfds: Array of TFD
374 * @urbd0s: Array of URBD0
375 * @buf: Array of data_buf structure
376 */
377struct txq {
378 u16 count;
379
380 dma_addr_t tfds_p_addr;
381 struct tfd *tfds;
382
383 dma_addr_t urbd0s_p_addr;
384 struct urbd0 *urbd0s;
385
386 dma_addr_t buf_p_addr;
387 void *buf_v_addr;
388 struct data_buf *bufs;
389};
390
391/* Structure for RX Queue
392 * @count: Number of descriptors
393 * @frbds: Array of FRBD
394 * @urbd1s: Array of URBD1
395 * @buf: Array of data_buf structure
396 */
397struct rxq {
398 u16 count;
399
400 dma_addr_t frbds_p_addr;
401 struct frbd *frbds;
402
403 dma_addr_t urbd1s_p_addr;
404 struct urbd1 *urbd1s;
405
406 dma_addr_t buf_p_addr;
407 void *buf_v_addr;
408 struct data_buf *bufs;
409};
410
411/* Structure for DRAM Buffer
412 * @count: Number of descriptors
413 * @buf: Array of data_buf structure
414 */
415struct btintel_pcie_dbgc {
416 u16 count;
417
418 void *frag_v_addr;
419 dma_addr_t frag_p_addr;
420 u16 frag_size;
421
422 dma_addr_t buf_p_addr;
423 void *buf_v_addr;
424 struct data_buf *bufs;
425};
426
427struct btintel_pcie_dump_header {
428 const char *driver_name;
429 u32 cnvi_top;
430 u32 cnvr_top;
431 u16 fw_timestamp;
432 u8 fw_build_type;
433 u32 fw_build_num;
434 u32 fw_git_sha1;
435 u32 cnvi_bt;
436 u32 write_ptr;
437 u32 wrap_ctr;
438 u16 trigger_reason;
439 int state;
440 u8 event_type;
441 u16 event_id;
442};
443
444/* struct btintel_pcie_data
445 * @pdev: pci device
446 * @hdev: hdev device
447 * @flags: driver state
448 * @irq_lock: spinlock for MSI-X
449 * @hci_rx_lock: spinlock for HCI RX flow
450 * @base_addr: pci base address (from BAR)
451 * @msix_entries: array of MSI-X entries
452 * @msix_enabled: true if MSI-X is enabled;
453 * @alloc_vecs: number of interrupt vectors allocated
454 * @def_irq: default irq for all causes
455 * @fh_init_mask: initial unmasked rxq causes
456 * @hw_init_mask: initial unmaksed hw causes
457 * @boot_stage_cache: cached value of boot stage register
458 * @img_resp_cache: cached value of image response register
459 * @cnvi: CNVi register value
460 * @cnvr: CNVr register value
461 * @gp0_received: condition for gp0 interrupt
462 * @gp0_wait_q: wait_q for gp0 interrupt
463 * @tx_wait_done: condition for tx interrupt
464 * @tx_wait_q: wait_q for tx interrupt
465 * @workqueue: workqueue for RX work
466 * @rx_skb_q: SKB queue for RX packet
467 * @rx_work: RX work struct to process the RX packet in @rx_skb_q
468 * @dump_workqueue: dedicated ordered workqueue serializing the coredump,
469 * hardware exception, and firmware-trigger dump workers
470 * @coredump_work: work struct for DRAM trace coredump collection
471 * @hwexp_work: work struct for hardware exception event read
472 * @fwtrigger_work: work struct for firmware-triggered diagnostic event read
473 * @dma_pool: DMA pool for descriptors, index array and ci
474 * @dma_p_addr: DMA address for pool
475 * @dma_v_addr: address of pool
476 * @ci_p_addr: DMA address for CI struct
477 * @ci: CI struct
478 * @ia: Index Array struct
479 * @txq: TX Queue struct
480 * @rxq: RX Queue struct
481 * @alive_intr_ctxt: Alive interrupt context
482 * @pm_sx_event: PM event on which system got suspended
483 */
484struct btintel_pcie_data {
485 struct pci_dev *pdev;
486 struct hci_dev *hdev;
487
488 unsigned long flags;
489 /* lock used in MSI-X interrupt */
490 spinlock_t irq_lock;
491 /* lock to serialize rx events */
492 spinlock_t hci_rx_lock;
493
494 void __iomem *base_addr;
495
496 struct msix_entry msix_entries[BTINTEL_PCIE_MSIX_VEC_MAX];
497 bool msix_enabled;
498 u32 alloc_vecs;
499 u32 def_irq;
500
501 u32 fh_init_mask;
502 u32 hw_init_mask;
503
504 u32 boot_stage_cache;
505 u32 img_resp_cache;
506
507 u32 cnvi;
508 u32 cnvr;
509
510 bool gp0_received;
511 wait_queue_head_t gp0_wait_q;
512
513 bool tx_wait_done;
514 wait_queue_head_t tx_wait_q;
515
516 struct workqueue_struct *workqueue;
517 struct sk_buff_head rx_skb_q;
518 struct work_struct rx_work;
519 struct work_struct reset_work;
520
521 struct workqueue_struct *dump_workqueue;
522 struct work_struct coredump_work;
523 struct work_struct hwexp_work;
524 struct work_struct fwtrigger_work;
525
526 struct dma_pool *dma_pool;
527 dma_addr_t dma_p_addr;
528 void *dma_v_addr;
529
530 dma_addr_t ci_p_addr;
531 struct ctx_info *ci;
532 struct ia ia;
533 struct txq txq;
534 struct rxq rxq;
535 u32 alive_intr_ctxt;
536 enum btintel_pcie_reset_type reset_type;
537 struct btintel_pcie_dbgc dbgc;
538 struct btintel_pcie_dump_header dmp_hdr;
539 u8 pm_sx_event;
540 u32 debug_evt_addr;
541 u32 debug_evt_size;
542};
543
544static inline u32 btintel_pcie_rd_reg32(struct btintel_pcie_data *data,
545 u32 offset)
546{
547 return ioread32(data->base_addr + offset);
548}
549
550static inline void btintel_pcie_wr_reg8(struct btintel_pcie_data *data,
551 u32 offset, u8 val)
552{
553 iowrite8(val, data->base_addr + offset);
554}
555
556static inline void btintel_pcie_wr_reg32(struct btintel_pcie_data *data,
557 u32 offset, u32 val)
558{
559 iowrite32(val, data->base_addr + offset);
560}
561
562static inline void btintel_pcie_set_reg_bits(struct btintel_pcie_data *data,
563 u32 offset, u32 bits)
564{
565 u32 r;
566
567 r = ioread32(data->base_addr + offset);
568 r |= bits;
569 iowrite32(r, data->base_addr + offset);
570}
571
572static inline void btintel_pcie_clr_reg_bits(struct btintel_pcie_data *data,
573 u32 offset, u32 bits)
574{
575 u32 r;
576
577 r = ioread32(data->base_addr + offset);
578 r &= ~bits;
579 iowrite32(r, data->base_addr + offset);
580}
581
582static inline u32 btintel_pcie_rd_dev_mem(struct btintel_pcie_data *data,
583 u32 addr)
584{
585 btintel_pcie_wr_reg32(data, BTINTEL_PCIE_PRPH_DEV_ADDR_REG, addr);
586 return btintel_pcie_rd_reg32(data, BTINTEL_PCIE_PRPH_DEV_RD_REG);
587}
588