linux - drivers/bus/ti-sysc.c

3351 lines · 83.9 KiB

1	// SPDX-License-Identifier: GPL-2.0
2	/*
3	* ti-sysc.c - Texas Instruments sysc interconnect target driver
4	*
5	* TI SoCs have an interconnect target wrapper IP for many devices. The wrapper
6	* IP manages clock gating, resets, and PM capabilities for the connected devices.
7	*
8	* Copyright (C) 2017-2024 Texas Instruments Incorporated - https://www.ti.com/
9	*
10	* Many features are based on the earlier omap_hwmod arch code with thanks to all
11	* the people who developed and debugged the code over the years:
12	*
13	* Copyright (C) 2009-2011 Nokia Corporation
14	* Copyright (C) 2011-2021 Texas Instruments Incorporated - https://www.ti.com/
15	*/
16
17	#include <linux/io.h>
18	#include <linux/clk.h>
19	#include <linux/clkdev.h>
20	#include <linux/cpu_pm.h>
21	#include <linux/delay.h>
22	#include <linux/list.h>
23	#include <linux/module.h>
24	#include <linux/platform_device.h>
25	#include <linux/pm_domain.h>
26	#include <linux/pm_runtime.h>
27	#include <linux/reset.h>
28	#include <linux/of_address.h>
29	#include <linux/of_platform.h>
30	#include <linux/slab.h>
31	#include <linux/sys_soc.h>
32	#include <linux/timekeeping.h>
33	#include <linux/iopoll.h>
34
35	#include <linux/platform_data/ti-sysc.h>
36
37	#include <dt-bindings/bus/ti-sysc.h>
38
39	#define DIS_ISP BIT(2)
40	#define DIS_IVA BIT(1)
41	#define DIS_SGX BIT(0)
42
43	#define SOC_FLAG(match, flag) { .machine = match, .data = (void *)(flag), }
44
45	#define MAX_MODULE_SOFTRESET_WAIT 10000
46
47	enum sysc_soc {
48	SOC_UNKNOWN,
49	SOC_2420,
50	SOC_2430,
51	SOC_AM33,
52	SOC_3430,
53	SOC_AM35,
54	SOC_3630,
55	SOC_4430,
56	SOC_4460,
57	SOC_4470,
58	SOC_5430,
59	SOC_AM3,
60	SOC_AM4,
61	SOC_DRA7,
62	};
63
64	struct sysc_address {
65	unsigned long base;
66	struct list_head node;
67	};
68
69	struct sysc_module {
70	struct sysc *ddata;
71	struct list_head node;
72	};
73
74	struct sysc_soc_info {
75	unsigned long general_purpose:1;
76	enum sysc_soc soc;
77	struct mutex list_lock; /* disabled and restored modules list lock */
78	struct list_head disabled_modules;
79	struct list_head restored_modules;
80	struct notifier_block nb;
81	};
82
83	enum sysc_clocks {
84	SYSC_FCK,
85	SYSC_ICK,
86	SYSC_OPTFCK0,
87	SYSC_OPTFCK1,
88	SYSC_OPTFCK2,
89	SYSC_OPTFCK3,
90	SYSC_OPTFCK4,
91	SYSC_OPTFCK5,
92	SYSC_OPTFCK6,
93	SYSC_OPTFCK7,
94	SYSC_MAX_CLOCKS,
95	};
96
97	static struct sysc_soc_info *sysc_soc;
98	static const char * const reg_names[] = { "rev", "sysc", "syss", };
99	static const char * const clock_names[SYSC_MAX_CLOCKS] = {
100	"fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4",
101	"opt5", "opt6", "opt7",
102	};
103
104	#define SYSC_IDLEMODE_MASK 3
105	#define SYSC_CLOCKACTIVITY_MASK 3
106
107	/**
108	* struct sysc - TI sysc interconnect target module registers and capabilities
109	* @dev: struct device pointer
110	* @module_pa: physical address of the interconnect target module
111	* @module_size: size of the interconnect target module
112	* @module_va: virtual address of the interconnect target module
113	* @offsets: register offsets from module base
114	* @mdata: ti-sysc to hwmod translation data for a module
115	* @clocks: clocks used by the interconnect target module
116	* @clock_roles: clock role names for the found clocks
117	* @nr_clocks: number of clocks used by the interconnect target module
118	* @rsts: resets used by the interconnect target module
119	* @legacy_mode: configured for legacy mode if set
120	* @cap: interconnect target module capabilities
121	* @cfg: interconnect target module configuration
122	* @cookie: data used by legacy platform callbacks
123	* @name: name if available
124	* @revision: interconnect target module revision
125	* @sysconfig: saved sysconfig register value
126	* @reserved: target module is reserved and already in use
127	* @enabled: sysc runtime enabled status
128	* @needs_resume: runtime resume needed on resume from suspend
129	* @child_needs_resume: runtime resume needed for child on resume from suspend
130	* @idle_work: work structure used to perform delayed idle on a module
131	* @pre_reset_quirk: module specific pre-reset quirk
132	* @post_reset_quirk: module specific post-reset quirk
133	* @reset_done_quirk: module specific reset done quirk
134	* @module_enable_quirk: module specific enable quirk
135	* @module_disable_quirk: module specific disable quirk
136	* @module_unlock_quirk: module specific sysconfig unlock quirk
137	* @module_lock_quirk: module specific sysconfig lock quirk
138	*/
139	struct sysc {
140	struct device *dev;
141	u64 module_pa;
142	u32 module_size;
143	void __iomem *module_va;
144	int offsets[SYSC_MAX_REGS];
145	struct ti_sysc_module_data *mdata;
146	struct clk **clocks;
147	const char **clock_roles;
148	int nr_clocks;
149	struct reset_control *rsts;
150	const char *legacy_mode;
151	const struct sysc_capabilities *cap;
152	struct sysc_config cfg;
153	struct ti_sysc_cookie cookie;
154	const char *name;
155	u32 revision;
156	u32 sysconfig;
157	unsigned int reserved:1;
158	unsigned int enabled:1;
159	unsigned int needs_resume:1;
160	unsigned int child_needs_resume:1;
161	struct delayed_work idle_work;
162	void (pre_reset_quirk)(struct sysc sysc);
163	void (post_reset_quirk)(struct sysc sysc);
164	void (reset_done_quirk)(struct sysc sysc);
165	void (module_enable_quirk)(struct sysc sysc);
166	void (module_disable_quirk)(struct sysc sysc);
167	void (module_unlock_quirk)(struct sysc sysc);
168	void (module_lock_quirk)(struct sysc sysc);
169	};
170
171	static void sysc_parse_dts_quirks(struct sysc ddata, struct device_node np,
172	bool is_child);
173	static int sysc_reset(struct sysc *ddata);
174
175	static void sysc_write(struct sysc *ddata, int offset, u32 value)
176	{
177	if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
178	writew_relaxed(value & 0xffff, ddata->module_va + offset);
179
180	/* Only i2c revision has LO and HI register with stride of 4 */
181	if (ddata->offsets[SYSC_REVISION] >= 0 &&
182	offset == ddata->offsets[SYSC_REVISION]) {
183	u16 hi = value >> 16;
184
185	writew_relaxed(hi, ddata->module_va + offset + 4);
186	}
187
188	return;
189	}
190
191	writel_relaxed(value, ddata->module_va + offset);
192	}
193
194	static u32 sysc_read(struct sysc *ddata, int offset)
195	{
196	if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
197	u32 val;
198
199	val = readw_relaxed(ddata->module_va + offset);
200
201	/* Only i2c revision has LO and HI register with stride of 4 */
202	if (ddata->offsets[SYSC_REVISION] >= 0 &&
203	offset == ddata->offsets[SYSC_REVISION]) {
204	u16 tmp = readw_relaxed(ddata->module_va + offset + 4);
205
206	val \|= tmp << 16;
207	}
208
209	return val;
210	}
211
212	return readl_relaxed(ddata->module_va + offset);
213	}
214
215	static bool sysc_opt_clks_needed(struct sysc *ddata)
216	{
217	return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED);
218	}
219
220	static u32 sysc_read_revision(struct sysc *ddata)
221	{
222	int offset = ddata->offsets[SYSC_REVISION];
223
224	if (offset < 0)
225	return 0;
226
227	return sysc_read(ddata, offset);
228	}
229
230	static u32 sysc_read_sysconfig(struct sysc *ddata)
231	{
232	int offset = ddata->offsets[SYSC_SYSCONFIG];
233
234	if (offset < 0)
235	return 0;
236
237	return sysc_read(ddata, offset);
238	}
239
240	static u32 sysc_read_sysstatus(struct sysc *ddata)
241	{
242	int offset = ddata->offsets[SYSC_SYSSTATUS];
243
244	if (offset < 0)
245	return 0;
246
247	return sysc_read(ddata, offset);
248	}
249
250	static int sysc_poll_reset_sysstatus(struct sysc *ddata)
251	{
252	int error, retries;
253	u32 syss_done, rstval;
254
255	if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED)
256	syss_done = 0;
257	else
258	syss_done = ddata->cfg.syss_mask;
259
260	if (likely(!timekeeping_suspended)) {
261	error = readx_poll_timeout_atomic(sysc_read_sysstatus, ddata,
262	rstval, (rstval & ddata->cfg.syss_mask) ==
263	syss_done, 100, MAX_MODULE_SOFTRESET_WAIT);
264	} else {
265	retries = MAX_MODULE_SOFTRESET_WAIT;
266	while (retries--) {
267	rstval = sysc_read_sysstatus(ddata);
268	if ((rstval & ddata->cfg.syss_mask) == syss_done)
269	return 0;
270	udelay(2); /* Account for udelay flakeyness */
271	}
272	error = -ETIMEDOUT;
273	}
274
275	return error;
276	}
277
278	static int sysc_poll_reset_sysconfig(struct sysc *ddata)
279	{
280	int error, retries;
281	u32 sysc_mask, rstval;
282
283	sysc_mask = BIT(ddata->cap->regbits->srst_shift);
284
285	if (likely(!timekeeping_suspended)) {
286	error = readx_poll_timeout_atomic(sysc_read_sysconfig, ddata,
287	rstval, !(rstval & sysc_mask),
288	100, MAX_MODULE_SOFTRESET_WAIT);
289	} else {
290	retries = MAX_MODULE_SOFTRESET_WAIT;
291	while (retries--) {
292	rstval = sysc_read_sysconfig(ddata);
293	if (!(rstval & sysc_mask))
294	return 0;
295	udelay(2); /* Account for udelay flakeyness */
296	}
297	error = -ETIMEDOUT;
298	}
299
300	return error;
301	}
302
303	/* Poll on reset status */
304	static int sysc_wait_softreset(struct sysc *ddata)
305	{
306	int syss_offset, error = 0;
307
308	if (ddata->cap->regbits->srst_shift < 0)
309	return 0;
310
311	syss_offset = ddata->offsets[SYSC_SYSSTATUS];
312
313	if (syss_offset >= 0)
314	error = sysc_poll_reset_sysstatus(ddata);
315	else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS)
316	error = sysc_poll_reset_sysconfig(ddata);
317
318	return error;
319	}
320
321	static int sysc_add_named_clock_from_child(struct sysc *ddata,
322	const char *name,
323	const char *optfck_name)
324	{
325	struct device_node *np = ddata->dev->of_node;
326	struct device_node *child;
327	struct clk_lookup *cl;
328	struct clk *clock;
329	const char *n;
330
331	if (name)
332	n = name;
333	else
334	n = optfck_name;
335
336	/* Does the clock alias already exist? */
337	clock = of_clk_get_by_name(np, n);
338	if (!IS_ERR(clock)) {
339	clk_put(clock);
340
341	return 0;
342	}
343
344	child = of_get_next_available_child(np, NULL);
345	if (!child)
346	return -ENODEV;
347
348	clock = devm_get_clk_from_child(ddata->dev, child, name);
349	if (IS_ERR(clock))
350	return PTR_ERR(clock);
351
352	/*
353	* Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID
354	* limit for clk_get(). If cl ever needs to be freed, it should be done
355	* with clkdev_drop().
356	*/
357	cl = kzalloc_obj(*cl);
358	if (!cl)
359	return -ENOMEM;
360
361	cl->con_id = n;
362	cl->dev_id = dev_name(ddata->dev);
363	cl->clk = clock;
364	clkdev_add(cl);
365
366	clk_put(clock);
367
368	return 0;
369	}
370
371	static int sysc_init_ext_opt_clock(struct sysc ddata, const char name)
372	{
373	const char *optfck_name;
374	int error, index;
375
376	if (ddata->nr_clocks < SYSC_OPTFCK0)
377	index = SYSC_OPTFCK0;
378	else
379	index = ddata->nr_clocks;
380
381	if (name)
382	optfck_name = name;
383	else
384	optfck_name = clock_names[index];
385
386	error = sysc_add_named_clock_from_child(ddata, name, optfck_name);
387	if (error)
388	return error;
389
390	ddata->clock_roles[index] = optfck_name;
391	ddata->nr_clocks++;
392
393	return 0;
394	}
395
396	static int sysc_get_one_clock(struct sysc ddata, const char name)
397	{
398	int error, i, index = -ENODEV;
399
400	if (!strncmp(clock_names[SYSC_FCK], name, 3))
401	index = SYSC_FCK;
402	else if (!strncmp(clock_names[SYSC_ICK], name, 3))
403	index = SYSC_ICK;
404
405	if (index < 0) {
406	for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
407	if (!ddata->clocks[i]) {
408	index = i;
409	break;
410	}
411	}
412	}
413
414	if (index < 0) {
415	dev_err(ddata->dev, "clock %s not added\n", name);
416	return index;
417	}
418
419	ddata->clocks[index] = devm_clk_get(ddata->dev, name);
420	if (IS_ERR(ddata->clocks[index])) {
421	dev_err(ddata->dev, "clock get error for %s: %li\n",
422	name, PTR_ERR(ddata->clocks[index]));
423
424	return PTR_ERR(ddata->clocks[index]);
425	}
426
427	error = clk_prepare(ddata->clocks[index]);
428	if (error) {
429	dev_err(ddata->dev, "clock prepare error for %s: %i\n",
430	name, error);
431
432	return error;
433	}
434
435	return 0;
436	}
437
438	static int sysc_get_clocks(struct sysc *ddata)
439	{
440	struct device_node *np = ddata->dev->of_node;
441	struct property *prop;
442	const char *name;
443	int nr_fck = 0, nr_ick = 0, i, error = 0;
444
445	ddata->clock_roles = devm_kcalloc(ddata->dev,
446	SYSC_MAX_CLOCKS,
447	sizeof(*ddata->clock_roles),
448	GFP_KERNEL);
449	if (!ddata->clock_roles)
450	return -ENOMEM;
451
452	of_property_for_each_string(np, "clock-names", prop, name) {
453	if (!strncmp(clock_names[SYSC_FCK], name, 3))
454	nr_fck++;
455	if (!strncmp(clock_names[SYSC_ICK], name, 3))
456	nr_ick++;
457	ddata->clock_roles[ddata->nr_clocks] = name;
458	ddata->nr_clocks++;
459	}
460
461	if (ddata->nr_clocks < 1)
462	return 0;
463
464	if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) {
465	error = sysc_init_ext_opt_clock(ddata, NULL);
466	if (error)
467	return error;
468	}
469
470	if (ddata->nr_clocks > SYSC_MAX_CLOCKS) {
471	dev_err(ddata->dev, "too many clocks for %pOF\n", np);
472
473	return -EINVAL;
474	}
475
476	if (nr_fck > 1 \|\| nr_ick > 1) {
477	dev_err(ddata->dev, "max one fck and ick for %pOF\n", np);
478
479	return -EINVAL;
480	}
481
482	/* Always add a slot for main clocks fck and ick even if unused */
483	if (!nr_fck)
484	ddata->nr_clocks++;
485	if (!nr_ick)
486	ddata->nr_clocks++;
487
488	ddata->clocks = devm_kcalloc(ddata->dev,
489	ddata->nr_clocks, sizeof(*ddata->clocks),
490	GFP_KERNEL);
491	if (!ddata->clocks)
492	return -ENOMEM;
493
494	for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
495	const char *name = ddata->clock_roles[i];
496
497	if (!name)
498	continue;
499
500	error = sysc_get_one_clock(ddata, name);
501	if (error)
502	return error;
503	}
504
505	return 0;
506	}
507
508	static int sysc_enable_main_clocks(struct sysc *ddata)
509	{
510	struct clk *clock;
511	int i, error;
512
513	if (!ddata->clocks)
514	return 0;
515
516	for (i = 0; i < SYSC_OPTFCK0; i++) {
517	clock = ddata->clocks[i];
518
519	/* Main clocks may not have ick */
520	if (IS_ERR_OR_NULL(clock))
521	continue;
522
523	error = clk_enable(clock);
524	if (error)
525	goto err_disable;
526	}
527
528	return 0;
529
530	err_disable:
531	for (i--; i >= 0; i--) {
532	clock = ddata->clocks[i];
533
534	/* Main clocks may not have ick */
535	if (IS_ERR_OR_NULL(clock))
536	continue;
537
538	clk_disable(clock);
539	}
540
541	return error;
542	}
543
544	static void sysc_disable_main_clocks(struct sysc *ddata)
545	{
546	struct clk *clock;
547	int i;
548
549	if (!ddata->clocks)
550	return;
551
552	for (i = 0; i < SYSC_OPTFCK0; i++) {
553	clock = ddata->clocks[i];
554	if (IS_ERR_OR_NULL(clock))
555	continue;
556
557	clk_disable(clock);
558	}
559	}
560
561	static int sysc_enable_opt_clocks(struct sysc *ddata)
562	{
563	struct clk *clock;
564	int i, error;
565
566	if (!ddata->clocks \|\| ddata->nr_clocks < SYSC_OPTFCK0 + 1)
567	return 0;
568
569	for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
570	clock = ddata->clocks[i];
571
572	/* Assume no holes for opt clocks */
573	if (IS_ERR_OR_NULL(clock))
574	return 0;
575
576	error = clk_enable(clock);
577	if (error)
578	goto err_disable;
579	}
580
581	return 0;
582
583	err_disable:
584	for (i--; i >= 0; i--) {
585	clock = ddata->clocks[i];
586	if (IS_ERR_OR_NULL(clock))
587	continue;
588
589	clk_disable(clock);
590	}
591
592	return error;
593	}
594
595	static void sysc_disable_opt_clocks(struct sysc *ddata)
596	{
597	struct clk *clock;
598	int i;
599
600	if (!ddata->clocks \|\| ddata->nr_clocks < SYSC_OPTFCK0 + 1)
601	return;
602
603	for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
604	clock = ddata->clocks[i];
605
606	/* Assume no holes for opt clocks */
607	if (IS_ERR_OR_NULL(clock))
608	return;
609
610	clk_disable(clock);
611	}
612	}
613
614	static void sysc_clkdm_deny_idle(struct sysc *ddata)
615	{
616	struct ti_sysc_platform_data *pdata;
617
618	if (ddata->legacy_mode \|\| (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
619	return;
620
621	pdata = dev_get_platdata(ddata->dev);
622	if (pdata && pdata->clkdm_deny_idle)
623	pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie);
624	}
625
626	static void sysc_clkdm_allow_idle(struct sysc *ddata)
627	{
628	struct ti_sysc_platform_data *pdata;
629
630	if (ddata->legacy_mode \|\| (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
631	return;
632
633	pdata = dev_get_platdata(ddata->dev);
634	if (pdata && pdata->clkdm_allow_idle)
635	pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie);
636	}
637
638	/**
639	* sysc_init_resets - init rstctrl reset line if configured
640	* @ddata: device driver data
641	*
642	* See sysc_rstctrl_reset_deassert().
643	*/
644	static int sysc_init_resets(struct sysc *ddata)
645	{
646	ddata->rsts =
647	devm_reset_control_get_optional_shared(ddata->dev, "rstctrl");
648
649	return PTR_ERR_OR_ZERO(ddata->rsts);
650	}
651
652	/**
653	* sysc_parse_and_check_child_range - parses module IO region from ranges
654	* @ddata: device driver data
655	*
656	* In general we only need rev, syss, and sysc registers and not the whole
657	* module range. But we do want the offsets for these registers from the
658	* module base. This allows us to check them against the legacy hwmod
659	* platform data. Let's also check the ranges are configured properly.
660	*/
661	static int sysc_parse_and_check_child_range(struct sysc *ddata)
662	{
663	struct device_node *np = ddata->dev->of_node;
664	struct of_range_parser parser;
665	struct of_range range;
666	int error;
667
668	error = of_range_parser_init(&parser, np);
669	if (error)
670	return error;
671
672	for_each_of_range(&parser, &range) {
673	ddata->module_pa = range.cpu_addr;
674	ddata->module_size = range.size;
675	break;
676	}
677
678	return 0;
679	}
680
681	static struct device_node *stdout_path;
682
683	static void sysc_init_stdout_path(struct sysc *ddata)
684	{
685	struct device_node *chosen;
686	struct device_node *np = NULL;
687	const char *uart;
688
689	if (IS_ERR(stdout_path))
690	return;
691
692	if (stdout_path)
693	return;
694
695	chosen = of_find_node_by_path("/chosen");
696	if (!chosen)
697	goto err;
698
699	uart = of_get_property(chosen, "stdout-path", NULL);
700	if (!uart) {
701	of_node_put(chosen);
702	goto err;
703	}
704
705	np = of_find_node_by_path(uart);
706	of_node_put(chosen);
707	if (!np)
708	goto err;
709
710	stdout_path = np;
711
712	return;
713
714	err:
715	stdout_path = ERR_PTR(-ENODEV);
716	}
717
718	static void sysc_check_quirk_stdout(struct sysc *ddata,
719	struct device_node *np)
720	{
721	sysc_init_stdout_path(ddata);
722	if (np != stdout_path)
723	return;
724
725	ddata->cfg.quirks \|= SYSC_QUIRK_NO_IDLE_ON_INIT \|
726	SYSC_QUIRK_NO_RESET_ON_INIT;
727	}
728
729	/**
730	* sysc_check_one_child - check child configuration
731	* @ddata: device driver data
732	* @np: child device node
733	*
734	* Let's avoid messy situations where we have new interconnect target
735	* node but children have "ti,hwmods". These belong to the interconnect
736	* target node and are managed by this driver.
737	*/
738	static void sysc_check_one_child(struct sysc *ddata,
739	struct device_node *np)
740	{
741	const char *name;
742
743	name = of_get_property(np, "ti,hwmods", NULL);
744	if (name && !of_device_is_compatible(np, "ti,sysc"))
745	dev_warn(ddata->dev, "really a child ti,hwmods property?");
746
747	sysc_check_quirk_stdout(ddata, np);
748	sysc_parse_dts_quirks(ddata, np, true);
749	}
750
751	static void sysc_check_children(struct sysc *ddata)
752	{
753	struct device_node *child;
754
755	for_each_child_of_node(ddata->dev->of_node, child)
756	sysc_check_one_child(ddata, child);
757	}
758
759	/*
760	* So far only I2C uses 16-bit read access with clockactivity with revision
761	* in two registers with stride of 4. We can detect this based on the rev
762	* register size to configure things far enough to be able to properly read
763	* the revision register.
764	*/
765	static void sysc_check_quirk_16bit(struct sysc ddata, struct resource res)
766	{
767	if (resource_size(res) == 8)
768	ddata->cfg.quirks \|= SYSC_QUIRK_16BIT \| SYSC_QUIRK_USE_CLOCKACT;
769	}
770
771	/**
772	* sysc_parse_one - parses the interconnect target module registers
773	* @ddata: device driver data
774	* @reg: register to parse
775	*/
776	static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg)
777	{
778	struct resource *res;
779	const char *name;
780
781	switch (reg) {
782	case SYSC_REVISION:
783	case SYSC_SYSCONFIG:
784	case SYSC_SYSSTATUS:
785	name = reg_names[reg];
786	break;
787	default:
788	return -EINVAL;
789	}
790
791	res = platform_get_resource_byname(to_platform_device(ddata->dev),
792	IORESOURCE_MEM, name);
793	if (!res) {
794	ddata->offsets[reg] = -ENODEV;
795
796	return 0;
797	}
798
799	ddata->offsets[reg] = res->start - ddata->module_pa;
800	if (reg == SYSC_REVISION)
801	sysc_check_quirk_16bit(ddata, res);
802
803	return 0;
804	}
805
806	static int sysc_parse_registers(struct sysc *ddata)
807	{
808	int i, error;
809
810	for (i = 0; i < SYSC_MAX_REGS; i++) {
811	error = sysc_parse_one(ddata, i);
812	if (error)
813	return error;
814	}
815
816	return 0;
817	}
818
819	/**
820	* sysc_check_registers - check for misconfigured register overlaps
821	* @ddata: device driver data
822	*/
823	static int sysc_check_registers(struct sysc *ddata)
824	{
825	int i, j, nr_regs = 0, nr_matches = 0;
826
827	for (i = 0; i < SYSC_MAX_REGS; i++) {
828	if (ddata->offsets[i] < 0)
829	continue;
830
831	if (ddata->offsets[i] > (ddata->module_size - 4)) {
832	dev_err(ddata->dev, "register outside module range");
833
834	return -EINVAL;
835	}
836
837	for (j = 0; j < SYSC_MAX_REGS; j++) {
838	if (ddata->offsets[j] < 0)
839	continue;
840
841	if (ddata->offsets[i] == ddata->offsets[j])
842	nr_matches++;
843	}
844	nr_regs++;
845	}
846
847	if (nr_matches > nr_regs) {
848	dev_err(ddata->dev, "overlapping registers: (%i/%i)",
849	nr_regs, nr_matches);
850
851	return -EINVAL;
852	}
853
854	return 0;
855	}
856
857	/**
858	* sysc_ioremap - ioremap register space for the interconnect target module
859	* @ddata: device driver data
860	*
861	* Note that the interconnect target module registers can be anywhere
862	* within the interconnect target module range. For example, SGX has
863	* them at offset 0x1fc00 in the 32MB module address space. And cpsw
864	* has them at offset 0x1200 in the CPSW_WR child. Usually the
865	* interconnect target module registers are at the beginning of
866	* the module range though.
867	*/
868	static int sysc_ioremap(struct sysc *ddata)
869	{
870	int size;
871
872	if (ddata->offsets[SYSC_REVISION] < 0 &&
873	ddata->offsets[SYSC_SYSCONFIG] < 0 &&
874	ddata->offsets[SYSC_SYSSTATUS] < 0) {
875	size = ddata->module_size;
876	} else {
877	size = max3(ddata->offsets[SYSC_REVISION],
878	ddata->offsets[SYSC_SYSCONFIG],
879	ddata->offsets[SYSC_SYSSTATUS]);
880
881	if (size < SZ_1K)
882	size = SZ_1K;
883
884	if ((size + sizeof(u32)) > ddata->module_size)
885	size = ddata->module_size;
886	}
887
888	ddata->module_va = devm_ioremap(ddata->dev,
889	ddata->module_pa,
890	size + sizeof(u32));
891	if (!ddata->module_va)
892	return -EIO;
893
894	return 0;
895	}
896
897	/**
898	* sysc_map_and_check_registers - ioremap and check device registers
899	* @ddata: device driver data
900	*/
901	static int sysc_map_and_check_registers(struct sysc *ddata)
902	{
903	struct device_node *np = ddata->dev->of_node;
904	int error;
905
906	error = sysc_parse_and_check_child_range(ddata);
907	if (error)
908	return error;
909
910	sysc_check_children(ddata);
911
912	if (!of_property_present(np, "reg"))
913	return 0;
914
915	error = sysc_parse_registers(ddata);
916	if (error)
917	return error;
918
919	error = sysc_ioremap(ddata);
920	if (error)
921	return error;
922
923	error = sysc_check_registers(ddata);
924	if (error)
925	return error;
926
927	return 0;
928	}
929
930	/**
931	* sysc_show_rev - read and show interconnect target module revision
932	* @bufp: buffer to print the information to
933	* @ddata: device driver data
934	*/
935	static int sysc_show_rev(char bufp, struct sysc ddata)
936	{
937	int len;
938
939	if (ddata->offsets[SYSC_REVISION] < 0)
940	return sprintf(bufp, ":NA");
941
942	len = sprintf(bufp, ":%08x", ddata->revision);
943
944	return len;
945	}
946
947	static int sysc_show_reg(struct sysc *ddata,
948	char *bufp, enum sysc_registers reg)
949	{
950	if (ddata->offsets[reg] < 0)
951	return sprintf(bufp, ":NA");
952
953	return sprintf(bufp, ":%x", ddata->offsets[reg]);
954	}
955
956	static int sysc_show_name(char bufp, struct sysc ddata)
957	{
958	if (!ddata->name)
959	return 0;
960
961	return sprintf(bufp, ":%s", ddata->name);
962	}
963
964	/**
965	* sysc_show_registers - show information about interconnect target module
966	* @ddata: device driver data
967	*/
968	static void sysc_show_registers(struct sysc *ddata)
969	{
970	char buf[128];
971	char *bufp = buf;
972	int i;
973
974	for (i = 0; i < SYSC_MAX_REGS; i++)
975	bufp += sysc_show_reg(ddata, bufp, i);
976
977	bufp += sysc_show_rev(bufp, ddata);
978	bufp += sysc_show_name(bufp, ddata);
979
980	dev_dbg(ddata->dev, "%llx:%x%s\n",
981	ddata->module_pa, ddata->module_size,
982	buf);
983	}
984
985	/**
986	* sysc_write_sysconfig - handle sysconfig quirks for register write
987	* @ddata: device driver data
988	* @value: register value
989	*/
990	static void sysc_write_sysconfig(struct sysc *ddata, u32 value)
991	{
992	if (ddata->module_unlock_quirk)
993	ddata->module_unlock_quirk(ddata);
994
995	sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], value);
996
997	if (ddata->module_lock_quirk)
998	ddata->module_lock_quirk(ddata);
999	}
1000
1001	#define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1)
1002	#define SYSC_CLOCACT_ICK 2
1003
1004	/* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
1005	static int sysc_enable_module(struct device *dev)
1006	{
1007	struct sysc *ddata;
1008	const struct sysc_regbits *regbits;
1009	u32 reg, idlemodes, best_mode;
1010	int error;
1011
1012	ddata = dev_get_drvdata(dev);
1013
1014	/*
1015	* Some modules like DSS reset automatically on idle. Enable optional
1016	* reset clocks and wait for OCP softreset to complete.
1017	*/
1018	if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) {
1019	error = sysc_enable_opt_clocks(ddata);
1020	if (error) {
1021	dev_err(ddata->dev,
1022	"Optional clocks failed for enable: %i\n",
1023	error);
1024	return error;
1025	}
1026	}
1027	/*
1028	* Some modules like i2c and hdq1w have unusable reset status unless
1029	* the module reset quirk is enabled. Skip status check on enable.
1030	*/
1031	if (!(ddata->cfg.quirks & SYSC_MODULE_QUIRK_ENA_RESETDONE)) {
1032	error = sysc_wait_softreset(ddata);
1033	if (error)
1034	dev_warn(ddata->dev, "OCP softreset timed out\n");
1035	}
1036	if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET)
1037	sysc_disable_opt_clocks(ddata);
1038
1039	/*
1040	* Some subsystem private interconnects, like DSS top level module,
1041	* need only the automatic OCP softreset handling with no sysconfig
1042	* register bits to configure.
1043	*/
1044	if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
1045	return 0;
1046
1047	regbits = ddata->cap->regbits;
1048	reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1049
1050	/*
1051	* Set CLOCKACTIVITY, we only use it for ick. And we only configure it
1052	* based on the SYSC_QUIRK_USE_CLOCKACT flag, not based on the hardware
1053	* capabilities. See the old HWMOD_SET_DEFAULT_CLOCKACT flag.
1054	*/
1055	if (regbits->clkact_shift >= 0 &&
1056	(ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT))
1057	reg \|= SYSC_CLOCACT_ICK << regbits->clkact_shift;
1058
1059	/* Set SIDLE mode */
1060	idlemodes = ddata->cfg.sidlemodes;
1061	if (!idlemodes \|\| regbits->sidle_shift < 0)
1062	goto set_midle;
1063
1064	if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE \|
1065	SYSC_QUIRK_SWSUP_SIDLE_ACT)) {
1066	best_mode = SYSC_IDLE_NO;
1067
1068	/* Clear WAKEUP */
1069	if (regbits->enwkup_shift >= 0 &&
1070	ddata->cfg.sysc_val & BIT(regbits->enwkup_shift))
1071	reg &= ~BIT(regbits->enwkup_shift);
1072	} else {
1073	best_mode = fls(ddata->cfg.sidlemodes) - 1;
1074	if (best_mode > SYSC_IDLE_MASK) {
1075	dev_err(dev, "%s: invalid sidlemode\n", __func__);
1076	return -EINVAL;
1077	}
1078
1079	/* Set WAKEUP */
1080	if (regbits->enwkup_shift >= 0 &&
1081	ddata->cfg.sysc_val & BIT(regbits->enwkup_shift))
1082	reg \|= BIT(regbits->enwkup_shift);
1083	}
1084
1085	reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1086	reg \|= best_mode << regbits->sidle_shift;
1087	sysc_write_sysconfig(ddata, reg);
1088
1089	set_midle:
1090	/* Set MIDLE mode */
1091	idlemodes = ddata->cfg.midlemodes;
1092	if (!idlemodes \|\| regbits->midle_shift < 0)
1093	goto set_autoidle;
1094
1095	best_mode = fls(ddata->cfg.midlemodes) - 1;
1096	if (best_mode > SYSC_IDLE_MASK) {
1097	dev_err(dev, "%s: invalid midlemode\n", __func__);
1098	error = -EINVAL;
1099	goto save_context;
1100	}
1101
1102	if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY)
1103	best_mode = SYSC_IDLE_NO;
1104
1105	reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
1106	reg \|= best_mode << regbits->midle_shift;
1107	sysc_write_sysconfig(ddata, reg);
1108
1109	set_autoidle:
1110	/* Autoidle bit must enabled separately if available */
1111	if (regbits->autoidle_shift >= 0 &&
1112	ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) {
1113	reg \|= 1 << regbits->autoidle_shift;
1114	sysc_write_sysconfig(ddata, reg);
1115	}
1116
1117	error = 0;
1118
1119	save_context:
1120	/* Save context and flush posted write */
1121	ddata->sysconfig = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1122
1123	if (ddata->module_enable_quirk)
1124	ddata->module_enable_quirk(ddata);
1125
1126	return error;
1127	}
1128
1129	static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode)
1130	{
1131	if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP))
1132	*best_mode = SYSC_IDLE_SMART_WKUP;
1133	else if (idlemodes & BIT(SYSC_IDLE_SMART))
1134	*best_mode = SYSC_IDLE_SMART;
1135	else if (idlemodes & BIT(SYSC_IDLE_FORCE))
1136	*best_mode = SYSC_IDLE_FORCE;
1137	else
1138	return -EINVAL;
1139
1140	return 0;
1141	}
1142
1143	/* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
1144	static int sysc_disable_module(struct device *dev)
1145	{
1146	struct sysc *ddata;
1147	const struct sysc_regbits *regbits;
1148	u32 reg, idlemodes, best_mode;
1149	int ret;
1150
1151	ddata = dev_get_drvdata(dev);
1152	if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
1153	return 0;
1154
1155	if (ddata->module_disable_quirk)
1156	ddata->module_disable_quirk(ddata);
1157
1158	regbits = ddata->cap->regbits;
1159	reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1160
1161	/* Set MIDLE mode */
1162	idlemodes = ddata->cfg.midlemodes;
1163	if (!idlemodes \|\| regbits->midle_shift < 0)
1164	goto set_sidle;
1165
1166	ret = sysc_best_idle_mode(idlemodes, &best_mode);
1167	if (ret) {
1168	dev_err(dev, "%s: invalid midlemode\n", __func__);
1169	return ret;
1170	}
1171
1172	if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_MSTANDBY) \|\|
1173	ddata->cfg.quirks & (SYSC_QUIRK_FORCE_MSTANDBY))
1174	best_mode = SYSC_IDLE_FORCE;
1175
1176	reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
1177	reg \|= best_mode << regbits->midle_shift;
1178	sysc_write_sysconfig(ddata, reg);
1179
1180	set_sidle:
1181	/* Set SIDLE mode */
1182	idlemodes = ddata->cfg.sidlemodes;
1183	if (!idlemodes \|\| regbits->sidle_shift < 0) {
1184	ret = 0;
1185	goto save_context;
1186	}
1187
1188	if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) {
1189	best_mode = SYSC_IDLE_FORCE;
1190	} else {
1191	ret = sysc_best_idle_mode(idlemodes, &best_mode);
1192	if (ret) {
1193	dev_err(dev, "%s: invalid sidlemode\n", __func__);
1194	ret = -EINVAL;
1195	goto save_context;
1196	}
1197	}
1198
1199	if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE_ACT) {
1200	/* Set WAKEUP */
1201	if (regbits->enwkup_shift >= 0 &&
1202	ddata->cfg.sysc_val & BIT(regbits->enwkup_shift))
1203	reg \|= BIT(regbits->enwkup_shift);
1204	}
1205
1206	reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1207	reg \|= best_mode << regbits->sidle_shift;
1208	if (regbits->autoidle_shift >= 0 &&
1209	ddata->cfg.sysc_val & BIT(regbits->autoidle_shift))
1210	reg \|= 1 << regbits->autoidle_shift;
1211	sysc_write_sysconfig(ddata, reg);
1212
1213	ret = 0;
1214
1215	save_context:
1216	/* Save context and flush posted write */
1217	ddata->sysconfig = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1218
1219	return ret;
1220	}
1221
1222	static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev,
1223	struct sysc *ddata)
1224	{
1225	struct ti_sysc_platform_data *pdata;
1226	int error;
1227
1228	pdata = dev_get_platdata(ddata->dev);
1229	if (!pdata)
1230	return 0;
1231
1232	if (!pdata->idle_module)
1233	return -ENODEV;
1234
1235	error = pdata->idle_module(dev, &ddata->cookie);
1236	if (error)
1237	dev_err(dev, "%s: could not idle: %i\n",
1238	__func__, error);
1239
1240	reset_control_assert(ddata->rsts);
1241
1242	return 0;
1243	}
1244
1245	static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev,
1246	struct sysc *ddata)
1247	{
1248	struct ti_sysc_platform_data *pdata;
1249	int error;
1250
1251	pdata = dev_get_platdata(ddata->dev);
1252	if (!pdata)
1253	return 0;
1254
1255	if (!pdata->enable_module)
1256	return -ENODEV;
1257
1258	error = pdata->enable_module(dev, &ddata->cookie);
1259	if (error)
1260	dev_err(dev, "%s: could not enable: %i\n",
1261	__func__, error);
1262
1263	reset_control_deassert(ddata->rsts);
1264
1265	return 0;
1266	}
1267
1268	static int __maybe_unused sysc_runtime_suspend(struct device *dev)
1269	{
1270	struct sysc *ddata;
1271	int error = 0;
1272
1273	ddata = dev_get_drvdata(dev);
1274
1275	if (!ddata->enabled)
1276	return 0;
1277
1278	sysc_clkdm_deny_idle(ddata);
1279
1280	if (ddata->legacy_mode) {
1281	error = sysc_runtime_suspend_legacy(dev, ddata);
1282	if (error)
1283	goto err_allow_idle;
1284	} else {
1285	error = sysc_disable_module(dev);
1286	if (error)
1287	goto err_allow_idle;
1288	}
1289
1290	sysc_disable_main_clocks(ddata);
1291
1292	if (sysc_opt_clks_needed(ddata))
1293	sysc_disable_opt_clocks(ddata);
1294
1295	ddata->enabled = false;
1296
1297	err_allow_idle:
1298	sysc_clkdm_allow_idle(ddata);
1299
1300	reset_control_assert(ddata->rsts);
1301
1302	return error;
1303	}
1304
1305	static int __maybe_unused sysc_runtime_resume(struct device *dev)
1306	{
1307	struct sysc *ddata;
1308	int error = 0;
1309
1310	ddata = dev_get_drvdata(dev);
1311
1312	if (ddata->enabled)
1313	return 0;
1314
1315
1316	sysc_clkdm_deny_idle(ddata);
1317
1318	if (sysc_opt_clks_needed(ddata)) {
1319	error = sysc_enable_opt_clocks(ddata);
1320	if (error)
1321	goto err_allow_idle;
1322	}
1323
1324	error = sysc_enable_main_clocks(ddata);
1325	if (error)
1326	goto err_opt_clocks;
1327
1328	reset_control_deassert(ddata->rsts);
1329
1330	if (ddata->legacy_mode) {
1331	error = sysc_runtime_resume_legacy(dev, ddata);
1332	if (error)
1333	goto err_main_clocks;
1334	} else {
1335	error = sysc_enable_module(dev);
1336	if (error)
1337	goto err_main_clocks;
1338	}
1339
1340	ddata->enabled = true;
1341
1342	sysc_clkdm_allow_idle(ddata);
1343
1344	return 0;
1345
1346	err_main_clocks:
1347	sysc_disable_main_clocks(ddata);
1348	err_opt_clocks:
1349	if (sysc_opt_clks_needed(ddata))
1350	sysc_disable_opt_clocks(ddata);
1351	err_allow_idle:
1352	sysc_clkdm_allow_idle(ddata);
1353
1354	return error;
1355	}
1356
1357	/*
1358	* Checks if device context was lost. Assumes the sysconfig register value
1359	* after lost context is different from the configured value. Only works for
1360	* enabled devices.
1361	*
1362	* Eventually we may want to also add support to using the context lost
1363	* registers that some SoCs have.
1364	*/
1365	static int sysc_check_context(struct sysc *ddata)
1366	{
1367	u32 reg;
1368
1369	if (!ddata->enabled)
1370	return -ENODATA;
1371
1372	reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1373	if (reg == ddata->sysconfig)
1374	return 0;
1375
1376	return -EACCES;
1377	}
1378
1379	static int sysc_reinit_module(struct sysc *ddata, bool leave_enabled)
1380	{
1381	struct device *dev = ddata->dev;
1382	int error;
1383
1384	if (ddata->enabled) {
1385	/* Nothing to do if enabled and context not lost */
1386	error = sysc_check_context(ddata);
1387	if (!error)
1388	return 0;
1389
1390	/* Disable target module if it is enabled */
1391	error = sysc_runtime_suspend(dev);
1392	if (error)
1393	dev_warn(dev, "reinit suspend failed: %i\n", error);
1394	}
1395
1396	/* Enable target module */
1397	error = sysc_runtime_resume(dev);
1398	if (error)
1399	dev_warn(dev, "reinit resume failed: %i\n", error);
1400
1401	/* Some modules like am335x gpmc need reset and restore of sysconfig */
1402	if (ddata->cfg.quirks & SYSC_QUIRK_RESET_ON_CTX_LOST) {
1403	error = sysc_reset(ddata);
1404	if (error)
1405	dev_warn(dev, "reinit reset failed: %i\n", error);
1406
1407	sysc_write_sysconfig(ddata, ddata->sysconfig);
1408	}
1409
1410	if (leave_enabled)
1411	return error;
1412
1413	/* Disable target module if no leave_enabled was set */
1414	error = sysc_runtime_suspend(dev);
1415	if (error)
1416	dev_warn(dev, "reinit suspend failed: %i\n", error);
1417
1418	return error;
1419	}
1420
1421	static int __maybe_unused sysc_noirq_suspend(struct device *dev)
1422	{
1423	struct sysc *ddata;
1424
1425	ddata = dev_get_drvdata(dev);
1426
1427	if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)
1428	return 0;
1429
1430	if (!ddata->enabled)
1431	return 0;
1432
1433	ddata->needs_resume = 1;
1434
1435	return sysc_runtime_suspend(dev);
1436	}
1437
1438	static int __maybe_unused sysc_noirq_resume(struct device *dev)
1439	{
1440	struct sysc *ddata;
1441	int error = 0;
1442
1443	ddata = dev_get_drvdata(dev);
1444
1445	if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)
1446	return 0;
1447
1448	if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_RESUME) {
1449	error = sysc_reinit_module(ddata, ddata->needs_resume);
1450	if (error)
1451	dev_warn(dev, "noirq_resume failed: %i\n", error);
1452	} else if (ddata->needs_resume) {
1453	error = sysc_runtime_resume(dev);
1454	if (error)
1455	dev_warn(dev, "noirq_resume failed: %i\n", error);
1456	}
1457
1458	ddata->needs_resume = 0;
1459
1460	return error;
1461	}
1462
1463	static const struct dev_pm_ops sysc_pm_ops = {
1464	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume)
1465	SET_RUNTIME_PM_OPS(sysc_runtime_suspend,
1466	sysc_runtime_resume,
1467	NULL)
1468	};
1469
1470	/* Module revision register based quirks */
1471	struct sysc_revision_quirk {
1472	const char *name;
1473	u32 base;
1474	int rev_offset;
1475	int sysc_offset;
1476	int syss_offset;
1477	u32 revision;
1478	u32 revision_mask;
1479	u32 quirks;
1480	};
1481
1482	#define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \
1483	optrev_val, optrevmask, optquirkmask) \
1484	{ \
1485	.name = (optname), \
1486	.base = (optbase), \
1487	.rev_offset = (optrev), \
1488	.sysc_offset = (optsysc), \
1489	.syss_offset = (optsyss), \
1490	.revision = (optrev_val), \
1491	.revision_mask = (optrevmask), \
1492	.quirks = (optquirkmask), \
1493	}
1494
1495	static const struct sysc_revision_quirk sysc_revision_quirks[] = {
1496	/* Quirks that need to be set based on the module address */
1497	SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -ENODEV, 0x50000800, 0xffffffff,
1498	SYSC_QUIRK_EXT_OPT_CLOCK \| SYSC_QUIRK_NO_RESET_ON_INIT \|
1499	SYSC_QUIRK_SWSUP_SIDLE),
1500
1501	/* Quirks that need to be set based on detected module */
1502	SYSC_QUIRK("aess", 0, 0, 0x10, -ENODEV, 0x40000000, 0xffffffff,
1503	SYSC_MODULE_QUIRK_AESS),
1504	/* Errata i893 handling for dra7 dcan1 and 2 */
1505	SYSC_QUIRK("dcan", 0x4ae3c000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff,
1506	SYSC_QUIRK_CLKDM_NOAUTO),
1507	SYSC_QUIRK("dcan", 0x48480000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff,
1508	SYSC_QUIRK_CLKDM_NOAUTO),
1509	SYSC_QUIRK("dss", 0x4832a000, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
1510	SYSC_QUIRK_OPT_CLKS_IN_RESET \| SYSC_MODULE_QUIRK_DSS_RESET),
1511	SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000040, 0xffffffff,
1512	SYSC_QUIRK_OPT_CLKS_IN_RESET \| SYSC_MODULE_QUIRK_DSS_RESET),
1513	SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000061, 0xffffffff,
1514	SYSC_QUIRK_OPT_CLKS_IN_RESET \| SYSC_MODULE_QUIRK_DSS_RESET),
1515	SYSC_QUIRK("dwc3", 0x48880000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
1516	SYSC_QUIRK_CLKDM_NOAUTO),
1517	SYSC_QUIRK("dwc3", 0x488c0000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
1518	SYSC_QUIRK_CLKDM_NOAUTO),
1519	SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff,
1520	SYSC_QUIRK_OPT_CLKS_IN_RESET),
1521	SYSC_QUIRK("gpmc", 0, 0, 0x10, 0x14, 0x00000060, 0xffffffff,
1522	SYSC_QUIRK_REINIT_ON_CTX_LOST \| SYSC_QUIRK_RESET_ON_CTX_LOST \|
1523	SYSC_QUIRK_GPMC_DEBUG),
1524	SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50030200, 0xffffffff,
1525	SYSC_QUIRK_OPT_CLKS_NEEDED),
1526	SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff,
1527	SYSC_MODULE_QUIRK_HDQ1W \| SYSC_MODULE_QUIRK_ENA_RESETDONE),
1528	SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff,
1529	SYSC_MODULE_QUIRK_HDQ1W \| SYSC_MODULE_QUIRK_ENA_RESETDONE),
1530	SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff,
1531	SYSC_MODULE_QUIRK_I2C \| SYSC_MODULE_QUIRK_ENA_RESETDONE),
1532	SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff,
1533	SYSC_MODULE_QUIRK_I2C \| SYSC_MODULE_QUIRK_ENA_RESETDONE),
1534	SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff,
1535	SYSC_MODULE_QUIRK_I2C \| SYSC_MODULE_QUIRK_ENA_RESETDONE),
1536	SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0,
1537	SYSC_MODULE_QUIRK_I2C \| SYSC_MODULE_QUIRK_ENA_RESETDONE),
1538	SYSC_QUIRK("gpu", 0x50000000, 0x14, -ENODEV, -ENODEV, 0x00010201, 0xffffffff, 0),
1539	SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff,
1540	SYSC_MODULE_QUIRK_SGX),
1541	SYSC_QUIRK("lcdc", 0, 0, 0x54, -ENODEV, 0x4f201000, 0xffffffff,
1542	SYSC_QUIRK_SWSUP_SIDLE \| SYSC_QUIRK_SWSUP_MSTANDBY),
1543	SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44306302, 0xffffffff,
1544	SYSC_QUIRK_SWSUP_SIDLE),
1545	SYSC_QUIRK("rtc", 0, 0x74, 0x78, -ENODEV, 0x4eb01908, 0xffff00f0,
1546	SYSC_MODULE_QUIRK_RTC_UNLOCK),
1547	SYSC_QUIRK("tptc", 0, 0, 0x10, -ENODEV, 0x40006c00, 0xffffefff,
1548	SYSC_QUIRK_SWSUP_SIDLE \| SYSC_QUIRK_SWSUP_MSTANDBY),
1549	SYSC_QUIRK("tptc", 0, 0, -ENODEV, -ENODEV, 0x40007c00, 0xffffffff,
1550	SYSC_QUIRK_SWSUP_SIDLE \| SYSC_QUIRK_SWSUP_MSTANDBY),
1551	SYSC_QUIRK("sata", 0, 0xfc, 0x1100, -ENODEV, 0x5e412000, 0xffffffff,
1552	SYSC_QUIRK_SWSUP_SIDLE \| SYSC_QUIRK_SWSUP_MSTANDBY),
1553	SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff,
1554	SYSC_QUIRK_SWSUP_SIDLE_ACT),
1555	SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,
1556	SYSC_QUIRK_SWSUP_SIDLE_ACT),
1557	/* Uarts on omap4 and later */
1558	SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff,
1559	SYSC_QUIRK_SWSUP_SIDLE_ACT),
1560	SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff,
1561	SYSC_QUIRK_SWSUP_SIDLE_ACT),
1562	SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47424e03, 0xffffffff,
1563	SYSC_QUIRK_SWSUP_SIDLE_ACT),
1564	SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff,
1565	SYSC_QUIRK_SWSUP_SIDLE \| SYSC_QUIRK_SWSUP_MSTANDBY),
1566	SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -ENODEV, 0x50700101, 0xffffffff,
1567	SYSC_QUIRK_SWSUP_SIDLE \| SYSC_QUIRK_SWSUP_MSTANDBY),
1568	SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000033,
1569	0xffffffff, SYSC_QUIRK_SWSUP_SIDLE \| SYSC_QUIRK_SWSUP_MSTANDBY \|
1570	SYSC_MODULE_QUIRK_OTG),
1571	SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000040,
1572	0xffffffff, SYSC_QUIRK_SWSUP_SIDLE \| SYSC_QUIRK_SWSUP_MSTANDBY \|
1573	SYSC_MODULE_QUIRK_OTG),
1574	SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
1575	0xffffffff, SYSC_QUIRK_SWSUP_SIDLE \| SYSC_QUIRK_SWSUP_MSTANDBY \|
1576	SYSC_MODULE_QUIRK_OTG),
1577	SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -ENODEV, 0x4ea2080d, 0xffffffff,
1578	SYSC_QUIRK_SWSUP_SIDLE \| SYSC_QUIRK_SWSUP_MSTANDBY \|
1579	SYSC_QUIRK_REINIT_ON_CTX_LOST),
1580	SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1581	SYSC_MODULE_QUIRK_WDT),
1582	/* PRUSS on am3, am4 and am5 */
1583	SYSC_QUIRK("pruss", 0, 0x26000, 0x26004, -ENODEV, 0x47000000, 0xff000000,
1584	SYSC_MODULE_QUIRK_PRUSS),
1585	/* Watchdog on am3 and am4 */
1586	SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1587	SYSC_MODULE_QUIRK_WDT \| SYSC_QUIRK_SWSUP_SIDLE),
1588
1589	#ifdef DEBUG
1590	SYSC_QUIRK("adc", 0, 0, 0x10, -ENODEV, 0x47300001, 0xffffffff, 0),
1591	SYSC_QUIRK("atl", 0, 0, -ENODEV, -ENODEV, 0x0a070100, 0xffffffff, 0),
1592	SYSC_QUIRK("cm", 0, 0, -ENODEV, -ENODEV, 0x40000301, 0xffffffff, 0),
1593	SYSC_QUIRK("control", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
1594	SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
1595	0xffff00f0, 0),
1596	SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 0),
1597	SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0x4edb1902, 0xffffffff, 0),
1598	SYSC_QUIRK("dispc", 0x4832a400, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1599	SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1600	SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000051, 0xffffffff, 0),
1601	SYSC_QUIRK("dmic", 0, 0, 0x10, -ENODEV, 0x50010000, 0xffffffff, 0),
1602	SYSC_QUIRK("dsi", 0x58004000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1603	SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1604	SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1605	SYSC_QUIRK("dsi", 0x58009000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1606	SYSC_QUIRK("dwc3", 0, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 0),
1607	SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1608	SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1609	SYSC_QUIRK("elm", 0x48080000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0),
1610	SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x40441403, 0xffff0fff, 0),
1611	SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x50440500, 0xffffffff, 0),
1612	SYSC_QUIRK("epwmss", 0, 0, 0x4, -ENODEV, 0x47400001, 0xffffffff, 0),
1613	SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -ENODEV, 0, 0, 0),
1614	SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 0),
1615	SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50031d00, 0xffffffff, 0),
1616	SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0),
1617	SYSC_QUIRK("iss", 0, 0, 0x10, -ENODEV, 0x40000101, 0xffffffff, 0),
1618	SYSC_QUIRK("keypad", 0x4a31c000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0),
1619	SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44307b02, 0xffffffff, 0),
1620	SYSC_QUIRK("mcbsp", 0, -ENODEV, 0x8c, -ENODEV, 0, 0, 0),
1621	SYSC_QUIRK("mcspi", 0, 0, 0x10, -ENODEV, 0x40300a0b, 0xffff00ff, 0),
1622	SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0),
1623	SYSC_QUIRK("mailbox", 0, 0, 0x10, -ENODEV, 0x00000400, 0xffffffff, 0),
1624	SYSC_QUIRK("m3", 0, 0, -ENODEV, -ENODEV, 0x5f580105, 0x0fff0f00, 0),
1625	SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0),
1626	SYSC_QUIRK("ocp2scp", 0, 0, -ENODEV, -ENODEV, 0x50060007, 0xffffffff, 0),
1627	SYSC_QUIRK("padconf", 0, 0, 0x10, -ENODEV, 0x4fff0800, 0xffffffff, 0),
1628	SYSC_QUIRK("padconf", 0, 0, -ENODEV, -ENODEV, 0x40001100, 0xffffffff, 0),
1629	SYSC_QUIRK("pcie", 0x51000000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0),
1630	SYSC_QUIRK("pcie", 0x51800000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0),
1631	SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000100, 0xffffffff, 0),
1632	SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x00004102, 0xffffffff, 0),
1633	SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000400, 0xffffffff, 0),
1634	SYSC_QUIRK("rfbi", 0x4832a800, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1635	SYSC_QUIRK("rfbi", 0x58002000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1636	SYSC_QUIRK("scm", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
1637	SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4e8b0100, 0xffffffff, 0),
1638	SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4f000100, 0xffffffff, 0),
1639	SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x40000900, 0xffffffff, 0),
1640	SYSC_QUIRK("scrm", 0, 0, -ENODEV, -ENODEV, 0x00000010, 0xffffffff, 0),
1641	SYSC_QUIRK("sdio", 0, 0, 0x10, -ENODEV, 0x40202301, 0xffff0ff0, 0),
1642	SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0),
1643	SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0),
1644	SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff, 0),
1645	SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40000902, 0xffffffff, 0),
1646	SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40002903, 0xffffffff, 0),
1647	SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x24, -ENODEV, 0x00000000, 0xffffffff, 0),
1648	SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x38, -ENODEV, 0x00000000, 0xffffffff, 0),
1649	SYSC_QUIRK("spinlock", 0, 0, 0x10, -ENODEV, 0x50020000, 0xffffffff, 0),
1650	SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -ENODEV, 0x00000020, 0xffffffff, 0),
1651	SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000013, 0xffffffff, 0),
1652	SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, 0),
1653	/* Some timers on omap4 and later */
1654	SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x50002100, 0xffffffff, 0),
1655	SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x4fff1301, 0xffff00ff, 0),
1656	SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000040, 0xffffffff, 0),
1657	SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000011, 0xffffffff, 0),
1658	SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000060, 0xffffffff, 0),
1659	SYSC_QUIRK("tpcc", 0, 0, -ENODEV, -ENODEV, 0x40014c00, 0xffffffff, 0),
1660	SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0),
1661	SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0),
1662	SYSC_QUIRK("venc", 0x58003000, 0, -ENODEV, -ENODEV, 0x00000002, 0xffffffff, 0),
1663	SYSC_QUIRK("vfpe", 0, 0, 0x104, -ENODEV, 0x4d001200, 0xffffffff, 0),
1664	#endif
1665	};
1666
1667	/*
1668	* Early quirks based on module base and register offsets only that are
1669	* needed before the module revision can be read
1670	*/
1671	static void sysc_init_early_quirks(struct sysc *ddata)
1672	{
1673	const struct sysc_revision_quirk *q;
1674	int i;
1675
1676	for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1677	q = &sysc_revision_quirks[i];
1678
1679	if (!q->base)
1680	continue;
1681
1682	if (q->base != ddata->module_pa)
1683	continue;
1684
1685	if (q->rev_offset != ddata->offsets[SYSC_REVISION])
1686	continue;
1687
1688	if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1689	continue;
1690
1691	if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1692	continue;
1693
1694	ddata->name = q->name;
1695	ddata->cfg.quirks \|= q->quirks;
1696	}
1697	}
1698
1699	/* Quirks that also consider the revision register value */
1700	static void sysc_init_revision_quirks(struct sysc *ddata)
1701	{
1702	const struct sysc_revision_quirk *q;
1703	int i;
1704
1705	for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1706	q = &sysc_revision_quirks[i];
1707
1708	if (q->base && q->base != ddata->module_pa)
1709	continue;
1710
1711	if (q->rev_offset != ddata->offsets[SYSC_REVISION])
1712	continue;
1713
1714	if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1715	continue;
1716
1717	if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1718	continue;
1719
1720	if (q->revision == ddata->revision \|\|
1721	(q->revision & q->revision_mask) ==
1722	(ddata->revision & q->revision_mask)) {
1723	ddata->name = q->name;
1724	ddata->cfg.quirks \|= q->quirks;
1725	}
1726	}
1727	}
1728
1729	/*
1730	* DSS needs dispc outputs disabled to reset modules. Returns mask of
1731	* enabled DSS interrupts. Eventually we may be able to do this on
1732	* dispc init rather than top-level DSS init.
1733	*/
1734	static u32 sysc_quirk_dispc(struct sysc *ddata, int dispc_offset,
1735	bool disable)
1736	{
1737	bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
1738	const int lcd_en_mask = BIT(0), digit_en_mask = BIT(1);
1739	int manager_count;
1740	bool framedonetv_irq = true;
1741	u32 val, irq_mask = 0;
1742
1743	switch (sysc_soc->soc) {
1744	case SOC_2420 ... SOC_3630:
1745	manager_count = 2;
1746	framedonetv_irq = false;
1747	break;
1748	case SOC_4430 ... SOC_4470:
1749	manager_count = 3;
1750	break;
1751	case SOC_5430:
1752	case SOC_DRA7:
1753	manager_count = 4;
1754	break;
1755	case SOC_AM4:
1756	manager_count = 1;
1757	framedonetv_irq = false;
1758	break;
1759	case SOC_UNKNOWN:
1760	default:
1761	return 0;
1762	}
1763
1764	/* Remap the whole module range to be able to reset dispc outputs */
1765	devm_iounmap(ddata->dev, ddata->module_va);
1766	ddata->module_va = devm_ioremap(ddata->dev,
1767	ddata->module_pa,
1768	ddata->module_size);
1769	if (!ddata->module_va)
1770	return -EIO;
1771
1772	/* DISP_CONTROL, shut down lcd and digit on disable if enabled */
1773	val = sysc_read(ddata, dispc_offset + 0x40);
1774	lcd_en = val & lcd_en_mask;
1775	digit_en = val & digit_en_mask;
1776	if (lcd_en)
1777	irq_mask \|= BIT(0); /* FRAMEDONE */
1778	if (digit_en) {
1779	if (framedonetv_irq)
1780	irq_mask \|= BIT(24); /* FRAMEDONETV */
1781	else
1782	irq_mask \|= BIT(2) \| BIT(3); /* EVSYNC bits */
1783	}
1784	if (disable && (lcd_en \|\| digit_en))
1785	sysc_write(ddata, dispc_offset + 0x40,
1786	val & ~(lcd_en_mask \| digit_en_mask));
1787
1788	if (manager_count <= 2)
1789	return irq_mask;
1790
1791	/* DISPC_CONTROL2 */
1792	val = sysc_read(ddata, dispc_offset + 0x238);
1793	lcd2_en = val & lcd_en_mask;
1794	if (lcd2_en)
1795	irq_mask \|= BIT(22); /* FRAMEDONE2 */
1796	if (disable && lcd2_en)
1797	sysc_write(ddata, dispc_offset + 0x238,
1798	val & ~lcd_en_mask);
1799
1800	if (manager_count <= 3)
1801	return irq_mask;
1802
1803	/* DISPC_CONTROL3 */
1804	val = sysc_read(ddata, dispc_offset + 0x848);
1805	lcd3_en = val & lcd_en_mask;
1806	if (lcd3_en)
1807	irq_mask \|= BIT(30); /* FRAMEDONE3 */
1808	if (disable && lcd3_en)
1809	sysc_write(ddata, dispc_offset + 0x848,
1810	val & ~lcd_en_mask);
1811
1812	return irq_mask;
1813	}
1814
1815	/* DSS needs child outputs disabled and SDI registers cleared for reset */
1816	static void sysc_pre_reset_quirk_dss(struct sysc *ddata)
1817	{
1818	const int dispc_offset = 0x1000;
1819	int error;
1820	u32 irq_mask, val;
1821
1822	/* Get enabled outputs */
1823	irq_mask = sysc_quirk_dispc(ddata, dispc_offset, false);
1824	if (!irq_mask)
1825	return;
1826
1827	/* Clear IRQSTATUS */
1828	sysc_write(ddata, dispc_offset + 0x18, irq_mask);
1829
1830	/* Disable outputs */
1831	val = sysc_quirk_dispc(ddata, dispc_offset, true);
1832
1833	/* Poll IRQSTATUS */
1834	error = readl_poll_timeout(ddata->module_va + dispc_offset + 0x18,
1835	val, val != irq_mask, 100, 50);
1836	if (error)
1837	dev_warn(ddata->dev, "%s: timed out %08x !+ %08x\n",
1838	__func__, val, irq_mask);
1839
1840	if (sysc_soc->soc == SOC_3430 \|\| sysc_soc->soc == SOC_AM35) {
1841	/* Clear DSS_SDI_CONTROL */
1842	sysc_write(ddata, 0x44, 0);
1843
1844	/* Clear DSS_PLL_CONTROL */
1845	sysc_write(ddata, 0x48, 0);
1846	}
1847
1848	/* Clear DSS_CONTROL to switch DSS clock sources to PRCM if not */
1849	sysc_write(ddata, 0x40, 0);
1850	}
1851
1852	/* 1-wire needs module's internal clocks enabled for reset */
1853	static void sysc_pre_reset_quirk_hdq1w(struct sysc *ddata)
1854	{
1855	int offset = 0x0c; /* HDQ_CTRL_STATUS */
1856	u16 val;
1857
1858	val = sysc_read(ddata, offset);
1859	val \|= BIT(5);
1860	sysc_write(ddata, offset, val);
1861	}
1862
1863	/* AESS (Audio Engine SubSystem) needs autogating set after enable */
1864	static void sysc_module_enable_quirk_aess(struct sysc *ddata)
1865	{
1866	int offset = 0x7c; /* AESS_AUTO_GATING_ENABLE */
1867
1868	sysc_write(ddata, offset, 1);
1869	}
1870
1871	/* I2C needs to be disabled for reset */
1872	static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable)
1873	{
1874	int offset;
1875	u16 val;
1876
1877	/* I2C_CON, omap2/3 is different from omap4 and later */
1878	if ((ddata->revision & 0xffffff00) == 0x001f0000)
1879	offset = 0x24;
1880	else
1881	offset = 0xa4;
1882
1883	/* I2C_EN */
1884	val = sysc_read(ddata, offset);
1885	if (enable)
1886	val \|= BIT(15);
1887	else
1888	val &= ~BIT(15);
1889	sysc_write(ddata, offset, val);
1890	}
1891
1892	static void sysc_pre_reset_quirk_i2c(struct sysc *ddata)
1893	{
1894	sysc_clk_quirk_i2c(ddata, false);
1895	}
1896
1897	static void sysc_post_reset_quirk_i2c(struct sysc *ddata)
1898	{
1899	sysc_clk_quirk_i2c(ddata, true);
1900	}
1901
1902	/* RTC on am3 and 4 needs to be unlocked and locked for sysconfig */
1903	static void sysc_quirk_rtc(struct sysc *ddata, bool lock)
1904	{
1905	u32 val, kick0_val = 0, kick1_val = 0;
1906	unsigned long flags;
1907	int error;
1908
1909	if (!lock) {
1910	kick0_val = 0x83e70b13;
1911	kick1_val = 0x95a4f1e0;
1912	}
1913
1914	local_irq_save(flags);
1915	/* RTC_STATUS BUSY bit may stay active for 1/32768 seconds (~30 usec) */
1916	error = readl_poll_timeout_atomic(ddata->module_va + 0x44, val,
1917	!(val & BIT(0)), 100, 50);
1918	if (error)
1919	dev_warn(ddata->dev, "rtc busy timeout\n");
1920	/* Now we have ~15 microseconds to read/write various registers */
1921	sysc_write(ddata, 0x6c, kick0_val);
1922	sysc_write(ddata, 0x70, kick1_val);
1923	local_irq_restore(flags);
1924	}
1925
1926	static void sysc_module_unlock_quirk_rtc(struct sysc *ddata)
1927	{
1928	sysc_quirk_rtc(ddata, false);
1929	}
1930
1931	static void sysc_module_lock_quirk_rtc(struct sysc *ddata)
1932	{
1933	sysc_quirk_rtc(ddata, true);
1934	}
1935
1936	/* OTG omap2430 glue layer up to omap4 needs OTG_FORCESTDBY configured */
1937	static void sysc_module_enable_quirk_otg(struct sysc *ddata)
1938	{
1939	int offset = 0x414; /* OTG_FORCESTDBY */
1940
1941	sysc_write(ddata, offset, 0);
1942	}
1943
1944	static void sysc_module_disable_quirk_otg(struct sysc *ddata)
1945	{
1946	int offset = 0x414; /* OTG_FORCESTDBY */
1947	u32 val = BIT(0); /* ENABLEFORCE */
1948
1949	sysc_write(ddata, offset, val);
1950	}
1951
1952	/* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */
1953	static void sysc_module_enable_quirk_sgx(struct sysc *ddata)
1954	{
1955	int offset = 0xff08; /* OCP_DEBUG_CONFIG */
1956	u32 val = BIT(31); /* THALIA_INT_BYPASS */
1957
1958	sysc_write(ddata, offset, val);
1959	}
1960
1961	/* Watchdog timer needs a disable sequence after reset */
1962	static void sysc_reset_done_quirk_wdt(struct sysc *ddata)
1963	{
1964	int wps, spr, error;
1965	u32 val;
1966
1967	wps = 0x34;
1968	spr = 0x48;
1969
1970	sysc_write(ddata, spr, 0xaaaa);
1971	error = readl_poll_timeout(ddata->module_va + wps, val,
1972	!(val & 0x10), 100,
1973	MAX_MODULE_SOFTRESET_WAIT);
1974	if (error)
1975	dev_warn(ddata->dev, "wdt disable step1 failed\n");
1976
1977	sysc_write(ddata, spr, 0x5555);
1978	error = readl_poll_timeout(ddata->module_va + wps, val,
1979	!(val & 0x10), 100,
1980	MAX_MODULE_SOFTRESET_WAIT);
1981	if (error)
1982	dev_warn(ddata->dev, "wdt disable step2 failed\n");
1983	}
1984
1985	/* PRUSS needs to set MSTANDBY_INIT inorder to idle properly */
1986	static void sysc_module_disable_quirk_pruss(struct sysc *ddata)
1987	{
1988	u32 reg;
1989
1990	reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1991	reg \|= SYSC_PRUSS_STANDBY_INIT;
1992	sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
1993	}
1994
1995	static void sysc_module_enable_quirk_pruss(struct sysc *ddata)
1996	{
1997	u32 reg;
1998
1999	reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
2000
2001	/*
2002	* Clearing the SYSC_PRUSS_STANDBY_INIT bit - Updates OCP master
2003	* port configuration to enable memory access outside of the
2004	* PRU-ICSS subsystem.
2005	*/
2006	reg &= (~SYSC_PRUSS_STANDBY_INIT);
2007	sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
2008	}
2009
2010	static void sysc_init_module_quirks(struct sysc *ddata)
2011	{
2012	if (ddata->legacy_mode \|\| !ddata->name)
2013	return;
2014
2015	if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) {
2016	ddata->pre_reset_quirk = sysc_pre_reset_quirk_hdq1w;
2017
2018	return;
2019	}
2020
2021	#ifdef CONFIG_OMAP_GPMC_DEBUG
2022	if (ddata->cfg.quirks & SYSC_QUIRK_GPMC_DEBUG) {
2023	ddata->cfg.quirks \|= SYSC_QUIRK_NO_RESET_ON_INIT;
2024
2025	return;
2026	}
2027	#endif
2028
2029	if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) {
2030	ddata->pre_reset_quirk = sysc_pre_reset_quirk_i2c;
2031	ddata->post_reset_quirk = sysc_post_reset_quirk_i2c;
2032
2033	return;
2034	}
2035
2036	if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS)
2037	ddata->module_enable_quirk = sysc_module_enable_quirk_aess;
2038
2039	if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_DSS_RESET)
2040	ddata->pre_reset_quirk = sysc_pre_reset_quirk_dss;
2041
2042	if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_RTC_UNLOCK) {
2043	ddata->module_unlock_quirk = sysc_module_unlock_quirk_rtc;
2044	ddata->module_lock_quirk = sysc_module_lock_quirk_rtc;
2045
2046	return;
2047	}
2048
2049	if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_OTG) {
2050	ddata->module_enable_quirk = sysc_module_enable_quirk_otg;
2051	ddata->module_disable_quirk = sysc_module_disable_quirk_otg;
2052	}
2053
2054	if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX)
2055	ddata->module_enable_quirk = sysc_module_enable_quirk_sgx;
2056
2057	if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) {
2058	ddata->reset_done_quirk = sysc_reset_done_quirk_wdt;
2059	ddata->module_disable_quirk = sysc_reset_done_quirk_wdt;
2060	}
2061
2062	if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_PRUSS) {
2063	ddata->module_enable_quirk = sysc_module_enable_quirk_pruss;
2064	ddata->module_disable_quirk = sysc_module_disable_quirk_pruss;
2065	}
2066	}
2067
2068	static int sysc_clockdomain_init(struct sysc *ddata)
2069	{
2070	struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2071	struct clk fck = NULL, ick = NULL;
2072	int error;
2073
2074	if (!pdata \|\| !pdata->init_clockdomain)
2075	return 0;
2076
2077	switch (ddata->nr_clocks) {
2078	case 2:
2079	ick = ddata->clocks[SYSC_ICK];
2080	fallthrough;
2081	case 1:
2082	fck = ddata->clocks[SYSC_FCK];
2083	break;
2084	case 0:
2085	return 0;
2086	}
2087
2088	error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie);
2089	if (!error \|\| error == -ENODEV)
2090	return 0;
2091
2092	return error;
2093	}
2094
2095	/*
2096	* Note that pdata->init_module() typically does a reset first. After
2097	* pdata->init_module() is done, PM runtime can be used for the interconnect
2098	* target module.
2099	*/
2100	static int sysc_legacy_init(struct sysc *ddata)
2101	{
2102	struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2103	int error;
2104
2105	if (!pdata \|\| !pdata->init_module)
2106	return 0;
2107
2108	error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie);
2109	if (error == -EEXIST)
2110	error = 0;
2111
2112	return error;
2113	}
2114
2115	/*
2116	* Note that the caller must ensure the interconnect target module is enabled
2117	* before calling reset. Otherwise reset will not complete.
2118	*/
2119	static int sysc_reset(struct sysc *ddata)
2120	{
2121	int sysc_offset, sysc_val, error;
2122	u32 sysc_mask;
2123
2124	sysc_offset = ddata->offsets[SYSC_SYSCONFIG];
2125
2126	if (ddata->legacy_mode \|\|
2127	ddata->cap->regbits->srst_shift < 0)
2128	return 0;
2129
2130	sysc_mask = BIT(ddata->cap->regbits->srst_shift);
2131
2132	if (ddata->pre_reset_quirk)
2133	ddata->pre_reset_quirk(ddata);
2134
2135	if (sysc_offset >= 0) {
2136	sysc_val = sysc_read_sysconfig(ddata);
2137	sysc_val \|= sysc_mask;
2138	sysc_write(ddata, sysc_offset, sysc_val);
2139
2140	/*
2141	* Some devices need a delay before reading registers
2142	* after reset. Presumably a srst_udelay is not needed
2143	* for devices that use a rstctrl register reset.
2144	*/
2145	if (ddata->cfg.srst_udelay)
2146	fsleep(ddata->cfg.srst_udelay);
2147
2148	/*
2149	* Flush posted write. For devices needing srst_udelay
2150	* this should trigger an interconnect error if the
2151	* srst_udelay value is needed but not configured.
2152	*/
2153	sysc_val = sysc_read_sysconfig(ddata);
2154	}
2155
2156	if (ddata->post_reset_quirk)
2157	ddata->post_reset_quirk(ddata);
2158
2159	error = sysc_wait_softreset(ddata);
2160	if (error)
2161	dev_warn(ddata->dev, "OCP softreset timed out\n");
2162
2163	if (ddata->reset_done_quirk)
2164	ddata->reset_done_quirk(ddata);
2165
2166	return error;
2167	}
2168
2169	/*
2170	* At this point the module is configured enough to read the revision but
2171	* module may not be completely configured yet to use PM runtime. Enable
2172	* all clocks directly during init to configure the quirks needed for PM
2173	* runtime based on the revision register.
2174	*/
2175	static int sysc_init_module(struct sysc *ddata)
2176	{
2177	bool rstctrl_deasserted = false;
2178	int error = sysc_clockdomain_init(ddata);
2179
2180	if (error)
2181	return error;
2182
2183	sysc_clkdm_deny_idle(ddata);
2184
2185	/*
2186	* Always enable clocks. The bootloader may or may not have enabled
2187	* the related clocks.
2188	*/
2189	error = sysc_enable_opt_clocks(ddata);
2190	if (error)
2191	return error;
2192
2193	error = sysc_enable_main_clocks(ddata);
2194	if (error)
2195	goto err_opt_clocks;
2196
2197	if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) {
2198	error = reset_control_deassert(ddata->rsts);
2199	if (error)
2200	goto err_main_clocks;
2201	rstctrl_deasserted = true;
2202	}
2203
2204	ddata->revision = sysc_read_revision(ddata);
2205	sysc_init_revision_quirks(ddata);
2206	sysc_init_module_quirks(ddata);
2207
2208	if (ddata->legacy_mode) {
2209	error = sysc_legacy_init(ddata);
2210	if (error)
2211	goto err_main_clocks;
2212	}
2213
2214	if (!ddata->legacy_mode) {
2215	error = sysc_enable_module(ddata->dev);
2216	if (error)
2217	goto err_main_clocks;
2218	}
2219
2220	if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) {
2221	error = sysc_reset(ddata);
2222	if (error)
2223	dev_err(ddata->dev, "Reset failed with %d\n", error);
2224
2225	if (error && !ddata->legacy_mode)
2226	sysc_disable_module(ddata->dev);
2227	}
2228
2229	err_main_clocks:
2230	if (error)
2231	sysc_disable_main_clocks(ddata);
2232	err_opt_clocks:
2233	/* No re-enable of clockdomain autoidle to prevent module autoidle */
2234	if (error) {
2235	sysc_disable_opt_clocks(ddata);
2236	sysc_clkdm_allow_idle(ddata);
2237	}
2238
2239	if (error && rstctrl_deasserted &&
2240	!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
2241	reset_control_assert(ddata->rsts);
2242
2243	return error;
2244	}
2245
2246	static int sysc_init_sysc_mask(struct sysc *ddata)
2247	{
2248	struct device_node *np = ddata->dev->of_node;
2249	int error;
2250	u32 val;
2251
2252	error = of_property_read_u32(np, "ti,sysc-mask", &val);
2253	if (error)
2254	return 0;
2255
2256	ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
2257
2258	return 0;
2259	}
2260
2261	static int sysc_init_idlemode(struct sysc ddata, u8 idlemodes,
2262	const char *name)
2263	{
2264	struct device_node *np = ddata->dev->of_node;
2265	u32 val;
2266
2267	of_property_for_each_u32(np, name, val) {
2268	if (val >= SYSC_NR_IDLEMODES) {
2269	dev_err(ddata->dev, "invalid idlemode: %i\n", val);
2270	return -EINVAL;
2271	}
2272	*idlemodes \|= (1 << val);
2273	}
2274
2275	return 0;
2276	}
2277
2278	static int sysc_init_idlemodes(struct sysc *ddata)
2279	{
2280	int error;
2281
2282	error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes,
2283	"ti,sysc-midle");
2284	if (error)
2285	return error;
2286
2287	error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes,
2288	"ti,sysc-sidle");
2289	if (error)
2290	return error;
2291
2292	return 0;
2293	}
2294
2295	/*
2296	* Only some devices on omap4 and later have SYSCONFIG reset done
2297	* bit. We can detect this if there is no SYSSTATUS at all, or the
2298	* SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers
2299	* have multiple bits for the child devices like OHCI and EHCI.
2300	* Depends on SYSC being parsed first.
2301	*/
2302	static int sysc_init_syss_mask(struct sysc *ddata)
2303	{
2304	struct device_node *np = ddata->dev->of_node;
2305	int error;
2306	u32 val;
2307
2308	error = of_property_read_u32(np, "ti,syss-mask", &val);
2309	if (error) {
2310	if ((ddata->cap->type == TI_SYSC_OMAP4 \|\|
2311	ddata->cap->type == TI_SYSC_OMAP4_TIMER) &&
2312	(ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
2313	ddata->cfg.quirks \|= SYSC_QUIRK_RESET_STATUS;
2314
2315	return 0;
2316	}
2317
2318	if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
2319	ddata->cfg.quirks \|= SYSC_QUIRK_RESET_STATUS;
2320
2321	ddata->cfg.syss_mask = val;
2322
2323	return 0;
2324	}
2325
2326	/*
2327	* Many child device drivers need to have fck and opt clocks available
2328	* to get the clock rate for device internal configuration etc.
2329	*/
2330	static int sysc_child_add_named_clock(struct sysc *ddata,
2331	struct device *child,
2332	const char *name)
2333	{
2334	struct clk *clk;
2335	struct clk_lookup *l;
2336	int error = 0;
2337
2338	if (!name)
2339	return 0;
2340
2341	clk = clk_get(child, name);
2342	if (!IS_ERR(clk)) {
2343	error = -EEXIST;
2344	goto put_clk;
2345	}
2346
2347	clk = clk_get(ddata->dev, name);
2348	if (IS_ERR(clk))
2349	return -ENODEV;
2350
2351	l = clkdev_create(clk, name, dev_name(child));
2352	if (!l)
2353	error = -ENOMEM;
2354	put_clk:
2355	clk_put(clk);
2356
2357	return error;
2358	}
2359
2360	static int sysc_child_add_clocks(struct sysc *ddata,
2361	struct device *child)
2362	{
2363	int i, error;
2364
2365	for (i = 0; i < ddata->nr_clocks; i++) {
2366	error = sysc_child_add_named_clock(ddata,
2367	child,
2368	ddata->clock_roles[i]);
2369	if (error && error != -EEXIST) {
2370	dev_err(ddata->dev, "could not add child clock %s: %i\n",
2371	ddata->clock_roles[i], error);
2372
2373	return error;
2374	}
2375	}
2376
2377	return 0;
2378	}
2379
2380	static const struct device_type sysc_device_type = {
2381	};
2382
2383	static struct sysc sysc_child_to_parent(struct device dev)
2384	{
2385	struct device *parent = dev->parent;
2386
2387	if (!parent \|\| parent->type != &sysc_device_type)
2388	return NULL;
2389
2390	return dev_get_drvdata(parent);
2391	}
2392
2393	static int __maybe_unused sysc_child_runtime_suspend(struct device *dev)
2394	{
2395	struct sysc *ddata;
2396	int error;
2397
2398	ddata = sysc_child_to_parent(dev);
2399
2400	error = pm_generic_runtime_suspend(dev);
2401	if (error)
2402	return error;
2403
2404	if (!ddata->enabled)
2405	return 0;
2406
2407	return sysc_runtime_suspend(ddata->dev);
2408	}
2409
2410	static int __maybe_unused sysc_child_runtime_resume(struct device *dev)
2411	{
2412	struct sysc *ddata;
2413	int error;
2414
2415	ddata = sysc_child_to_parent(dev);
2416
2417	if (!ddata->enabled) {
2418	error = sysc_runtime_resume(ddata->dev);
2419	if (error < 0)
2420	dev_err(ddata->dev,
2421	"%s error: %i\n", __func__, error);
2422	}
2423
2424	return pm_generic_runtime_resume(dev);
2425	}
2426
2427	/* Caller needs to take list_lock if ever used outside of cpu_pm */
2428	static void sysc_reinit_modules(struct sysc_soc_info *soc)
2429	{
2430	struct sysc_module *module;
2431	struct sysc *ddata;
2432
2433	list_for_each_entry(module, &sysc_soc->restored_modules, node) {
2434	ddata = module->ddata;
2435	sysc_reinit_module(ddata, ddata->enabled);
2436	}
2437	}
2438
2439	/**
2440	* sysc_context_notifier - optionally reset and restore module after idle
2441	* @nb: notifier block
2442	* @cmd: unused
2443	* @v: unused
2444	*
2445	* Some interconnect target modules need to be restored, or reset and restored
2446	* on CPU_PM CPU_PM_CLUSTER_EXIT notifier. This is needed at least for am335x
2447	* OTG and GPMC target modules even if the modules are unused.
2448	*/
2449	static int sysc_context_notifier(struct notifier_block *nb, unsigned long cmd,
2450	void *v)
2451	{
2452	struct sysc_soc_info *soc;
2453
2454	soc = container_of(nb, struct sysc_soc_info, nb);
2455
2456	switch (cmd) {
2457	case CPU_CLUSTER_PM_ENTER:
2458	break;
2459	case CPU_CLUSTER_PM_ENTER_FAILED: /* No need to restore context */
2460	break;
2461	case CPU_CLUSTER_PM_EXIT:
2462	sysc_reinit_modules(soc);
2463	break;
2464	}
2465
2466	return NOTIFY_OK;
2467	}
2468
2469	/**
2470	* sysc_add_restored - optionally add reset and restore quirk hanlling
2471	* @ddata: device data
2472	*/
2473	static void sysc_add_restored(struct sysc *ddata)
2474	{
2475	struct sysc_module *restored_module;
2476
2477	restored_module = kzalloc_obj(*restored_module);
2478	if (!restored_module)
2479	return;
2480
2481	restored_module->ddata = ddata;
2482
2483	mutex_lock(&sysc_soc->list_lock);
2484
2485	list_add(&restored_module->node, &sysc_soc->restored_modules);
2486
2487	if (sysc_soc->nb.notifier_call)
2488	goto out_unlock;
2489
2490	sysc_soc->nb.notifier_call = sysc_context_notifier;
2491	cpu_pm_register_notifier(&sysc_soc->nb);
2492
2493	out_unlock:
2494	mutex_unlock(&sysc_soc->list_lock);
2495	}
2496
2497	static int sysc_notifier_call(struct notifier_block *nb,
2498	unsigned long event, void *device)
2499	{
2500	struct device *dev = device;
2501	struct sysc *ddata;
2502	int error;
2503
2504	ddata = sysc_child_to_parent(dev);
2505	if (!ddata)
2506	return NOTIFY_DONE;
2507
2508	switch (event) {
2509	case BUS_NOTIFY_ADD_DEVICE:
2510	error = sysc_child_add_clocks(ddata, dev);
2511	if (error)
2512	return error;
2513	break;
2514	default:
2515	break;
2516	}
2517
2518	return NOTIFY_DONE;
2519	}
2520
2521	static struct notifier_block sysc_nb = {
2522	.notifier_call = sysc_notifier_call,
2523	};
2524
2525	/* Device tree configured quirks */
2526	struct sysc_dts_quirk {
2527	const char *name;
2528	u32 mask;
2529	};
2530
2531	static const struct sysc_dts_quirk sysc_dts_quirks[] = {
2532	{ .name = "ti,no-idle-on-init",
2533	.mask = SYSC_QUIRK_NO_IDLE_ON_INIT, },
2534	{ .name = "ti,no-reset-on-init",
2535	.mask = SYSC_QUIRK_NO_RESET_ON_INIT, },
2536	{ .name = "ti,no-idle",
2537	.mask = SYSC_QUIRK_NO_IDLE, },
2538	};
2539
2540	static void sysc_parse_dts_quirks(struct sysc ddata, struct device_node np,
2541	bool is_child)
2542	{
2543	int i;
2544
2545	for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) {
2546	const char *name = sysc_dts_quirks[i].name;
2547
2548	if (!of_property_present(np, name))
2549	continue;
2550
2551	ddata->cfg.quirks \|= sysc_dts_quirks[i].mask;
2552	if (is_child) {
2553	dev_warn(ddata->dev,
2554	"dts flag should be at module level for %s\n",
2555	name);
2556	}
2557	}
2558	}
2559
2560	static int sysc_init_dts_quirks(struct sysc *ddata)
2561	{
2562	struct device_node *np = ddata->dev->of_node;
2563	int error;
2564	u32 val;
2565
2566	ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
2567
2568	sysc_parse_dts_quirks(ddata, np, false);
2569	error = of_property_read_u32(np, "ti,sysc-delay-us", &val);
2570	if (!error) {
2571	if (val > 255) {
2572	dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n",
2573	val);
2574	}
2575
2576	ddata->cfg.srst_udelay = (u8)val;
2577	}
2578
2579	return 0;
2580	}
2581
2582	static void sysc_unprepare(struct sysc *ddata)
2583	{
2584	int i;
2585
2586	if (!ddata->clocks)
2587	return;
2588
2589	for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
2590	if (!IS_ERR_OR_NULL(ddata->clocks[i]))
2591	clk_unprepare(ddata->clocks[i]);
2592	}
2593	}
2594
2595	/*
2596	* Common sysc register bits found on omap2, also known as type1
2597	*/
2598	static const struct sysc_regbits sysc_regbits_omap2 = {
2599	.dmadisable_shift = -ENODEV,
2600	.midle_shift = 12,
2601	.sidle_shift = 3,
2602	.clkact_shift = 8,
2603	.emufree_shift = 5,
2604	.enwkup_shift = 2,
2605	.srst_shift = 1,
2606	.autoidle_shift = 0,
2607	};
2608
2609	static const struct sysc_capabilities sysc_omap2 = {
2610	.type = TI_SYSC_OMAP2,
2611	.sysc_mask = SYSC_OMAP2_CLOCKACTIVITY \| SYSC_OMAP2_EMUFREE \|
2612	SYSC_OMAP2_ENAWAKEUP \| SYSC_OMAP2_SOFTRESET \|
2613	SYSC_OMAP2_AUTOIDLE,
2614	.regbits = &sysc_regbits_omap2,
2615	};
2616
2617	/* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */
2618	static const struct sysc_capabilities sysc_omap2_timer = {
2619	.type = TI_SYSC_OMAP2_TIMER,
2620	.sysc_mask = SYSC_OMAP2_CLOCKACTIVITY \| SYSC_OMAP2_EMUFREE \|
2621	SYSC_OMAP2_ENAWAKEUP \| SYSC_OMAP2_SOFTRESET \|
2622	SYSC_OMAP2_AUTOIDLE,
2623	.regbits = &sysc_regbits_omap2,
2624	.mod_quirks = SYSC_QUIRK_USE_CLOCKACT,
2625	};
2626
2627	/*
2628	* SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2
2629	* with different sidle position
2630	*/
2631	static const struct sysc_regbits sysc_regbits_omap3_sham = {
2632	.dmadisable_shift = -ENODEV,
2633	.midle_shift = -ENODEV,
2634	.sidle_shift = 4,
2635	.clkact_shift = -ENODEV,
2636	.enwkup_shift = -ENODEV,
2637	.srst_shift = 1,
2638	.autoidle_shift = 0,
2639	.emufree_shift = -ENODEV,
2640	};
2641
2642	static const struct sysc_capabilities sysc_omap3_sham = {
2643	.type = TI_SYSC_OMAP3_SHAM,
2644	.sysc_mask = SYSC_OMAP2_SOFTRESET \| SYSC_OMAP2_AUTOIDLE,
2645	.regbits = &sysc_regbits_omap3_sham,
2646	};
2647
2648	/*
2649	* AES register bits found on omap3 and later, a variant of
2650	* sysc_regbits_omap2 with different sidle position
2651	*/
2652	static const struct sysc_regbits sysc_regbits_omap3_aes = {
2653	.dmadisable_shift = -ENODEV,
2654	.midle_shift = -ENODEV,
2655	.sidle_shift = 6,
2656	.clkact_shift = -ENODEV,
2657	.enwkup_shift = -ENODEV,
2658	.srst_shift = 1,
2659	.autoidle_shift = 0,
2660	.emufree_shift = -ENODEV,
2661	};
2662
2663	static const struct sysc_capabilities sysc_omap3_aes = {
2664	.type = TI_SYSC_OMAP3_AES,
2665	.sysc_mask = SYSC_OMAP2_SOFTRESET \| SYSC_OMAP2_AUTOIDLE,
2666	.regbits = &sysc_regbits_omap3_aes,
2667	};
2668
2669	/*
2670	* Common sysc register bits found on omap4, also known as type2
2671	*/
2672	static const struct sysc_regbits sysc_regbits_omap4 = {
2673	.dmadisable_shift = 16,
2674	.midle_shift = 4,
2675	.sidle_shift = 2,
2676	.clkact_shift = -ENODEV,
2677	.enwkup_shift = -ENODEV,
2678	.emufree_shift = 1,
2679	.srst_shift = 0,
2680	.autoidle_shift = -ENODEV,
2681	};
2682
2683	static const struct sysc_capabilities sysc_omap4 = {
2684	.type = TI_SYSC_OMAP4,
2685	.sysc_mask = SYSC_OMAP4_DMADISABLE \| SYSC_OMAP4_FREEEMU \|
2686	SYSC_OMAP4_SOFTRESET,
2687	.regbits = &sysc_regbits_omap4,
2688	};
2689
2690	static const struct sysc_capabilities sysc_omap4_timer = {
2691	.type = TI_SYSC_OMAP4_TIMER,
2692	.sysc_mask = SYSC_OMAP4_DMADISABLE \| SYSC_OMAP4_FREEEMU \|
2693	SYSC_OMAP4_SOFTRESET,
2694	.regbits = &sysc_regbits_omap4,
2695	};
2696
2697	/*
2698	* Common sysc register bits found on omap4, also known as type3
2699	*/
2700	static const struct sysc_regbits sysc_regbits_omap4_simple = {
2701	.dmadisable_shift = -ENODEV,
2702	.midle_shift = 2,
2703	.sidle_shift = 0,
2704	.clkact_shift = -ENODEV,
2705	.enwkup_shift = -ENODEV,
2706	.srst_shift = -ENODEV,
2707	.emufree_shift = -ENODEV,
2708	.autoidle_shift = -ENODEV,
2709	};
2710
2711	static const struct sysc_capabilities sysc_omap4_simple = {
2712	.type = TI_SYSC_OMAP4_SIMPLE,
2713	.regbits = &sysc_regbits_omap4_simple,
2714	};
2715
2716	/*
2717	* SmartReflex sysc found on omap34xx
2718	*/
2719	static const struct sysc_regbits sysc_regbits_omap34xx_sr = {
2720	.dmadisable_shift = -ENODEV,
2721	.midle_shift = -ENODEV,
2722	.sidle_shift = -ENODEV,
2723	.clkact_shift = 20,
2724	.enwkup_shift = -ENODEV,
2725	.srst_shift = -ENODEV,
2726	.emufree_shift = -ENODEV,
2727	.autoidle_shift = -ENODEV,
2728	};
2729
2730	static const struct sysc_capabilities sysc_34xx_sr = {
2731	.type = TI_SYSC_OMAP34XX_SR,
2732	.sysc_mask = SYSC_OMAP2_CLOCKACTIVITY,
2733	.regbits = &sysc_regbits_omap34xx_sr,
2734	.mod_quirks = SYSC_QUIRK_USE_CLOCKACT \| SYSC_QUIRK_UNCACHED,
2735	};
2736
2737	/*
2738	* SmartReflex sysc found on omap36xx and later
2739	*/
2740	static const struct sysc_regbits sysc_regbits_omap36xx_sr = {
2741	.dmadisable_shift = -ENODEV,
2742	.midle_shift = -ENODEV,
2743	.sidle_shift = 24,
2744	.clkact_shift = -ENODEV,
2745	.enwkup_shift = 26,
2746	.srst_shift = -ENODEV,
2747	.emufree_shift = -ENODEV,
2748	.autoidle_shift = -ENODEV,
2749	};
2750
2751	static const struct sysc_capabilities sysc_36xx_sr = {
2752	.type = TI_SYSC_OMAP36XX_SR,
2753	.sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP,
2754	.regbits = &sysc_regbits_omap36xx_sr,
2755	.mod_quirks = SYSC_QUIRK_UNCACHED,
2756	};
2757
2758	static const struct sysc_capabilities sysc_omap4_sr = {
2759	.type = TI_SYSC_OMAP4_SR,
2760	.regbits = &sysc_regbits_omap36xx_sr,
2761	};
2762
2763	/*
2764	* McASP register bits found on omap4 and later
2765	*/
2766	static const struct sysc_regbits sysc_regbits_omap4_mcasp = {
2767	.dmadisable_shift = -ENODEV,
2768	.midle_shift = -ENODEV,
2769	.sidle_shift = 0,
2770	.clkact_shift = -ENODEV,
2771	.enwkup_shift = -ENODEV,
2772	.srst_shift = -ENODEV,
2773	.emufree_shift = -ENODEV,
2774	.autoidle_shift = -ENODEV,
2775	};
2776
2777	static const struct sysc_capabilities sysc_omap4_mcasp = {
2778	.type = TI_SYSC_OMAP4_MCASP,
2779	.regbits = &sysc_regbits_omap4_mcasp,
2780	.mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2781	};
2782
2783	/*
2784	* McASP found on dra7 and later
2785	*/
2786	static const struct sysc_capabilities sysc_dra7_mcasp = {
2787	.type = TI_SYSC_OMAP4_SIMPLE,
2788	.regbits = &sysc_regbits_omap4_simple,
2789	.mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2790	};
2791
2792	/*
2793	* FS USB host found on omap4 and later
2794	*/
2795	static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = {
2796	.dmadisable_shift = -ENODEV,
2797	.midle_shift = -ENODEV,
2798	.sidle_shift = 24,
2799	.clkact_shift = -ENODEV,
2800	.enwkup_shift = 26,
2801	.srst_shift = -ENODEV,
2802	.emufree_shift = -ENODEV,
2803	.autoidle_shift = -ENODEV,
2804	};
2805
2806	static const struct sysc_capabilities sysc_omap4_usb_host_fs = {
2807	.type = TI_SYSC_OMAP4_USB_HOST_FS,
2808	.sysc_mask = SYSC_OMAP2_ENAWAKEUP,
2809	.regbits = &sysc_regbits_omap4_usb_host_fs,
2810	};
2811
2812	static const struct sysc_regbits sysc_regbits_dra7_mcan = {
2813	.dmadisable_shift = -ENODEV,
2814	.midle_shift = -ENODEV,
2815	.sidle_shift = -ENODEV,
2816	.clkact_shift = -ENODEV,
2817	.enwkup_shift = 4,
2818	.srst_shift = 0,
2819	.emufree_shift = -ENODEV,
2820	.autoidle_shift = -ENODEV,
2821	};
2822
2823	static const struct sysc_capabilities sysc_dra7_mcan = {
2824	.type = TI_SYSC_DRA7_MCAN,
2825	.sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP \| SYSC_OMAP4_SOFTRESET,
2826	.regbits = &sysc_regbits_dra7_mcan,
2827	.mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED,
2828	};
2829
2830	/*
2831	* PRUSS found on some AM33xx, AM437x and AM57xx SoCs
2832	*/
2833	static const struct sysc_capabilities sysc_pruss = {
2834	.type = TI_SYSC_PRUSS,
2835	.sysc_mask = SYSC_PRUSS_STANDBY_INIT \| SYSC_PRUSS_SUB_MWAIT,
2836	.regbits = &sysc_regbits_omap4_simple,
2837	.mod_quirks = SYSC_MODULE_QUIRK_PRUSS,
2838	};
2839
2840	static int sysc_init_pdata(struct sysc *ddata)
2841	{
2842	struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2843	struct ti_sysc_module_data *mdata;
2844
2845	if (!pdata)
2846	return 0;
2847
2848	mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL);
2849	if (!mdata)
2850	return -ENOMEM;
2851
2852	if (ddata->legacy_mode) {
2853	mdata->name = ddata->legacy_mode;
2854	mdata->module_pa = ddata->module_pa;
2855	mdata->module_size = ddata->module_size;
2856	mdata->offsets = ddata->offsets;
2857	mdata->nr_offsets = SYSC_MAX_REGS;
2858	mdata->cap = ddata->cap;
2859	mdata->cfg = &ddata->cfg;
2860	}
2861
2862	ddata->mdata = mdata;
2863
2864	return 0;
2865	}
2866
2867	static int sysc_init_match(struct sysc *ddata)
2868	{
2869	const struct sysc_capabilities *cap;
2870
2871	cap = of_device_get_match_data(ddata->dev);
2872	if (!cap)
2873	return -EINVAL;
2874
2875	ddata->cap = cap;
2876	if (ddata->cap)
2877	ddata->cfg.quirks \|= ddata->cap->mod_quirks;
2878
2879	return 0;
2880	}
2881
2882	static void ti_sysc_idle(struct work_struct *work)
2883	{
2884	struct sysc *ddata;
2885
2886	ddata = container_of(work, struct sysc, idle_work.work);
2887
2888	/*
2889	* One time decrement of clock usage counts if left on from init.
2890	* Note that we disable opt clocks unconditionally in this case
2891	* as they are enabled unconditionally during init without
2892	* considering sysc_opt_clks_needed() at that point.
2893	*/
2894	if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE \|
2895	SYSC_QUIRK_NO_IDLE_ON_INIT)) {
2896	sysc_disable_main_clocks(ddata);
2897	sysc_disable_opt_clocks(ddata);
2898	sysc_clkdm_allow_idle(ddata);
2899	}
2900
2901	/* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */
2902	if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)
2903	return;
2904
2905	/*
2906	* Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT
2907	* and SYSC_QUIRK_NO_RESET_ON_INIT
2908	*/
2909	if (pm_runtime_active(ddata->dev))
2910	pm_runtime_put_sync(ddata->dev);
2911	}
2912
2913	/*
2914	* SoC model and features detection. Only needed for SoCs that need
2915	* special handling for quirks, no need to list others.
2916	*/
2917	static const struct soc_device_attribute sysc_soc_match[] = {
2918	SOC_FLAG("OMAP242*", SOC_2420),
2919	SOC_FLAG("OMAP243*", SOC_2430),
2920	SOC_FLAG("AM33*", SOC_AM33),
2921	SOC_FLAG("AM35*", SOC_AM35),
2922	SOC_FLAG("OMAP3[45]*", SOC_3430),
2923	SOC_FLAG("OMAP3[67]*", SOC_3630),
2924	SOC_FLAG("OMAP443*", SOC_4430),
2925	SOC_FLAG("OMAP446*", SOC_4460),
2926	SOC_FLAG("OMAP447*", SOC_4470),
2927	SOC_FLAG("OMAP54*", SOC_5430),
2928	SOC_FLAG("AM433", SOC_AM3),
2929	SOC_FLAG("AM43*", SOC_AM4),
2930	SOC_FLAG("DRA7*", SOC_DRA7),
2931
2932	{ /* sentinel */ }
2933	};
2934
2935	/*
2936	* List of SoCs variants with disabled features. By default we assume all
2937	* devices in the device tree are available so no need to list those SoCs.
2938	*/
2939	static const struct soc_device_attribute sysc_soc_feat_match[] = {
2940	/* OMAP3430/3530 and AM3517 variants with some accelerators disabled */
2941	SOC_FLAG("AM3505", DIS_SGX),
2942	SOC_FLAG("OMAP3525", DIS_SGX),
2943	SOC_FLAG("OMAP3515", DIS_IVA \| DIS_SGX),
2944	SOC_FLAG("OMAP3503", DIS_ISP \| DIS_IVA \| DIS_SGX),
2945
2946	/* OMAP3630/DM3730 variants with some accelerators disabled */
2947	SOC_FLAG("AM3703", DIS_IVA \| DIS_SGX),
2948	SOC_FLAG("DM3725", DIS_SGX),
2949	SOC_FLAG("OMAP3611", DIS_ISP \| DIS_IVA \| DIS_SGX),
2950	SOC_FLAG("OMAP3615/AM3715", DIS_IVA),
2951	SOC_FLAG("OMAP3621", DIS_ISP),
2952
2953	{ /* sentinel */ }
2954	};
2955
2956	static int sysc_add_disabled(unsigned long base)
2957	{
2958	struct sysc_address *disabled_module;
2959
2960	disabled_module = kzalloc_obj(*disabled_module);
2961	if (!disabled_module)
2962	return -ENOMEM;
2963
2964	disabled_module->base = base;
2965
2966	mutex_lock(&sysc_soc->list_lock);
2967	list_add(&disabled_module->node, &sysc_soc->disabled_modules);
2968	mutex_unlock(&sysc_soc->list_lock);
2969
2970	return 0;
2971	}
2972
2973	/*
2974	* One time init to detect the booted SoC, disable unavailable features
2975	* and initialize list for optional cpu_pm notifier.
2976	*
2977	* Note that we initialize static data shared across all ti-sysc instances
2978	* so ddata is only used for SoC type. This can be called from module_init
2979	* once we no longer need to rely on platform data.
2980	*/
2981	static int sysc_init_static_data(struct sysc *ddata)
2982	{
2983	const struct soc_device_attribute *match;
2984	struct ti_sysc_platform_data *pdata;
2985	unsigned long features = 0;
2986	struct device_node *np;
2987
2988	if (sysc_soc)
2989	return 0;
2990
2991	sysc_soc = kzalloc_obj(*sysc_soc);
2992	if (!sysc_soc)
2993	return -ENOMEM;
2994
2995	mutex_init(&sysc_soc->list_lock);
2996	INIT_LIST_HEAD(&sysc_soc->disabled_modules);
2997	INIT_LIST_HEAD(&sysc_soc->restored_modules);
2998	sysc_soc->general_purpose = true;
2999
3000	pdata = dev_get_platdata(ddata->dev);
3001	if (pdata && pdata->soc_type_gp)
3002	sysc_soc->general_purpose = pdata->soc_type_gp();
3003
3004	match = soc_device_match(sysc_soc_match);
3005	if (match && match->data)
3006	sysc_soc->soc = (enum sysc_soc)(uintptr_t)match->data;
3007
3008	/*
3009	* Check and warn about possible old incomplete dtb. We now want to see
3010	* simple-pm-bus instead of simple-bus in the dtb for genpd using SoCs.
3011	*/
3012	switch (sysc_soc->soc) {
3013	case SOC_AM3:
3014	case SOC_AM4:
3015	case SOC_4430 ... SOC_4470:
3016	case SOC_5430:
3017	case SOC_DRA7:
3018	np = of_find_node_by_path("/ocp");
3019	WARN_ONCE(np && of_device_is_compatible(np, "simple-bus"),
3020	"ti-sysc: Incomplete old dtb, please update\n");
3021	break;
3022	default:
3023	break;
3024	}
3025
3026	/* Ignore devices that are not available on HS and EMU SoCs */
3027	if (!sysc_soc->general_purpose) {
3028	switch (sysc_soc->soc) {
3029	case SOC_3430 ... SOC_3630:
3030	sysc_add_disabled(0x48304000); /* timer12 */
3031	break;
3032	case SOC_AM3:
3033	sysc_add_disabled(0x48310000); /* rng */
3034	break;
3035	default:
3036	break;
3037	}
3038	}
3039
3040	match = soc_device_match(sysc_soc_feat_match);
3041	if (!match)
3042	return 0;
3043
3044	if (match->data)
3045	features = (unsigned long)match->data;
3046
3047	/*
3048	* Add disabled devices to the list based on the module base.
3049	* Note that this must be done before we attempt to access the
3050	* device and have module revision checks working.
3051	*/
3052	if (features & DIS_ISP)
3053	sysc_add_disabled(0x480bd400);
3054	if (features & DIS_IVA)
3055	sysc_add_disabled(0x5d000000);
3056	if (features & DIS_SGX)
3057	sysc_add_disabled(0x50000000);
3058
3059	return 0;
3060	}
3061
3062	static void sysc_cleanup_static_data(void)
3063	{
3064	struct sysc_module *restored_module;
3065	struct sysc_address *disabled_module;
3066	struct list_head pos, tmp;
3067
3068	if (!sysc_soc)
3069	return;
3070
3071	if (sysc_soc->nb.notifier_call)
3072	cpu_pm_unregister_notifier(&sysc_soc->nb);
3073
3074	mutex_lock(&sysc_soc->list_lock);
3075	list_for_each_safe(pos, tmp, &sysc_soc->restored_modules) {
3076	restored_module = list_entry(pos, struct sysc_module, node);
3077	list_del(pos);
3078	kfree(restored_module);
3079	}
3080	list_for_each_safe(pos, tmp, &sysc_soc->disabled_modules) {
3081	disabled_module = list_entry(pos, struct sysc_address, node);
3082	list_del(pos);
3083	kfree(disabled_module);
3084	}
3085	mutex_unlock(&sysc_soc->list_lock);
3086	}
3087
3088	static int sysc_check_disabled_devices(struct sysc *ddata)
3089	{
3090	struct sysc_address *disabled_module;
3091	int error = 0;
3092
3093	mutex_lock(&sysc_soc->list_lock);
3094	list_for_each_entry(disabled_module, &sysc_soc->disabled_modules, node) {
3095	if (ddata->module_pa == disabled_module->base) {
3096	dev_dbg(ddata->dev, "module disabled for this SoC\n");
3097	error = -ENODEV;
3098	break;
3099	}
3100	}
3101	mutex_unlock(&sysc_soc->list_lock);
3102
3103	return error;
3104	}
3105
3106	/*
3107	* Ignore timers tagged with no-reset and no-idle. These are likely in use,
3108	* for example by drivers/clocksource/timer-ti-dm-systimer.c. If more checks
3109	* are needed, we could also look at the timer register configuration.
3110	*/
3111	static int sysc_check_active_timer(struct sysc *ddata)
3112	{
3113	int error;
3114
3115	if (ddata->cap->type != TI_SYSC_OMAP2_TIMER &&
3116	ddata->cap->type != TI_SYSC_OMAP4_TIMER)
3117	return 0;
3118
3119	/*
3120	* Quirk for omap3 beagleboard revision A to B4 to use gpt12.
3121	* Revision C and later are fixed with commit 23885389dbbb ("ARM:
3122	* dts: Fix timer regression for beagleboard revision c"). This all
3123	* can be dropped if we stop supporting old beagleboard revisions
3124	* A to B4 at some point.
3125	*/
3126	switch (sysc_soc->soc) {
3127	case SOC_AM33:
3128	case SOC_3430:
3129	case SOC_AM35:
3130	error = -ENXIO;
3131	break;
3132	default:
3133	error = -EBUSY;
3134	}
3135
3136	if ((ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) &&
3137	(ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE))
3138	return error;
3139
3140	return 0;
3141	}
3142
3143	static const struct of_device_id sysc_match_table[] = {
3144	{ .compatible = "simple-bus", },
3145	{ /* sentinel */ },
3146	};
3147
3148	static int sysc_probe(struct platform_device *pdev)
3149	{
3150	struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev);
3151	struct sysc *ddata;
3152	int error;
3153
3154	ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
3155	if (!ddata)
3156	return -ENOMEM;
3157
3158	ddata->offsets[SYSC_REVISION] = -ENODEV;
3159	ddata->offsets[SYSC_SYSCONFIG] = -ENODEV;
3160	ddata->offsets[SYSC_SYSSTATUS] = -ENODEV;
3161	ddata->dev = &pdev->dev;
3162	platform_set_drvdata(pdev, ddata);
3163
3164	error = sysc_init_static_data(ddata);
3165	if (error)
3166	return error;
3167
3168	error = sysc_init_match(ddata);
3169	if (error)
3170	return error;
3171
3172	error = sysc_init_dts_quirks(ddata);
3173	if (error)
3174	return error;
3175
3176	error = sysc_map_and_check_registers(ddata);
3177	if (error)
3178	return error;
3179
3180	error = sysc_init_sysc_mask(ddata);
3181	if (error)
3182	return error;
3183
3184	error = sysc_init_idlemodes(ddata);
3185	if (error)
3186	return error;
3187
3188	error = sysc_init_syss_mask(ddata);
3189	if (error)
3190	return error;
3191
3192	error = sysc_init_pdata(ddata);
3193	if (error)
3194	return error;
3195
3196	sysc_init_early_quirks(ddata);
3197
3198	error = sysc_check_disabled_devices(ddata);
3199	if (error)
3200	return error;
3201
3202	error = sysc_check_active_timer(ddata);
3203	if (error == -ENXIO)
3204	ddata->reserved = true;
3205	else if (error)
3206	return error;
3207
3208	error = sysc_get_clocks(ddata);
3209	if (error)
3210	return error;
3211
3212	error = sysc_init_resets(ddata);
3213	if (error)
3214	goto unprepare;
3215
3216	error = sysc_init_module(ddata);
3217	if (error)
3218	goto unprepare;
3219
3220	pm_runtime_enable(ddata->dev);
3221	error = pm_runtime_resume_and_get(ddata->dev);
3222	if (error < 0) {
3223	pm_runtime_disable(ddata->dev);
3224	goto unprepare;
3225	}
3226
3227	/* Balance use counts as PM runtime should have enabled these all */
3228	if (!(ddata->cfg.quirks &
3229	(SYSC_QUIRK_NO_IDLE \| SYSC_QUIRK_NO_IDLE_ON_INIT))) {
3230	sysc_disable_main_clocks(ddata);
3231	sysc_disable_opt_clocks(ddata);
3232	sysc_clkdm_allow_idle(ddata);
3233	}
3234
3235	if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
3236	reset_control_assert(ddata->rsts);
3237
3238	sysc_show_registers(ddata);
3239
3240	ddata->dev->type = &sysc_device_type;
3241
3242	if (!ddata->reserved) {
3243	error = of_platform_populate(ddata->dev->of_node,
3244	sysc_match_table,
3245	pdata ? pdata->auxdata : NULL,
3246	ddata->dev);
3247	if (error)
3248	goto err;
3249	}
3250
3251	INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle);
3252
3253	/* At least earlycon won't survive without deferred idle */
3254	if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE \|
3255	SYSC_QUIRK_NO_IDLE_ON_INIT \|
3256	SYSC_QUIRK_NO_RESET_ON_INIT)) {
3257	schedule_delayed_work(&ddata->idle_work, 3000);
3258	} else {
3259	pm_runtime_put(&pdev->dev);
3260	}
3261
3262	if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_CTX_LOST)
3263	sysc_add_restored(ddata);
3264
3265	return 0;
3266
3267	err:
3268	pm_runtime_put_sync(&pdev->dev);
3269	pm_runtime_disable(&pdev->dev);
3270	unprepare:
3271	sysc_unprepare(ddata);
3272
3273	return error;
3274	}
3275
3276	static void sysc_remove(struct platform_device *pdev)
3277	{
3278	struct sysc *ddata = platform_get_drvdata(pdev);
3279	int error;
3280
3281	/* Device can still be enabled, see deferred idle quirk in probe */
3282	if (cancel_delayed_work_sync(&ddata->idle_work))
3283	ti_sysc_idle(&ddata->idle_work.work);
3284
3285	error = pm_runtime_resume_and_get(ddata->dev);
3286	if (error < 0) {
3287	pm_runtime_disable(ddata->dev);
3288	goto unprepare;
3289	}
3290
3291	of_platform_depopulate(&pdev->dev);
3292
3293	pm_runtime_put_sync(&pdev->dev);
3294	pm_runtime_disable(&pdev->dev);
3295
3296	if (!reset_control_status(ddata->rsts))
3297	reset_control_assert(ddata->rsts);
3298
3299	unprepare:
3300	sysc_unprepare(ddata);
3301	}
3302
3303	static const struct of_device_id sysc_match[] = {
3304	{ .compatible = "ti,sysc-omap2", .data = &sysc_omap2, },
3305	{ .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, },
3306	{ .compatible = "ti,sysc-omap4", .data = &sysc_omap4, },
3307	{ .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, },
3308	{ .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, },
3309	{ .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, },
3310	{ .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, },
3311	{ .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, },
3312	{ .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, },
3313	{ .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, },
3314	{ .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, },
3315	{ .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, },
3316	{ .compatible = "ti,sysc-usb-host-fs",
3317	.data = &sysc_omap4_usb_host_fs, },
3318	{ .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, },
3319	{ .compatible = "ti,sysc-pruss", .data = &sysc_pruss, },
3320	{ },
3321	};
3322	MODULE_DEVICE_TABLE(of, sysc_match);
3323
3324	static struct platform_driver sysc_driver = {
3325	.probe = sysc_probe,
3326	.remove = sysc_remove,
3327	.driver = {
3328	.name = "ti-sysc",
3329	.of_match_table = sysc_match,
3330	.pm = &sysc_pm_ops,
3331	},
3332	};
3333
3334	static int __init sysc_init(void)
3335	{
3336	bus_register_notifier(&platform_bus_type, &sysc_nb);
3337
3338	return platform_driver_register(&sysc_driver);
3339	}
3340	module_init(sysc_init);
3341
3342	static void __exit sysc_exit(void)
3343	{
3344	bus_unregister_notifier(&platform_bus_type, &sysc_nb);
3345	platform_driver_unregister(&sysc_driver);
3346	sysc_cleanup_static_data();
3347	}
3348	module_exit(sysc_exit);
3349
3350	MODULE_DESCRIPTION("TI sysc interconnect target driver");
3351	MODULE_LICENSE("GPL v2");