| 1 | |
| 2 | |
| 3 | * Clock driver for Hi655x
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| 4 | *
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| 5 | * Copyright (c) 2017, Linaro Ltd.
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| 6 | *
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| 7 | * Author: Daniel Lezcano <[email protected]>
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| 8 |
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| 9 | #include <linux/clk-provider.h>
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| 10 | #include <linux/module.h>
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| 11 | #include <linux/platform_device.h>
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| 12 | #include <linux/regmap.h>
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| 13 | #include <linux/slab.h>
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| 14 | #include <linux/mfd/core.h>
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| 15 | #include <linux/mfd/hi655x-pmic.h>
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| 16 |
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| 17 | #define HI655X_CLK_BASE HI655X_BUS_ADDR(0x1c)
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| 18 | #define HI655X_CLK_SET BIT(6)
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| 19 |
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| 20 | struct hi655x_clk {
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| 21 | struct hi655x_pmic *hi655x;
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| 22 | struct clk_hw clk_hw;
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| 23 | };
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| 24 |
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| 25 | static unsigned long hi655x_clk_recalc_rate(struct clk_hw *hw,
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| 26 | unsigned long parent_rate)
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| 27 | {
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| 28 | return 32768;
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| 29 | }
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| 30 |
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| 31 | static int hi655x_clk_enable(struct clk_hw *hw, bool enable)
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| 32 | {
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| 33 | struct hi655x_clk *hi655x_clk =
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| 34 | container_of(hw, struct hi655x_clk, clk_hw);
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| 35 |
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| 36 | struct hi655x_pmic *hi655x = hi655x_clk->hi655x;
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| 37 |
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| 38 | return regmap_update_bits(hi655x->regmap, HI655X_CLK_BASE,
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| 39 | HI655X_CLK_SET, enable ? HI655X_CLK_SET : 0);
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| 40 | }
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| 41 |
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| 42 | static int hi655x_clk_prepare(struct clk_hw *hw)
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| 43 | {
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| 44 | return hi655x_clk_enable(hw, true);
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| 45 | }
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| 46 |
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| 47 | static void hi655x_clk_unprepare(struct clk_hw *hw)
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| 48 | {
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| 49 | hi655x_clk_enable(hw, false);
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| 50 | }
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| 51 |
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| 52 | static int hi655x_clk_is_prepared(struct clk_hw *hw)
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| 53 | {
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| 54 | struct hi655x_clk *hi655x_clk =
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| 55 | container_of(hw, struct hi655x_clk, clk_hw);
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| 56 | struct hi655x_pmic *hi655x = hi655x_clk->hi655x;
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| 57 | int ret;
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| 58 | uint32_t val;
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| 59 |
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| 60 | ret = regmap_read(hi655x->regmap, HI655X_CLK_BASE, &val);
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| 61 | if (ret < 0)
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| 62 | return ret;
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| 63 |
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| 64 | return val & HI655X_CLK_BASE;
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| 65 | }
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| 66 |
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| 67 | static const struct clk_ops hi655x_clk_ops = {
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| 68 | .prepare = hi655x_clk_prepare,
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| 69 | .unprepare = hi655x_clk_unprepare,
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| 70 | .is_prepared = hi655x_clk_is_prepared,
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| 71 | .recalc_rate = hi655x_clk_recalc_rate,
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| 72 | };
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| 73 |
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| 74 | static int hi655x_clk_probe(struct platform_device *pdev)
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| 75 | {
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| 76 | struct device *parent = pdev->dev.parent;
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| 77 | struct hi655x_pmic *hi655x = dev_get_drvdata(parent);
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| 78 | struct hi655x_clk *hi655x_clk;
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| 79 | const char *clk_name = "hi655x-clk";
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| 80 | struct clk_init_data init = {
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| 81 | .name = clk_name,
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| 82 | .ops = &hi655x_clk_ops
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| 83 | };
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| 84 | int ret;
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| 85 |
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| 86 | hi655x_clk = devm_kzalloc(&pdev->dev, sizeof(*hi655x_clk), GFP_KERNEL);
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| 87 | if (!hi655x_clk)
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| 88 | return -ENOMEM;
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| 89 |
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| 90 | of_property_read_string_index(parent->of_node, "clock-output-names",
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| 91 | 0, &clk_name);
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| 92 |
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| 93 | hi655x_clk->clk_hw.init = &init;
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| 94 | hi655x_clk->hi655x = hi655x;
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| 95 |
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| 96 | platform_set_drvdata(pdev, hi655x_clk);
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| 97 |
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| 98 | ret = devm_clk_hw_register(&pdev->dev, &hi655x_clk->clk_hw);
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| 99 | if (ret)
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| 100 | return ret;
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| 101 |
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| 102 | return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_simple_get,
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| 103 | &hi655x_clk->clk_hw);
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| 104 | }
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| 105 |
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| 106 | static struct platform_driver hi655x_clk_driver = {
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| 107 | .probe = hi655x_clk_probe,
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| 108 | .driver = {
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| 109 | .name = "hi655x-clk",
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| 110 | },
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| 111 | };
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| 112 |
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| 113 | module_platform_driver(hi655x_clk_driver);
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| 114 |
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| 115 | MODULE_DESCRIPTION("Clk driver for the hi655x series PMICs");
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| 116 | MODULE_AUTHOR("Daniel Lezcano <[email protected]>");
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| 117 | MODULE_LICENSE("GPL");
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| 118 | MODULE_ALIAS("platform:hi655x-clk");
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