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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * System Control and Power Interface (SCMI) Protocol based clock driver
4 *
5 * Copyright (C) 2018-2024 ARM Ltd.
6 */
7
8#include <linux/bits.h>
9#include <linux/clk-provider.h>
10#include <linux/device.h>
11#include <linux/err.h>
12#include <linux/of.h>
13#include <linux/module.h>
14#include <linux/scmi_protocol.h>
15
16#include "clk-scmi.h"
17
18const struct scmi_clk_proto_ops *scmi_proto_clk_ops;
19
20static unsigned long scmi_clk_recalc_rate(struct clk_hw *hw,
21 unsigned long parent_rate)
22{
23 int ret;
24 u64 rate;
25 struct scmi_clk *clk = to_scmi_clk(hw);
26
27 ret = scmi_proto_clk_ops->rate_get(clk->ph, clk->id, &rate);
28 if (ret)
29 return 0;
30 return rate;
31}
32
33static int scmi_clk_determine_rate(struct clk_hw *hw,
34 struct clk_rate_request *req)
35{
36 int ret;
37 struct scmi_clk *clk = to_scmi_clk(hw);
38
39 /*
40 * If we could not get a better rate scmi_clk_recalc_rate() will be
41 * called after the rate is set and we'll know what rate the clock is
42 * running at then.
43 */
44 ret = scmi_proto_clk_ops->determine_rate(clk->ph, clk->id, &req->rate);
45 if (ret)
46 return ret;
47
48 return 0;
49}
50
51static int scmi_clk_set_rate(struct clk_hw *hw, unsigned long rate,
52 unsigned long parent_rate)
53{
54 struct scmi_clk *clk = to_scmi_clk(hw);
55
56 return scmi_proto_clk_ops->rate_set(clk->ph, clk->id, rate);
57}
58
59static int scmi_clk_set_parent(struct clk_hw *hw, u8 parent_index)
60{
61 struct scmi_clk *clk = to_scmi_clk(hw);
62
63 return scmi_proto_clk_ops->parent_set(clk->ph, clk->id, parent_index);
64}
65
66static u8 scmi_clk_get_parent(struct clk_hw *hw)
67{
68 struct scmi_clk *clk = to_scmi_clk(hw);
69 u32 parent_id, p_idx;
70 int ret;
71
72 ret = scmi_proto_clk_ops->parent_get(clk->ph, clk->id, &parent_id);
73 if (ret)
74 return 0;
75
76 for (p_idx = 0; p_idx < clk->info->num_parents; p_idx++) {
77 if (clk->parent_data[p_idx].index == parent_id)
78 break;
79 }
80
81 if (p_idx == clk->info->num_parents)
82 return 0;
83
84 return p_idx;
85}
86
87static int scmi_clk_enable(struct clk_hw *hw)
88{
89 struct scmi_clk *clk = to_scmi_clk(hw);
90
91 return scmi_proto_clk_ops->enable(clk->ph, clk->id, NOT_ATOMIC);
92}
93
94static void scmi_clk_disable(struct clk_hw *hw)
95{
96 struct scmi_clk *clk = to_scmi_clk(hw);
97
98 scmi_proto_clk_ops->disable(clk->ph, clk->id, NOT_ATOMIC);
99}
100
101static int scmi_clk_atomic_enable(struct clk_hw *hw)
102{
103 struct scmi_clk *clk = to_scmi_clk(hw);
104
105 return scmi_proto_clk_ops->enable(clk->ph, clk->id, ATOMIC);
106}
107
108static void scmi_clk_atomic_disable(struct clk_hw *hw)
109{
110 struct scmi_clk *clk = to_scmi_clk(hw);
111
112 scmi_proto_clk_ops->disable(clk->ph, clk->id, ATOMIC);
113}
114
115static int __scmi_clk_is_enabled(struct clk_hw *hw, bool atomic)
116{
117 int ret;
118 bool enabled = false;
119 struct scmi_clk *clk = to_scmi_clk(hw);
120
121 ret = scmi_proto_clk_ops->state_get(clk->ph, clk->id, &enabled, atomic);
122 if (ret)
123 dev_warn(clk->dev,
124 "Failed to get state for clock ID %d\n", clk->id);
125
126 return !!enabled;
127}
128
129static int scmi_clk_atomic_is_enabled(struct clk_hw *hw)
130{
131 return __scmi_clk_is_enabled(hw, ATOMIC);
132}
133
134static int scmi_clk_is_enabled(struct clk_hw *hw)
135{
136 return __scmi_clk_is_enabled(hw, NOT_ATOMIC);
137}
138
139static int scmi_clk_get_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
140{
141 int ret;
142 u32 val;
143 struct scmi_clk *clk = to_scmi_clk(hw);
144
145 ret = scmi_proto_clk_ops->config_oem_get(clk->ph, clk->id,
146 SCMI_CLOCK_CFG_DUTY_CYCLE,
147 &val, NULL, false);
148 if (!ret) {
149 duty->num = val;
150 duty->den = 100;
151 } else {
152 dev_warn(clk->dev,
153 "Failed to get duty cycle for clock ID %d\n", clk->id);
154 }
155
156 return ret;
157}
158
159static int scmi_clk_set_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
160{
161 int ret;
162 u32 val;
163 struct scmi_clk *clk = to_scmi_clk(hw);
164
165 /* SCMI OEM Duty Cycle is expressed as a percentage */
166 val = (duty->num * 100) / duty->den;
167 ret = scmi_proto_clk_ops->config_oem_set(clk->ph, clk->id,
168 SCMI_CLOCK_CFG_DUTY_CYCLE,
169 val, false);
170 if (ret)
171 dev_warn(clk->dev,
172 "Failed to set duty cycle(%u/%u) for clock ID %d\n",
173 duty->num, duty->den, clk->id);
174
175 return ret;
176}
177
178static int scmi_clk_ops_init(struct device *dev, struct scmi_clk *sclk,
179 const struct clk_ops *scmi_ops)
180{
181 int ret;
182
183 struct clk_init_data init = {
184 .flags = CLK_GET_RATE_NOCACHE,
185 .num_parents = sclk->info->num_parents,
186 .ops = scmi_ops,
187 .name = sclk->info->name,
188 .parent_data = sclk->parent_data,
189 };
190
191 sclk->hw.init = &init;
192 ret = devm_clk_hw_register(dev, &sclk->hw);
193 if (ret)
194 return ret;
195
196 clk_hw_set_rate_range(&sclk->hw, sclk->info->min_rate,
197 sclk->info->max_rate);
198 return ret;
199}
200
201/**
202 * scmi_clk_ops_alloc() - Alloc and configure clock operations
203 * @dev: A device reference for devres
204 * @feats_key: A bitmap representing the desired clk_ops capabilities
205 *
206 * Allocate and configure a proper set of clock operations depending on the
207 * specifically required SCMI clock features.
208 *
209 * Return: A pointer to the allocated and configured clk_ops on success,
210 * or NULL on allocation failure.
211 */
212static const struct clk_ops *
213scmi_clk_ops_alloc(struct device *dev, unsigned long feats_key)
214{
215 struct scmi_clk_oem *oem_data = dev_get_drvdata(dev);
216 struct clk_ops *ops;
217
218 ops = devm_kzalloc(dev, sizeof(*ops), GFP_KERNEL);
219 if (!ops)
220 return NULL;
221 /*
222 * We can provide enable/disable/is_enabled atomic callbacks only if the
223 * underlying SCMI transport for an SCMI instance is configured to
224 * handle SCMI commands in an atomic manner.
225 *
226 * When no SCMI atomic transport support is available we instead provide
227 * only the prepare/unprepare API, as allowed by the clock framework
228 * when atomic calls are not available.
229 */
230 if (feats_key & BIT(SCMI_CLK_STATE_CTRL_SUPPORTED)) {
231 if (feats_key & BIT(SCMI_CLK_ATOMIC_SUPPORTED)) {
232 ops->enable = scmi_clk_atomic_enable;
233 ops->disable = scmi_clk_atomic_disable;
234 } else {
235 ops->prepare = scmi_clk_enable;
236 ops->unprepare = scmi_clk_disable;
237 }
238 }
239
240 if (feats_key & BIT(SCMI_CLK_ATOMIC_SUPPORTED))
241 ops->is_enabled = scmi_clk_atomic_is_enabled;
242 else
243 ops->is_prepared = scmi_clk_is_enabled;
244
245 /* Rate ops */
246 ops->recalc_rate = scmi_clk_recalc_rate;
247 ops->determine_rate = scmi_clk_determine_rate;
248 if (feats_key & BIT(SCMI_CLK_RATE_CTRL_SUPPORTED))
249 ops->set_rate = scmi_clk_set_rate;
250
251 /* Parent ops */
252 ops->get_parent = scmi_clk_get_parent;
253 if (feats_key & BIT(SCMI_CLK_PARENT_CTRL_SUPPORTED))
254 ops->set_parent = scmi_clk_set_parent;
255
256 /* Duty cycle */
257 if (feats_key & BIT(SCMI_CLK_DUTY_CYCLE_SUPPORTED)) {
258 ops->get_duty_cycle = scmi_clk_get_duty_cycle;
259 ops->set_duty_cycle = scmi_clk_set_duty_cycle;
260 }
261
262 if (oem_data && (feats_key & BIT(SCMI_CLK_EXT_OEM_SSC_SUPPORTED)))
263 ops->set_spread_spectrum = oem_data->set_spread_spectrum;
264
265 return ops;
266}
267
268/**
269 * scmi_clk_ops_select() - Select a proper set of clock operations
270 * @sdev: pointer to the SCMI device
271 * @sclk: A reference to an SCMI clock descriptor
272 * @atomic_capable: A flag to indicate if atomic mode is supported by the
273 * transport
274 * @atomic_threshold_us: Platform atomic threshold value in microseconds:
275 * clk_ops are atomic when clock enable latency is less
276 * than this threshold
277 * @clk_ops_db: A reference to the array used as a database to store all the
278 * created clock operations combinations.
279 * @db_size: Maximum number of entries held by @clk_ops_db
280 *
281 * After having built a bitmap descriptor to represent the set of features
282 * needed by this SCMI clock, at first use it to lookup into the set of
283 * previously allocated clk_ops to check if a suitable combination of clock
284 * operations was already created; when no match is found allocate a brand new
285 * set of clk_ops satisfying the required combination of features and save it
286 * for future references.
287 *
288 * In this way only one set of clk_ops is ever created for each different
289 * combination that is effectively needed by a driver instance.
290 *
291 * Return: A pointer to the allocated and configured clk_ops on success, or
292 * NULL otherwise.
293 */
294static const struct clk_ops *
295scmi_clk_ops_select(struct scmi_device *sdev, struct scmi_clk *sclk,
296 bool atomic_capable, unsigned int atomic_threshold_us,
297 const struct clk_ops **clk_ops_db, size_t db_size)
298{
299 int ret;
300 u32 val;
301 const struct scmi_clock_info *ci = sclk->info;
302 unsigned int feats_key = 0;
303 const struct clk_ops *ops;
304 struct scmi_clk_oem *oem_data = dev_get_drvdata(&sdev->dev);
305
306 /*
307 * Note that when transport is atomic but SCMI protocol did not
308 * specify (or support) an enable_latency associated with a
309 * clock, we default to use atomic operations mode.
310 */
311 if (atomic_capable && ci->enable_latency <= atomic_threshold_us)
312 feats_key |= BIT(SCMI_CLK_ATOMIC_SUPPORTED);
313
314 if (!ci->state_ctrl_forbidden)
315 feats_key |= BIT(SCMI_CLK_STATE_CTRL_SUPPORTED);
316
317 if (!ci->rate_ctrl_forbidden)
318 feats_key |= BIT(SCMI_CLK_RATE_CTRL_SUPPORTED);
319
320 if (!ci->parent_ctrl_forbidden)
321 feats_key |= BIT(SCMI_CLK_PARENT_CTRL_SUPPORTED);
322
323 if (ci->extended_config) {
324 ret = scmi_proto_clk_ops->config_oem_get(sclk->ph, sclk->id,
325 SCMI_CLOCK_CFG_DUTY_CYCLE,
326 &val, NULL, false);
327 if (!ret)
328 feats_key |= BIT(SCMI_CLK_DUTY_CYCLE_SUPPORTED);
329
330 if (oem_data && oem_data->query_ext_oem_feats)
331 oem_data->query_ext_oem_feats(sclk->ph, sclk->id, &feats_key);
332 }
333
334 if (WARN_ON(feats_key >= db_size))
335 return NULL;
336
337 /* Lookup previously allocated ops */
338 ops = clk_ops_db[feats_key];
339 if (ops)
340 return ops;
341
342 /* Did not find a pre-allocated clock_ops */
343 ops = scmi_clk_ops_alloc(sclk->dev, feats_key);
344 if (!ops)
345 return NULL;
346
347 /* Store new ops combinations */
348 clk_ops_db[feats_key] = ops;
349
350 return ops;
351}
352
353static int scmi_clocks_probe(struct scmi_device *sdev)
354{
355 int idx, count, err;
356 unsigned int atomic_threshold_us;
357 bool transport_is_atomic;
358 struct clk_hw **hws;
359 struct clk_hw_onecell_data *clk_data;
360 struct device *dev = &sdev->dev;
361 struct device_node *np = dev->of_node;
362 const struct scmi_handle *handle = sdev->handle;
363 struct scmi_protocol_handle *ph;
364 const struct clk_ops *scmi_clk_ops_db[SCMI_MAX_CLK_OPS] = {};
365 struct scmi_clk *sclks;
366
367 if (!handle)
368 return -ENODEV;
369
370 scmi_proto_clk_ops =
371 handle->devm_protocol_get(sdev, SCMI_PROTOCOL_CLOCK, &ph);
372 if (IS_ERR(scmi_proto_clk_ops))
373 return PTR_ERR(scmi_proto_clk_ops);
374
375 count = scmi_proto_clk_ops->count_get(ph);
376 if (count < 0) {
377 dev_err(dev, "%pOFn: invalid clock output count\n", np);
378 return -EINVAL;
379 }
380
381 clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, count),
382 GFP_KERNEL);
383 if (!clk_data)
384 return -ENOMEM;
385
386 clk_data->num = count;
387 hws = clk_data->hws;
388
389 scmi_clk_oem_init(sdev);
390
391 transport_is_atomic = handle->is_transport_atomic(handle,
392 &atomic_threshold_us);
393
394 sclks = devm_kcalloc(dev, count, sizeof(*sclks), GFP_KERNEL);
395 if (!sclks)
396 return -ENOMEM;
397
398 for (idx = 0; idx < count; idx++)
399 hws[idx] = &sclks[idx].hw;
400
401 for (idx = 0; idx < count; idx++) {
402 struct scmi_clk *sclk = &sclks[idx];
403 const struct clk_ops *scmi_ops;
404
405 sclk->info = scmi_proto_clk_ops->info_get(ph, idx);
406 if (!sclk->info) {
407 dev_dbg(dev, "invalid clock info for idx %d\n", idx);
408 hws[idx] = NULL;
409 continue;
410 }
411
412 sclk->id = idx;
413 sclk->ph = ph;
414 sclk->dev = dev;
415
416 /*
417 * Note that the scmi_clk_ops_db is on the stack, not global,
418 * because it cannot be shared between multiple probe-sequences
419 * to avoid sharing the devm_ allocated clk_ops between multiple
420 * SCMI clk driver instances.
421 */
422 scmi_ops = scmi_clk_ops_select(sdev, sclk, transport_is_atomic,
423 atomic_threshold_us,
424 scmi_clk_ops_db,
425 ARRAY_SIZE(scmi_clk_ops_db));
426 if (!scmi_ops)
427 return -ENOMEM;
428
429 /* Initialize clock parent data. */
430 if (sclk->info->num_parents > 0) {
431 sclk->parent_data = devm_kcalloc(dev, sclk->info->num_parents,
432 sizeof(*sclk->parent_data), GFP_KERNEL);
433 if (!sclk->parent_data)
434 return -ENOMEM;
435
436 for (int i = 0; i < sclk->info->num_parents; i++) {
437 sclk->parent_data[i].index = sclk->info->parents[i];
438 sclk->parent_data[i].hw = hws[sclk->info->parents[i]];
439 }
440 }
441
442 err = scmi_clk_ops_init(dev, sclk, scmi_ops);
443 if (err) {
444 dev_err(dev, "failed to register clock %d\n", idx);
445 devm_kfree(dev, sclk->parent_data);
446 hws[idx] = NULL;
447 } else {
448 dev_dbg(dev, "Registered clock:%s%s\n",
449 sclk->info->name,
450 scmi_ops->enable ? " (atomic ops)" : "");
451 }
452 }
453
454 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
455 clk_data);
456}
457
458static const struct scmi_device_id scmi_id_table[] = {
459 { SCMI_PROTOCOL_CLOCK, "clocks" },
460 { },
461};
462MODULE_DEVICE_TABLE(scmi, scmi_id_table);
463
464static struct scmi_driver scmi_clocks_driver = {
465 .name = "scmi-clocks",
466 .probe = scmi_clocks_probe,
467 .id_table = scmi_id_table,
468};
469module_scmi_driver(scmi_clocks_driver);
470
471MODULE_AUTHOR("Sudeep Holla <[email protected]>");
472MODULE_DESCRIPTION("ARM SCMI clock driver");
473MODULE_LICENSE("GPL v2");