| 1 | |
| 2 | |
| 3 | * System Control and Power Interface (SCPI) Protocol based clock driver
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| 4 | *
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| 5 | * Copyright (C) 2015 ARM Ltd.
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| 6 |
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| 7 |
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| 8 | #include <linux/clk-provider.h>
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| 9 | #include <linux/device.h>
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| 10 | #include <linux/err.h>
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| 11 | #include <linux/of.h>
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| 12 | #include <linux/module.h>
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| 13 | #include <linux/platform_device.h>
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| 14 | #include <linux/scpi_protocol.h>
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| 15 |
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| 16 | struct scpi_clk {
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| 17 | u32 id;
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| 18 | struct clk_hw hw;
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| 19 | struct scpi_dvfs_info *info;
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| 20 | struct scpi_ops *scpi_ops;
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| 21 | };
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| 22 |
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| 23 | #define to_scpi_clk(clk) container_of(clk, struct scpi_clk, hw)
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| 24 |
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| 25 | static struct platform_device *cpufreq_dev;
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| 26 |
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| 27 | static unsigned long scpi_clk_recalc_rate(struct clk_hw *hw,
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| 28 | unsigned long parent_rate)
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| 29 | {
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| 30 | struct scpi_clk *clk = to_scpi_clk(hw);
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| 31 |
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| 32 | return clk->scpi_ops->clk_get_val(clk->id);
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| 33 | }
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| 34 |
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| 35 | static int scpi_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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| 36 | unsigned long parent_rate)
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| 37 | {
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| 38 | struct scpi_clk *clk = to_scpi_clk(hw);
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| 39 |
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| 40 | return clk->scpi_ops->clk_set_val(clk->id, rate);
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| 41 | }
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| 42 |
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| 43 | static const struct clk_ops scpi_clk_ops = {
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| 44 | .recalc_rate = scpi_clk_recalc_rate,
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| 45 | .determine_rate = clk_determine_rate_noop,
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| 46 | .set_rate = scpi_clk_set_rate,
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| 47 | };
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| 48 |
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| 49 |
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| 50 | static long __scpi_dvfs_round_rate(struct scpi_clk *clk, unsigned long rate)
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| 51 | {
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| 52 | int idx;
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| 53 | unsigned long fmin = 0, fmax = ~0, ftmp;
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| 54 | const struct scpi_opp *opp = clk->info->opps;
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| 55 |
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| 56 | for (idx = 0; idx < clk->info->count; idx++, opp++) {
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| 57 | ftmp = opp->freq;
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| 58 | if (ftmp >= rate) {
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| 59 | if (ftmp <= fmax)
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| 60 | fmax = ftmp;
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| 61 | break;
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| 62 | } else if (ftmp >= fmin) {
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| 63 | fmin = ftmp;
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| 64 | }
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| 65 | }
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| 66 | return fmax != ~0 ? fmax : fmin;
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| 67 | }
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| 68 |
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| 69 | static unsigned long scpi_dvfs_recalc_rate(struct clk_hw *hw,
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| 70 | unsigned long parent_rate)
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| 71 | {
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| 72 | struct scpi_clk *clk = to_scpi_clk(hw);
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| 73 | int idx = clk->scpi_ops->dvfs_get_idx(clk->id);
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| 74 | const struct scpi_opp *opp;
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| 75 |
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| 76 | if (idx < 0 || idx >= clk->info->count)
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| 77 | return 0;
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| 78 |
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| 79 | opp = clk->info->opps + idx;
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| 80 | return opp->freq;
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| 81 | }
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| 82 |
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| 83 | static int scpi_dvfs_determine_rate(struct clk_hw *hw,
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| 84 | struct clk_rate_request *req)
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| 85 | {
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| 86 | struct scpi_clk *clk = to_scpi_clk(hw);
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| 87 |
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| 88 | req->rate = __scpi_dvfs_round_rate(clk, req->rate);
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| 89 |
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| 90 | return 0;
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| 91 | }
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| 92 |
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| 93 | static int __scpi_find_dvfs_index(struct scpi_clk *clk, unsigned long rate)
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| 94 | {
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| 95 | int idx, max_opp = clk->info->count;
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| 96 | const struct scpi_opp *opp = clk->info->opps;
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| 97 |
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| 98 | for (idx = 0; idx < max_opp; idx++, opp++)
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| 99 | if (opp->freq == rate)
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| 100 | return idx;
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| 101 | return -EINVAL;
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| 102 | }
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| 103 |
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| 104 | static int scpi_dvfs_set_rate(struct clk_hw *hw, unsigned long rate,
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| 105 | unsigned long parent_rate)
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| 106 | {
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| 107 | struct scpi_clk *clk = to_scpi_clk(hw);
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| 108 | int ret = __scpi_find_dvfs_index(clk, rate);
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| 109 |
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| 110 | if (ret < 0)
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| 111 | return ret;
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| 112 | return clk->scpi_ops->dvfs_set_idx(clk->id, (u8)ret);
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| 113 | }
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| 114 |
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| 115 | static const struct clk_ops scpi_dvfs_ops = {
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| 116 | .recalc_rate = scpi_dvfs_recalc_rate,
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| 117 | .determine_rate = scpi_dvfs_determine_rate,
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| 118 | .set_rate = scpi_dvfs_set_rate,
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| 119 | };
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| 120 |
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| 121 | static const struct of_device_id scpi_clk_match[] __maybe_unused = {
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| 122 | { .compatible = "arm,scpi-dvfs-clocks", .data = &scpi_dvfs_ops, },
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| 123 | { .compatible = "arm,scpi-variable-clocks", .data = &scpi_clk_ops, },
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| 124 | {}
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| 125 | };
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| 126 |
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| 127 | static int
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| 128 | scpi_clk_ops_init(struct device *dev, const struct of_device_id *match,
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| 129 | struct scpi_clk *sclk, const char *name)
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| 130 | {
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| 131 | struct clk_init_data init;
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| 132 | unsigned long min = 0, max = 0;
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| 133 | int ret;
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| 134 |
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| 135 | init.name = name;
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| 136 | init.flags = 0;
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| 137 | init.num_parents = 0;
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| 138 | init.ops = match->data;
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| 139 | sclk->hw.init = &init;
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| 140 | sclk->scpi_ops = get_scpi_ops();
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| 141 |
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| 142 | if (init.ops == &scpi_dvfs_ops) {
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| 143 | sclk->info = sclk->scpi_ops->dvfs_get_info(sclk->id);
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| 144 | if (IS_ERR(sclk->info))
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| 145 | return PTR_ERR(sclk->info);
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| 146 | } else if (init.ops == &scpi_clk_ops) {
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| 147 | if (sclk->scpi_ops->clk_get_range(sclk->id, &min, &max) || !max)
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| 148 | return -EINVAL;
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| 149 | } else {
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| 150 | return -EINVAL;
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| 151 | }
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| 152 |
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| 153 | ret = devm_clk_hw_register(dev, &sclk->hw);
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| 154 | if (!ret && max)
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| 155 | clk_hw_set_rate_range(&sclk->hw, min, max);
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| 156 | return ret;
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| 157 | }
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| 158 |
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| 159 | struct scpi_clk_data {
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| 160 | struct scpi_clk **clk;
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| 161 | unsigned int clk_num;
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| 162 | };
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| 163 |
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| 164 | static struct clk_hw *
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| 165 | scpi_of_clk_src_get(struct of_phandle_args *clkspec, void *data)
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| 166 | {
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| 167 | struct scpi_clk *sclk;
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| 168 | struct scpi_clk_data *clk_data = data;
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| 169 | unsigned int idx = clkspec->args[0], count;
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| 170 |
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| 171 | for (count = 0; count < clk_data->clk_num; count++) {
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| 172 | sclk = clk_data->clk[count];
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| 173 | if (idx == sclk->id)
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| 174 | return &sclk->hw;
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| 175 | }
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| 176 |
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| 177 | return ERR_PTR(-EINVAL);
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| 178 | }
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| 179 |
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| 180 | static int scpi_clk_add(struct device *dev, struct device_node *np,
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| 181 | const struct of_device_id *match)
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| 182 | {
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| 183 | int idx, count, err;
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| 184 | struct scpi_clk_data *clk_data;
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| 185 |
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| 186 | count = of_property_count_strings(np, "clock-output-names");
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| 187 | if (count < 0) {
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| 188 | dev_err(dev, "%pOFn: invalid clock output count\n", np);
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| 189 | return -EINVAL;
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| 190 | }
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| 191 |
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| 192 | clk_data = devm_kmalloc(dev, sizeof(*clk_data), GFP_KERNEL);
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| 193 | if (!clk_data)
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| 194 | return -ENOMEM;
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| 195 |
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| 196 | clk_data->clk_num = count;
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| 197 | clk_data->clk = devm_kcalloc(dev, count, sizeof(*clk_data->clk),
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| 198 | GFP_KERNEL);
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| 199 | if (!clk_data->clk)
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| 200 | return -ENOMEM;
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| 201 |
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| 202 | for (idx = 0; idx < count; idx++) {
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| 203 | struct scpi_clk *sclk;
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| 204 | const char *name;
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| 205 | u32 val;
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| 206 |
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| 207 | sclk = devm_kzalloc(dev, sizeof(*sclk), GFP_KERNEL);
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| 208 | if (!sclk)
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| 209 | return -ENOMEM;
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| 210 |
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| 211 | if (of_property_read_string_index(np, "clock-output-names",
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| 212 | idx, &name)) {
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| 213 | dev_err(dev, "invalid clock name @ %pOFn\n", np);
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| 214 | return -EINVAL;
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| 215 | }
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| 216 |
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| 217 | if (of_property_read_u32_index(np, "clock-indices",
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| 218 | idx, &val)) {
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| 219 | dev_err(dev, "invalid clock index @ %pOFn\n", np);
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| 220 | return -EINVAL;
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| 221 | }
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| 222 |
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| 223 | sclk->id = val;
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| 224 |
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| 225 | err = scpi_clk_ops_init(dev, match, sclk, name);
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| 226 | if (err) {
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| 227 | dev_err(dev, "failed to register clock '%s'\n", name);
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| 228 | return err;
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| 229 | }
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| 230 |
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| 231 | dev_dbg(dev, "Registered clock '%s'\n", name);
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| 232 | clk_data->clk[idx] = sclk;
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| 233 | }
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| 234 |
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| 235 | return of_clk_add_hw_provider(np, scpi_of_clk_src_get, clk_data);
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| 236 | }
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| 237 |
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| 238 | static void scpi_clocks_remove(struct platform_device *pdev)
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| 239 | {
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| 240 | struct device *dev = &pdev->dev;
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| 241 | struct device_node *child, *np = dev->of_node;
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| 242 |
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| 243 | if (cpufreq_dev) {
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| 244 | platform_device_unregister(cpufreq_dev);
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| 245 | cpufreq_dev = NULL;
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| 246 | }
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| 247 |
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| 248 | for_each_available_child_of_node(np, child)
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| 249 | of_clk_del_provider(child);
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| 250 | }
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| 251 |
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| 252 | static int scpi_clocks_probe(struct platform_device *pdev)
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| 253 | {
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| 254 | int ret;
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| 255 | struct device *dev = &pdev->dev;
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| 256 | struct device_node *np = dev->of_node;
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| 257 | const struct of_device_id *match;
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| 258 |
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| 259 | if (!get_scpi_ops())
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| 260 | return -ENXIO;
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| 261 |
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| 262 | for_each_available_child_of_node_scoped(np, child) {
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| 263 | match = of_match_node(scpi_clk_match, child);
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| 264 | if (!match)
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| 265 | continue;
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| 266 | ret = scpi_clk_add(dev, child, match);
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| 267 | if (ret) {
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| 268 | scpi_clocks_remove(pdev);
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| 269 | return ret;
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| 270 | }
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| 271 |
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| 272 | if (match->data != &scpi_dvfs_ops)
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| 273 | continue;
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| 274 |
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| 275 | if (cpufreq_dev)
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| 276 | continue;
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| 277 | cpufreq_dev = platform_device_register_simple("scpi-cpufreq",
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| 278 | PLATFORM_DEVID_NONE,
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| 279 | NULL, 0);
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| 280 | if (IS_ERR(cpufreq_dev)) {
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| 281 | pr_warn("unable to register cpufreq device");
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| 282 | cpufreq_dev = NULL;
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| 283 | }
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| 284 | }
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| 285 | return 0;
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| 286 | }
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| 287 |
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| 288 | static const struct of_device_id scpi_clocks_ids[] = {
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| 289 | { .compatible = "arm,scpi-clocks", },
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| 290 | {}
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| 291 | };
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| 292 | MODULE_DEVICE_TABLE(of, scpi_clocks_ids);
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| 293 |
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| 294 | static struct platform_driver scpi_clocks_driver = {
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| 295 | .driver = {
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| 296 | .name = "scpi_clocks",
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| 297 | .of_match_table = scpi_clocks_ids,
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| 298 | },
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| 299 | .probe = scpi_clocks_probe,
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| 300 | .remove = scpi_clocks_remove,
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| 301 | };
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| 302 | module_platform_driver(scpi_clocks_driver);
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| 303 |
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| 304 | MODULE_AUTHOR("Sudeep Holla <[email protected]>");
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| 305 | MODULE_DESCRIPTION("ARM SCPI clock driver");
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| 306 | MODULE_LICENSE("GPL v2");
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