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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Driver for IDT Versaclock 5
4 *
5 * Copyright (C) 2017 Marek Vasut <[email protected]>
6 */
7
8/*
9 * Possible optimizations:
10 * - Use spread spectrum
11 * - Use integer divider in FOD if applicable
12 */
13
14#include <linux/clk.h>
15#include <linux/clk-provider.h>
16#include <linux/delay.h>
17#include <linux/i2c.h>
18#include <linux/interrupt.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/property.h>
22#include <linux/regmap.h>
23#include <linux/slab.h>
24
25#include <dt-bindings/clock/versaclock.h>
26
27/* VersaClock5 registers */
28#define VC5_OTP_CONTROL 0x00
29
30/* Factory-reserved register block */
31#define VC5_RSVD_DEVICE_ID 0x01
32#define VC5_RSVD_ADC_GAIN_7_0 0x02
33#define VC5_RSVD_ADC_GAIN_15_8 0x03
34#define VC5_RSVD_ADC_OFFSET_7_0 0x04
35#define VC5_RSVD_ADC_OFFSET_15_8 0x05
36#define VC5_RSVD_TEMPY 0x06
37#define VC5_RSVD_OFFSET_TBIN 0x07
38#define VC5_RSVD_GAIN 0x08
39#define VC5_RSVD_TEST_NP 0x09
40#define VC5_RSVD_UNUSED 0x0a
41#define VC5_RSVD_BANDGAP_TRIM_UP 0x0b
42#define VC5_RSVD_BANDGAP_TRIM_DN 0x0c
43#define VC5_RSVD_CLK_R_12_CLK_AMP_4 0x0d
44#define VC5_RSVD_CLK_R_34_CLK_AMP_4 0x0e
45#define VC5_RSVD_CLK_AMP_123 0x0f
46
47/* Configuration register block */
48#define VC5_PRIM_SRC_SHDN 0x10
49#define VC5_PRIM_SRC_SHDN_EN_XTAL BIT(7)
50#define VC5_PRIM_SRC_SHDN_EN_CLKIN BIT(6)
51#define VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ BIT(3)
52#define VC5_PRIM_SRC_SHDN_SP BIT(1)
53#define VC5_PRIM_SRC_SHDN_EN_GBL_SHDN BIT(0)
54
55#define VC5_VCO_BAND 0x11
56#define VC5_XTAL_X1_LOAD_CAP 0x12
57#define VC5_XTAL_X2_LOAD_CAP 0x13
58#define VC5_REF_DIVIDER 0x15
59#define VC5_REF_DIVIDER_SEL_PREDIV2 BIT(7)
60#define VC5_REF_DIVIDER_REF_DIV(n) ((n) & 0x3f)
61
62#define VC5_VCO_CTRL_AND_PREDIV 0x16
63#define VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV BIT(7)
64
65#define VC5_FEEDBACK_INT_DIV 0x17
66#define VC5_FEEDBACK_INT_DIV_BITS 0x18
67#define VC5_FEEDBACK_FRAC_DIV(n) (0x19 + (n))
68#define VC5_RC_CONTROL0 0x1e
69#define VC5_RC_CONTROL1 0x1f
70
71/* These registers are named "Unused Factory Reserved Registers" */
72#define VC5_RESERVED_X0(idx) (0x20 + ((idx) * 0x10))
73#define VC5_RESERVED_X0_BYPASS_SYNC BIT(7) /* bypass_sync<idx> bit */
74
75/* Output divider control for divider 1,2,3,4 */
76#define VC5_OUT_DIV_CONTROL(idx) (0x21 + ((idx) * 0x10))
77#define VC5_OUT_DIV_CONTROL_RESET BIT(7)
78#define VC5_OUT_DIV_CONTROL_SELB_NORM BIT(3)
79#define VC5_OUT_DIV_CONTROL_SEL_EXT BIT(2)
80#define VC5_OUT_DIV_CONTROL_INT_MODE BIT(1)
81#define VC5_OUT_DIV_CONTROL_EN_FOD BIT(0)
82
83#define VC5_OUT_DIV_FRAC(idx, n) (0x22 + ((idx) * 0x10) + (n))
84#define VC5_OUT_DIV_FRAC4_OD_SCEE BIT(1)
85
86#define VC5_OUT_DIV_STEP_SPREAD(idx, n) (0x26 + ((idx) * 0x10) + (n))
87#define VC5_OUT_DIV_SPREAD_MOD(idx, n) (0x29 + ((idx) * 0x10) + (n))
88#define VC5_OUT_DIV_SKEW_INT(idx, n) (0x2b + ((idx) * 0x10) + (n))
89#define VC5_OUT_DIV_INT(idx, n) (0x2d + ((idx) * 0x10) + (n))
90#define VC5_OUT_DIV_SKEW_FRAC(idx) (0x2f + ((idx) * 0x10))
91
92/* Clock control register for clock 1,2 */
93#define VC5_CLK_OUTPUT_CFG(idx, n) (0x60 + ((idx) * 0x2) + (n))
94#define VC5_CLK_OUTPUT_CFG0_CFG_SHIFT 5
95#define VC5_CLK_OUTPUT_CFG0_CFG_MASK GENMASK(7, VC5_CLK_OUTPUT_CFG0_CFG_SHIFT)
96
97#define VC5_CLK_OUTPUT_CFG0_CFG_LVPECL (VC5_LVPECL)
98#define VC5_CLK_OUTPUT_CFG0_CFG_CMOS (VC5_CMOS)
99#define VC5_CLK_OUTPUT_CFG0_CFG_HCSL33 (VC5_HCSL33)
100#define VC5_CLK_OUTPUT_CFG0_CFG_LVDS (VC5_LVDS)
101#define VC5_CLK_OUTPUT_CFG0_CFG_CMOS2 (VC5_CMOS2)
102#define VC5_CLK_OUTPUT_CFG0_CFG_CMOSD (VC5_CMOSD)
103#define VC5_CLK_OUTPUT_CFG0_CFG_HCSL25 (VC5_HCSL25)
104
105#define VC5_CLK_OUTPUT_CFG0_PWR_SHIFT 3
106#define VC5_CLK_OUTPUT_CFG0_PWR_MASK GENMASK(4, VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
107#define VC5_CLK_OUTPUT_CFG0_PWR_18 (0<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
108#define VC5_CLK_OUTPUT_CFG0_PWR_25 (2<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
109#define VC5_CLK_OUTPUT_CFG0_PWR_33 (3<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
110#define VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT 0
111#define VC5_CLK_OUTPUT_CFG0_SLEW_MASK GENMASK(1, VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
112#define VC5_CLK_OUTPUT_CFG0_SLEW_80 (0<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
113#define VC5_CLK_OUTPUT_CFG0_SLEW_85 (1<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
114#define VC5_CLK_OUTPUT_CFG0_SLEW_90 (2<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
115#define VC5_CLK_OUTPUT_CFG0_SLEW_100 (3<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
116#define VC5_CLK_OUTPUT_CFG1_EN_CLKBUF BIT(0)
117
118#define VC5_CLK_OE_SHDN 0x68
119#define VC5_CLK_OS_SHDN 0x69
120
121#define VC5_GLOBAL_REGISTER 0x76
122#define VC5_GLOBAL_REGISTER_GLOBAL_RESET BIT(5)
123
124/* The minimum VCO frequency is 2.5 GHz. The maximum is variant specific. */
125#define VC5_PLL_VCO_MIN 2500000000UL
126
127/* VC5 Input mux settings */
128#define VC5_MUX_IN_XIN BIT(0)
129#define VC5_MUX_IN_CLKIN BIT(1)
130
131/* Maximum number of clk_out supported by this driver */
132#define VC5_MAX_CLK_OUT_NUM 5
133
134/* Maximum number of FODs supported by this driver */
135#define VC5_MAX_FOD_NUM 4
136
137/* flags to describe chip features */
138/* chip has built-in oscillator */
139#define VC5_HAS_INTERNAL_XTAL BIT(0)
140/* chip has PFD requency doubler */
141#define VC5_HAS_PFD_FREQ_DBL BIT(1)
142/* chip has bits to disable FOD sync */
143#define VC5_HAS_BYPASS_SYNC_BIT BIT(2)
144
145/* Supported IDT VC5 models. */
146enum vc5_model {
147 IDT_VC5_5P49V5923,
148 IDT_VC5_5P49V5925,
149 IDT_VC5_5P49V5933,
150 IDT_VC5_5P49V5935,
151 IDT_VC6_5P49V60,
152 IDT_VC6_5P49V6901,
153 IDT_VC6_5P49V6965,
154 IDT_VC6_5P49V6975,
155};
156
157/* Structure to describe features of a particular VC5 model */
158struct vc5_chip_info {
159 const enum vc5_model model;
160 const unsigned int clk_fod_cnt;
161 const unsigned int clk_out_cnt;
162 const u32 flags;
163 const unsigned long vco_max;
164};
165
166struct vc5_driver_data;
167
168struct vc5_hw_data {
169 struct clk_hw hw;
170 struct vc5_driver_data *vc5;
171 u32 div_int;
172 u32 div_frc;
173 unsigned int num;
174};
175
176struct vc5_out_data {
177 struct clk_hw hw;
178 struct vc5_driver_data *vc5;
179 unsigned int num;
180 unsigned int clk_output_cfg0;
181 unsigned int clk_output_cfg0_mask;
182};
183
184struct vc5_driver_data {
185 struct i2c_client *client;
186 struct regmap *regmap;
187 const struct vc5_chip_info *chip_info;
188
189 struct clk *pin_xin;
190 struct clk *pin_clkin;
191 unsigned char clk_mux_ins;
192 struct clk_hw clk_mux;
193 struct clk_hw clk_mul;
194 struct clk_hw clk_pfd;
195 struct vc5_hw_data clk_pll;
196 struct vc5_hw_data clk_fod[VC5_MAX_FOD_NUM];
197 struct vc5_out_data clk_out[VC5_MAX_CLK_OUT_NUM];
198};
199
200/*
201 * VersaClock5 i2c regmap
202 */
203static bool vc5_regmap_is_writeable(struct device *dev, unsigned int reg)
204{
205 /* Factory reserved regs, make them read-only */
206 if (reg <= 0xf)
207 return false;
208
209 /* Factory reserved regs, make them read-only */
210 if (reg == 0x14 || reg == 0x1c || reg == 0x1d)
211 return false;
212
213 return true;
214}
215
216static const struct regmap_config vc5_regmap_config = {
217 .reg_bits = 8,
218 .val_bits = 8,
219 .cache_type = REGCACHE_MAPLE,
220 .max_register = 0x76,
221 .writeable_reg = vc5_regmap_is_writeable,
222};
223
224/*
225 * VersaClock5 input multiplexer between XTAL and CLKIN divider
226 */
227static unsigned char vc5_mux_get_parent(struct clk_hw *hw)
228{
229 struct vc5_driver_data *vc5 =
230 container_of(hw, struct vc5_driver_data, clk_mux);
231 const u8 mask = VC5_PRIM_SRC_SHDN_EN_XTAL | VC5_PRIM_SRC_SHDN_EN_CLKIN;
232 unsigned int src;
233 int ret;
234
235 ret = regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &src);
236 if (ret)
237 return 0;
238
239 src &= mask;
240
241 if (src == VC5_PRIM_SRC_SHDN_EN_XTAL)
242 return 0;
243
244 if (src == VC5_PRIM_SRC_SHDN_EN_CLKIN)
245 return 1;
246
247 dev_warn(&vc5->client->dev,
248 "Invalid clock input configuration (%02x)\n", src);
249 return 0;
250}
251
252static int vc5_mux_set_parent(struct clk_hw *hw, u8 index)
253{
254 struct vc5_driver_data *vc5 =
255 container_of(hw, struct vc5_driver_data, clk_mux);
256 const u8 mask = VC5_PRIM_SRC_SHDN_EN_XTAL | VC5_PRIM_SRC_SHDN_EN_CLKIN;
257 u8 src;
258
259 if ((index > 1) || !vc5->clk_mux_ins)
260 return -EINVAL;
261
262 if (vc5->clk_mux_ins == (VC5_MUX_IN_CLKIN | VC5_MUX_IN_XIN)) {
263 if (index == 0)
264 src = VC5_PRIM_SRC_SHDN_EN_XTAL;
265 if (index == 1)
266 src = VC5_PRIM_SRC_SHDN_EN_CLKIN;
267 } else {
268 if (index != 0)
269 return -EINVAL;
270
271 if (vc5->clk_mux_ins == VC5_MUX_IN_XIN)
272 src = VC5_PRIM_SRC_SHDN_EN_XTAL;
273 else if (vc5->clk_mux_ins == VC5_MUX_IN_CLKIN)
274 src = VC5_PRIM_SRC_SHDN_EN_CLKIN;
275 else /* Invalid; should have been caught by vc5_probe() */
276 return -EINVAL;
277 }
278
279 return regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, mask, src);
280}
281
282static const struct clk_ops vc5_mux_ops = {
283 .determine_rate = clk_hw_determine_rate_no_reparent,
284 .set_parent = vc5_mux_set_parent,
285 .get_parent = vc5_mux_get_parent,
286};
287
288static unsigned long vc5_dbl_recalc_rate(struct clk_hw *hw,
289 unsigned long parent_rate)
290{
291 struct vc5_driver_data *vc5 =
292 container_of(hw, struct vc5_driver_data, clk_mul);
293 unsigned int premul;
294 int ret;
295
296 ret = regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &premul);
297 if (ret)
298 return 0;
299
300 if (premul & VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ)
301 parent_rate *= 2;
302
303 return parent_rate;
304}
305
306static int vc5_dbl_determine_rate(struct clk_hw *hw,
307 struct clk_rate_request *req)
308{
309 if ((req->best_parent_rate == req->rate) || ((req->best_parent_rate * 2) == req->rate))
310 return 0;
311 else
312 return -EINVAL;
313}
314
315static int vc5_dbl_set_rate(struct clk_hw *hw, unsigned long rate,
316 unsigned long parent_rate)
317{
318 struct vc5_driver_data *vc5 =
319 container_of(hw, struct vc5_driver_data, clk_mul);
320 u32 mask;
321
322 if ((parent_rate * 2) == rate)
323 mask = VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ;
324 else
325 mask = 0;
326
327 return regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN,
328 VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ,
329 mask);
330}
331
332static const struct clk_ops vc5_dbl_ops = {
333 .recalc_rate = vc5_dbl_recalc_rate,
334 .determine_rate = vc5_dbl_determine_rate,
335 .set_rate = vc5_dbl_set_rate,
336};
337
338static unsigned long vc5_pfd_recalc_rate(struct clk_hw *hw,
339 unsigned long parent_rate)
340{
341 struct vc5_driver_data *vc5 =
342 container_of(hw, struct vc5_driver_data, clk_pfd);
343 unsigned int prediv, div;
344 int ret;
345
346 ret = regmap_read(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, &prediv);
347 if (ret)
348 return 0;
349
350 /* The bypass_prediv is set, PLL fed from Ref_in directly. */
351 if (prediv & VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV)
352 return parent_rate;
353
354 ret = regmap_read(vc5->regmap, VC5_REF_DIVIDER, &div);
355 if (ret)
356 return 0;
357
358 /* The Sel_prediv2 is set, PLL fed from prediv2 (Ref_in / 2) */
359 if (div & VC5_REF_DIVIDER_SEL_PREDIV2)
360 return parent_rate / 2;
361 else
362 return parent_rate / VC5_REF_DIVIDER_REF_DIV(div);
363}
364
365static int vc5_pfd_determine_rate(struct clk_hw *hw,
366 struct clk_rate_request *req)
367{
368 unsigned long idiv;
369
370 /* PLL cannot operate with input clock above 50 MHz. */
371 if (req->rate > 50000000)
372 return -EINVAL;
373
374 /* CLKIN within range of PLL input, feed directly to PLL. */
375 if (req->best_parent_rate <= 50000000) {
376 req->rate = req->best_parent_rate;
377
378 return 0;
379 }
380
381 idiv = DIV_ROUND_UP(req->best_parent_rate, req->rate);
382 if (idiv > 127)
383 return -EINVAL;
384
385 req->rate = req->best_parent_rate / idiv;
386
387 return 0;
388}
389
390static int vc5_pfd_set_rate(struct clk_hw *hw, unsigned long rate,
391 unsigned long parent_rate)
392{
393 struct vc5_driver_data *vc5 =
394 container_of(hw, struct vc5_driver_data, clk_pfd);
395 unsigned long idiv;
396 int ret;
397 u8 div;
398
399 /* CLKIN within range of PLL input, feed directly to PLL. */
400 if (parent_rate <= 50000000) {
401 ret = regmap_set_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV,
402 VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV);
403 if (ret)
404 return ret;
405
406 return regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, 0x00);
407 }
408
409 idiv = DIV_ROUND_UP(parent_rate, rate);
410
411 /* We have dedicated div-2 predivider. */
412 if (idiv == 2)
413 div = VC5_REF_DIVIDER_SEL_PREDIV2;
414 else
415 div = VC5_REF_DIVIDER_REF_DIV(idiv);
416
417 ret = regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, div);
418 if (ret)
419 return ret;
420
421 return regmap_clear_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV,
422 VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV);
423}
424
425static const struct clk_ops vc5_pfd_ops = {
426 .recalc_rate = vc5_pfd_recalc_rate,
427 .determine_rate = vc5_pfd_determine_rate,
428 .set_rate = vc5_pfd_set_rate,
429};
430
431/*
432 * VersaClock5 PLL/VCO
433 */
434static unsigned long vc5_pll_recalc_rate(struct clk_hw *hw,
435 unsigned long parent_rate)
436{
437 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
438 struct vc5_driver_data *vc5 = hwdata->vc5;
439 u32 div_int, div_frc;
440 u8 fb[5];
441
442 regmap_bulk_read(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5);
443
444 div_int = (fb[0] << 4) | (fb[1] >> 4);
445 div_frc = (fb[2] << 16) | (fb[3] << 8) | fb[4];
446
447 /* The PLL divider has 12 integer bits and 24 fractional bits */
448 return (parent_rate * div_int) + ((parent_rate * div_frc) >> 24);
449}
450
451static int vc5_pll_determine_rate(struct clk_hw *hw,
452 struct clk_rate_request *req)
453{
454 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
455 struct vc5_driver_data *vc5 = hwdata->vc5;
456 u32 div_int;
457 u64 div_frc;
458
459 req->rate = clamp(req->rate, VC5_PLL_VCO_MIN, vc5->chip_info->vco_max);
460
461 /* Determine integer part, which is 12 bit wide */
462 div_int = req->rate / req->best_parent_rate;
463 if (div_int > 0xfff)
464 req->rate = req->best_parent_rate * 0xfff;
465
466 /* Determine best fractional part, which is 24 bit wide */
467 div_frc = req->rate % req->best_parent_rate;
468 div_frc *= BIT(24) - 1;
469 do_div(div_frc, req->best_parent_rate);
470
471 hwdata->div_int = div_int;
472 hwdata->div_frc = (u32)div_frc;
473
474 req->rate = (req->best_parent_rate * div_int) + ((req->best_parent_rate * div_frc) >> 24);
475
476 return 0;
477}
478
479static int vc5_pll_set_rate(struct clk_hw *hw, unsigned long rate,
480 unsigned long parent_rate)
481{
482 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
483 struct vc5_driver_data *vc5 = hwdata->vc5;
484 u8 fb[5];
485
486 fb[0] = hwdata->div_int >> 4;
487 fb[1] = hwdata->div_int << 4;
488 fb[2] = hwdata->div_frc >> 16;
489 fb[3] = hwdata->div_frc >> 8;
490 fb[4] = hwdata->div_frc;
491
492 return regmap_bulk_write(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5);
493}
494
495static const struct clk_ops vc5_pll_ops = {
496 .recalc_rate = vc5_pll_recalc_rate,
497 .determine_rate = vc5_pll_determine_rate,
498 .set_rate = vc5_pll_set_rate,
499};
500
501static unsigned long vc5_fod_recalc_rate(struct clk_hw *hw,
502 unsigned long parent_rate)
503{
504 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
505 struct vc5_driver_data *vc5 = hwdata->vc5;
506 /* VCO frequency is divided by two before entering FOD */
507 u32 f_in = parent_rate / 2;
508 u32 div_int, div_frc;
509 u8 od_int[2];
510 u8 od_frc[4];
511
512 regmap_bulk_read(vc5->regmap, VC5_OUT_DIV_INT(hwdata->num, 0),
513 od_int, 2);
514 regmap_bulk_read(vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0),
515 od_frc, 4);
516
517 div_int = (od_int[0] << 4) | (od_int[1] >> 4);
518 div_frc = (od_frc[0] << 22) | (od_frc[1] << 14) |
519 (od_frc[2] << 6) | (od_frc[3] >> 2);
520
521 /* Avoid division by zero if the output is not configured. */
522 if (div_int == 0 && div_frc == 0)
523 return 0;
524
525 /* The PLL divider has 12 integer bits and 30 fractional bits */
526 return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc);
527}
528
529static int vc5_fod_determine_rate(struct clk_hw *hw,
530 struct clk_rate_request *req)
531{
532 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
533 /* VCO frequency is divided by two before entering FOD */
534 u32 f_in = req->best_parent_rate / 2;
535 u32 div_int;
536 u64 div_frc;
537
538 /* Determine integer part, which is 12 bit wide */
539 div_int = f_in / req->rate;
540 /*
541 * WARNING: The clock chip does not output signal if the integer part
542 * of the divider is 0xfff and fractional part is non-zero.
543 * Clamp the divider at 0xffe to keep the code simple.
544 */
545 if (div_int > 0xffe) {
546 div_int = 0xffe;
547 req->rate = f_in / div_int;
548 }
549
550 /* Determine best fractional part, which is 30 bit wide */
551 div_frc = f_in % req->rate;
552 div_frc <<= 24;
553 do_div(div_frc, req->rate);
554
555 hwdata->div_int = div_int;
556 hwdata->div_frc = (u32)div_frc;
557
558 req->rate = div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc);
559
560 return 0;
561}
562
563static int vc5_fod_set_rate(struct clk_hw *hw, unsigned long rate,
564 unsigned long parent_rate)
565{
566 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
567 struct vc5_driver_data *vc5 = hwdata->vc5;
568 u8 data[14] = {
569 hwdata->div_frc >> 22, hwdata->div_frc >> 14,
570 hwdata->div_frc >> 6, hwdata->div_frc << 2,
571 0, 0, 0, 0, 0,
572 0, 0,
573 hwdata->div_int >> 4, hwdata->div_int << 4,
574 0
575 };
576 int ret;
577
578 ret = regmap_bulk_write(vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0),
579 data, 14);
580 if (ret)
581 return ret;
582
583 /*
584 * Toggle magic bit in undocumented register for unknown reason.
585 * This is what the IDT timing commander tool does and the chip
586 * datasheet somewhat implies this is needed, but the register
587 * and the bit is not documented.
588 */
589 ret = regmap_clear_bits(vc5->regmap, VC5_GLOBAL_REGISTER,
590 VC5_GLOBAL_REGISTER_GLOBAL_RESET);
591 if (ret)
592 return ret;
593
594 return regmap_set_bits(vc5->regmap, VC5_GLOBAL_REGISTER,
595 VC5_GLOBAL_REGISTER_GLOBAL_RESET);
596}
597
598static const struct clk_ops vc5_fod_ops = {
599 .recalc_rate = vc5_fod_recalc_rate,
600 .determine_rate = vc5_fod_determine_rate,
601 .set_rate = vc5_fod_set_rate,
602};
603
604static int vc5_clk_out_prepare(struct clk_hw *hw)
605{
606 struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw);
607 struct vc5_driver_data *vc5 = hwdata->vc5;
608 const u8 mask = VC5_OUT_DIV_CONTROL_SELB_NORM |
609 VC5_OUT_DIV_CONTROL_SEL_EXT |
610 VC5_OUT_DIV_CONTROL_EN_FOD;
611 unsigned int src;
612 int ret;
613
614 /*
615 * When enabling a FOD, all currently enabled FODs are briefly
616 * stopped in order to synchronize all of them. This causes a clock
617 * disruption to any unrelated chips that might be already using
618 * other clock outputs. Bypass the sync feature to avoid the issue,
619 * which is possible on the VersaClock 6E family via reserved
620 * registers.
621 */
622 if (vc5->chip_info->flags & VC5_HAS_BYPASS_SYNC_BIT) {
623 ret = regmap_set_bits(vc5->regmap,
624 VC5_RESERVED_X0(hwdata->num),
625 VC5_RESERVED_X0_BYPASS_SYNC);
626 if (ret)
627 return ret;
628 }
629
630 /*
631 * If the input mux is disabled, enable it first and
632 * select source from matching FOD.
633 */
634 ret = regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src);
635 if (ret)
636 return ret;
637
638 if ((src & mask) == 0) {
639 src = VC5_OUT_DIV_CONTROL_RESET | VC5_OUT_DIV_CONTROL_EN_FOD;
640 ret = regmap_update_bits(vc5->regmap,
641 VC5_OUT_DIV_CONTROL(hwdata->num),
642 mask | VC5_OUT_DIV_CONTROL_RESET, src);
643 if (ret)
644 return ret;
645 }
646
647 /* Enable the clock buffer */
648 ret = regmap_set_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1),
649 VC5_CLK_OUTPUT_CFG1_EN_CLKBUF);
650 if (ret)
651 return ret;
652
653 if (hwdata->clk_output_cfg0_mask) {
654 dev_dbg(&vc5->client->dev, "Update output %d mask 0x%0X val 0x%0X\n",
655 hwdata->num, hwdata->clk_output_cfg0_mask,
656 hwdata->clk_output_cfg0);
657
658 ret = regmap_update_bits(vc5->regmap,
659 VC5_CLK_OUTPUT_CFG(hwdata->num, 0),
660 hwdata->clk_output_cfg0_mask,
661 hwdata->clk_output_cfg0);
662 if (ret)
663 return ret;
664 }
665
666 return 0;
667}
668
669static void vc5_clk_out_unprepare(struct clk_hw *hw)
670{
671 struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw);
672 struct vc5_driver_data *vc5 = hwdata->vc5;
673
674 /* Disable the clock buffer */
675 regmap_clear_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1),
676 VC5_CLK_OUTPUT_CFG1_EN_CLKBUF);
677}
678
679static unsigned char vc5_clk_out_get_parent(struct clk_hw *hw)
680{
681 struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw);
682 struct vc5_driver_data *vc5 = hwdata->vc5;
683 const u8 mask = VC5_OUT_DIV_CONTROL_SELB_NORM |
684 VC5_OUT_DIV_CONTROL_SEL_EXT |
685 VC5_OUT_DIV_CONTROL_EN_FOD;
686 const u8 fodclkmask = VC5_OUT_DIV_CONTROL_SELB_NORM |
687 VC5_OUT_DIV_CONTROL_EN_FOD;
688 const u8 extclk = VC5_OUT_DIV_CONTROL_SELB_NORM |
689 VC5_OUT_DIV_CONTROL_SEL_EXT;
690 unsigned int src;
691 int ret;
692
693 ret = regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src);
694 if (ret)
695 return 0;
696
697 src &= mask;
698
699 if (src == 0) /* Input mux set to DISABLED */
700 return 0;
701
702 if ((src & fodclkmask) == VC5_OUT_DIV_CONTROL_EN_FOD)
703 return 0;
704
705 if (src == extclk)
706 return 1;
707
708 dev_warn(&vc5->client->dev,
709 "Invalid clock output configuration (%02x)\n", src);
710 return 0;
711}
712
713static int vc5_clk_out_set_parent(struct clk_hw *hw, u8 index)
714{
715 struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw);
716 struct vc5_driver_data *vc5 = hwdata->vc5;
717 const u8 mask = VC5_OUT_DIV_CONTROL_RESET |
718 VC5_OUT_DIV_CONTROL_SELB_NORM |
719 VC5_OUT_DIV_CONTROL_SEL_EXT |
720 VC5_OUT_DIV_CONTROL_EN_FOD;
721 const u8 extclk = VC5_OUT_DIV_CONTROL_SELB_NORM |
722 VC5_OUT_DIV_CONTROL_SEL_EXT;
723 u8 src = VC5_OUT_DIV_CONTROL_RESET;
724
725 if (index == 0)
726 src |= VC5_OUT_DIV_CONTROL_EN_FOD;
727 else
728 src |= extclk;
729
730 return regmap_update_bits(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num),
731 mask, src);
732}
733
734static const struct clk_ops vc5_clk_out_ops = {
735 .prepare = vc5_clk_out_prepare,
736 .unprepare = vc5_clk_out_unprepare,
737 .determine_rate = clk_hw_determine_rate_no_reparent,
738 .set_parent = vc5_clk_out_set_parent,
739 .get_parent = vc5_clk_out_get_parent,
740};
741
742static struct clk_hw *vc5_of_clk_get(struct of_phandle_args *clkspec,
743 void *data)
744{
745 struct vc5_driver_data *vc5 = data;
746 unsigned int idx = clkspec->args[0];
747
748 if (idx >= vc5->chip_info->clk_out_cnt)
749 return ERR_PTR(-EINVAL);
750
751 return &vc5->clk_out[idx].hw;
752}
753
754static int vc5_map_index_to_output(const enum vc5_model model,
755 const unsigned int n)
756{
757 switch (model) {
758 case IDT_VC5_5P49V5933:
759 return (n == 0) ? 0 : 3;
760 case IDT_VC5_5P49V5923:
761 case IDT_VC5_5P49V5925:
762 case IDT_VC5_5P49V5935:
763 case IDT_VC6_5P49V6901:
764 case IDT_VC6_5P49V6965:
765 case IDT_VC6_5P49V6975:
766 default:
767 return n;
768 }
769}
770
771static int vc5_update_mode(struct device_node *np_output,
772 struct vc5_out_data *clk_out)
773{
774 u32 value;
775
776 if (!of_property_read_u32(np_output, "idt,mode", &value)) {
777 clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_CFG_MASK;
778 switch (value) {
779 case VC5_CLK_OUTPUT_CFG0_CFG_LVPECL:
780 case VC5_CLK_OUTPUT_CFG0_CFG_CMOS:
781 case VC5_CLK_OUTPUT_CFG0_CFG_HCSL33:
782 case VC5_CLK_OUTPUT_CFG0_CFG_LVDS:
783 case VC5_CLK_OUTPUT_CFG0_CFG_CMOS2:
784 case VC5_CLK_OUTPUT_CFG0_CFG_CMOSD:
785 case VC5_CLK_OUTPUT_CFG0_CFG_HCSL25:
786 clk_out->clk_output_cfg0 |=
787 value << VC5_CLK_OUTPUT_CFG0_CFG_SHIFT;
788 break;
789 default:
790 return -EINVAL;
791 }
792 }
793 return 0;
794}
795
796static int vc5_update_power(struct device_node *np_output,
797 struct vc5_out_data *clk_out)
798{
799 u32 value;
800
801 if (!of_property_read_u32(np_output, "idt,voltage-microvolt",
802 &value)) {
803 clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_PWR_MASK;
804 switch (value) {
805 case 1800000:
806 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_18;
807 break;
808 case 2500000:
809 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_25;
810 break;
811 case 3300000:
812 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_33;
813 break;
814 default:
815 return -EINVAL;
816 }
817 }
818 return 0;
819}
820
821static int vc5_map_cap_value(u32 femtofarads)
822{
823 int mapped_value;
824
825 /*
826 * The datasheet explicitly states 9000 - 25000 with 0.5pF
827 * steps, but the Programmer's guide shows the steps are 0.430pF.
828 * After getting feedback from Renesas, the .5pF steps were the
829 * goal, but 430nF was the actual values.
830 * Because of this, the actual range goes to 22760 instead of 25000
831 */
832 if (femtofarads < 9000 || femtofarads > 22760)
833 return -EINVAL;
834
835 /*
836 * The Programmer's guide shows XTAL[5:0] but in reality,
837 * XTAL[0] and XTAL[1] are both LSB which makes the math
838 * strange. With clarfication from Renesas, setting the
839 * values should be simpler by ignoring XTAL[0]
840 */
841 mapped_value = DIV_ROUND_CLOSEST(femtofarads - 9000, 430);
842
843 /*
844 * Since the calculation ignores XTAL[0], there is one
845 * special case where mapped_value = 32. In reality, this means
846 * the real mapped value should be 111111b. In other cases,
847 * the mapped_value needs to be shifted 1 to the left.
848 */
849 if (mapped_value > 31)
850 mapped_value = 0x3f;
851 else
852 mapped_value <<= 1;
853
854 return mapped_value;
855}
856static int vc5_update_cap_load(struct device_node *node, struct vc5_driver_data *vc5)
857{
858 u32 value;
859 int mapped_value;
860 int ret;
861
862 if (of_property_read_u32(node, "idt,xtal-load-femtofarads", &value))
863 return 0;
864
865 mapped_value = vc5_map_cap_value(value);
866 if (mapped_value < 0)
867 return mapped_value;
868
869 /*
870 * The mapped_value is really the high 6 bits of
871 * VC5_XTAL_X1_LOAD_CAP and VC5_XTAL_X2_LOAD_CAP, so
872 * shift the value 2 places.
873 */
874 ret = regmap_update_bits(vc5->regmap, VC5_XTAL_X1_LOAD_CAP, ~0x03,
875 mapped_value << 2);
876 if (ret)
877 return ret;
878
879 return regmap_update_bits(vc5->regmap, VC5_XTAL_X2_LOAD_CAP, ~0x03,
880 mapped_value << 2);
881}
882
883static int vc5_update_slew(struct device_node *np_output,
884 struct vc5_out_data *clk_out)
885{
886 u32 value;
887
888 if (!of_property_read_u32(np_output, "idt,slew-percent", &value)) {
889 clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_SLEW_MASK;
890 switch (value) {
891 case 80:
892 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_80;
893 break;
894 case 85:
895 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_85;
896 break;
897 case 90:
898 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_90;
899 break;
900 case 100:
901 clk_out->clk_output_cfg0 |=
902 VC5_CLK_OUTPUT_CFG0_SLEW_100;
903 break;
904 default:
905 return -EINVAL;
906 }
907 }
908 return 0;
909}
910
911static int vc5_get_output_config(struct i2c_client *client,
912 struct vc5_out_data *clk_out)
913{
914 struct device_node *np_output;
915 char *child_name;
916 int ret = 0;
917
918 child_name = kasprintf(GFP_KERNEL, "OUT%d", clk_out->num + 1);
919 if (!child_name)
920 return -ENOMEM;
921
922 np_output = of_get_child_by_name(client->dev.of_node, child_name);
923 kfree(child_name);
924 if (!np_output)
925 return 0;
926
927 ret = vc5_update_mode(np_output, clk_out);
928 if (ret)
929 goto output_error;
930
931 ret = vc5_update_power(np_output, clk_out);
932 if (ret)
933 goto output_error;
934
935 ret = vc5_update_slew(np_output, clk_out);
936
937output_error:
938 if (ret) {
939 dev_err(&client->dev,
940 "Invalid clock output configuration OUT%d\n",
941 clk_out->num + 1);
942 }
943
944 of_node_put(np_output);
945
946 return ret;
947}
948
949static const struct of_device_id clk_vc5_of_match[];
950
951static int vc5_probe(struct i2c_client *client)
952{
953 unsigned int oe, sd, src_mask = 0, src_val = 0;
954 struct vc5_driver_data *vc5;
955 struct clk_init_data init;
956 const char *parent_names[2];
957 unsigned int n, idx = 0;
958 int ret;
959
960 vc5 = devm_kzalloc(&client->dev, sizeof(*vc5), GFP_KERNEL);
961 if (!vc5)
962 return -ENOMEM;
963
964 i2c_set_clientdata(client, vc5);
965 vc5->client = client;
966 vc5->chip_info = i2c_get_match_data(client);
967
968 vc5->pin_xin = devm_clk_get(&client->dev, "xin");
969 if (PTR_ERR(vc5->pin_xin) == -EPROBE_DEFER)
970 return -EPROBE_DEFER;
971
972 vc5->pin_clkin = devm_clk_get(&client->dev, "clkin");
973 if (PTR_ERR(vc5->pin_clkin) == -EPROBE_DEFER)
974 return -EPROBE_DEFER;
975
976 vc5->regmap = devm_regmap_init_i2c(client, &vc5_regmap_config);
977 if (IS_ERR(vc5->regmap))
978 return dev_err_probe(&client->dev, PTR_ERR(vc5->regmap),
979 "failed to allocate register map\n");
980
981 ret = of_property_read_u32(client->dev.of_node, "idt,shutdown", &sd);
982 if (!ret) {
983 src_mask |= VC5_PRIM_SRC_SHDN_EN_GBL_SHDN;
984 if (sd)
985 src_val |= VC5_PRIM_SRC_SHDN_EN_GBL_SHDN;
986 } else if (ret != -EINVAL) {
987 return dev_err_probe(&client->dev, ret,
988 "could not read idt,shutdown\n");
989 }
990
991 ret = of_property_read_u32(client->dev.of_node,
992 "idt,output-enable-active", &oe);
993 if (!ret) {
994 src_mask |= VC5_PRIM_SRC_SHDN_SP;
995 if (oe)
996 src_val |= VC5_PRIM_SRC_SHDN_SP;
997 } else if (ret != -EINVAL) {
998 return dev_err_probe(&client->dev, ret,
999 "could not read idt,output-enable-active\n");
1000 }
1001
1002 ret = regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, src_mask,
1003 src_val);
1004 if (ret)
1005 return ret;
1006
1007 /* Register clock input mux */
1008 memset(&init, 0, sizeof(init));
1009
1010 if (!IS_ERR(vc5->pin_xin)) {
1011 vc5->clk_mux_ins |= VC5_MUX_IN_XIN;
1012 parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin);
1013 } else if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL) {
1014 vc5->pin_xin = clk_register_fixed_rate(&client->dev,
1015 "internal-xtal", NULL,
1016 0, 25000000);
1017 if (IS_ERR(vc5->pin_xin))
1018 return PTR_ERR(vc5->pin_xin);
1019 vc5->clk_mux_ins |= VC5_MUX_IN_XIN;
1020 parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin);
1021 }
1022
1023 if (!IS_ERR(vc5->pin_clkin)) {
1024 vc5->clk_mux_ins |= VC5_MUX_IN_CLKIN;
1025 parent_names[init.num_parents++] =
1026 __clk_get_name(vc5->pin_clkin);
1027 }
1028
1029 if (!init.num_parents)
1030 return dev_err_probe(&client->dev, -EINVAL,
1031 "no input clock specified!\n");
1032
1033 /* Configure Optional Loading Capacitance for external XTAL */
1034 if (!(vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)) {
1035 ret = vc5_update_cap_load(client->dev.of_node, vc5);
1036 if (ret)
1037 goto err_clk_register;
1038 }
1039
1040 init.name = kasprintf(GFP_KERNEL, "%pOFn.mux", client->dev.of_node);
1041 if (!init.name) {
1042 ret = -ENOMEM;
1043 goto err_clk;
1044 }
1045
1046 init.ops = &vc5_mux_ops;
1047 init.flags = 0;
1048 init.parent_names = parent_names;
1049 vc5->clk_mux.init = &init;
1050 ret = devm_clk_hw_register(&client->dev, &vc5->clk_mux);
1051 if (ret)
1052 goto err_clk_register;
1053 kfree(init.name); /* clock framework made a copy of the name */
1054
1055 if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL) {
1056 /* Register frequency doubler */
1057 memset(&init, 0, sizeof(init));
1058 init.name = kasprintf(GFP_KERNEL, "%pOFn.dbl",
1059 client->dev.of_node);
1060 if (!init.name) {
1061 ret = -ENOMEM;
1062 goto err_clk;
1063 }
1064 init.ops = &vc5_dbl_ops;
1065 init.flags = CLK_SET_RATE_PARENT;
1066 init.parent_names = parent_names;
1067 parent_names[0] = clk_hw_get_name(&vc5->clk_mux);
1068 init.num_parents = 1;
1069 vc5->clk_mul.init = &init;
1070 ret = devm_clk_hw_register(&client->dev, &vc5->clk_mul);
1071 if (ret)
1072 goto err_clk_register;
1073 kfree(init.name); /* clock framework made a copy of the name */
1074 }
1075
1076 /* Register PFD */
1077 memset(&init, 0, sizeof(init));
1078 init.name = kasprintf(GFP_KERNEL, "%pOFn.pfd", client->dev.of_node);
1079 if (!init.name) {
1080 ret = -ENOMEM;
1081 goto err_clk;
1082 }
1083 init.ops = &vc5_pfd_ops;
1084 init.flags = CLK_SET_RATE_PARENT;
1085 init.parent_names = parent_names;
1086 if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL)
1087 parent_names[0] = clk_hw_get_name(&vc5->clk_mul);
1088 else
1089 parent_names[0] = clk_hw_get_name(&vc5->clk_mux);
1090 init.num_parents = 1;
1091 vc5->clk_pfd.init = &init;
1092 ret = devm_clk_hw_register(&client->dev, &vc5->clk_pfd);
1093 if (ret)
1094 goto err_clk_register;
1095 kfree(init.name); /* clock framework made a copy of the name */
1096
1097 /* Register PLL */
1098 memset(&init, 0, sizeof(init));
1099 init.name = kasprintf(GFP_KERNEL, "%pOFn.pll", client->dev.of_node);
1100 if (!init.name) {
1101 ret = -ENOMEM;
1102 goto err_clk;
1103 }
1104 init.ops = &vc5_pll_ops;
1105 init.flags = CLK_SET_RATE_PARENT;
1106 init.parent_names = parent_names;
1107 parent_names[0] = clk_hw_get_name(&vc5->clk_pfd);
1108 init.num_parents = 1;
1109 vc5->clk_pll.num = 0;
1110 vc5->clk_pll.vc5 = vc5;
1111 vc5->clk_pll.hw.init = &init;
1112 ret = devm_clk_hw_register(&client->dev, &vc5->clk_pll.hw);
1113 if (ret)
1114 goto err_clk_register;
1115 kfree(init.name); /* clock framework made a copy of the name */
1116
1117 /* Register FODs */
1118 for (n = 0; n < vc5->chip_info->clk_fod_cnt; n++) {
1119 idx = vc5_map_index_to_output(vc5->chip_info->model, n);
1120 memset(&init, 0, sizeof(init));
1121 init.name = kasprintf(GFP_KERNEL, "%pOFn.fod%d",
1122 client->dev.of_node, idx);
1123 if (!init.name) {
1124 ret = -ENOMEM;
1125 goto err_clk;
1126 }
1127 init.ops = &vc5_fod_ops;
1128 init.flags = CLK_SET_RATE_PARENT;
1129 init.parent_names = parent_names;
1130 parent_names[0] = clk_hw_get_name(&vc5->clk_pll.hw);
1131 init.num_parents = 1;
1132 vc5->clk_fod[n].num = idx;
1133 vc5->clk_fod[n].vc5 = vc5;
1134 vc5->clk_fod[n].hw.init = &init;
1135 ret = devm_clk_hw_register(&client->dev, &vc5->clk_fod[n].hw);
1136 if (ret)
1137 goto err_clk_register;
1138 kfree(init.name); /* clock framework made a copy of the name */
1139 }
1140
1141 /* Register MUX-connected OUT0_I2C_SELB output */
1142 memset(&init, 0, sizeof(init));
1143 init.name = kasprintf(GFP_KERNEL, "%pOFn.out0_sel_i2cb",
1144 client->dev.of_node);
1145 if (!init.name) {
1146 ret = -ENOMEM;
1147 goto err_clk;
1148 }
1149 init.ops = &vc5_clk_out_ops;
1150 init.flags = CLK_SET_RATE_PARENT;
1151 init.parent_names = parent_names;
1152 parent_names[0] = clk_hw_get_name(&vc5->clk_mux);
1153 init.num_parents = 1;
1154 vc5->clk_out[0].num = idx;
1155 vc5->clk_out[0].vc5 = vc5;
1156 vc5->clk_out[0].hw.init = &init;
1157 ret = devm_clk_hw_register(&client->dev, &vc5->clk_out[0].hw);
1158 if (ret)
1159 goto err_clk_register;
1160 kfree(init.name); /* clock framework made a copy of the name */
1161
1162 /* Register FOD-connected OUTx outputs */
1163 for (n = 1; n < vc5->chip_info->clk_out_cnt; n++) {
1164 idx = vc5_map_index_to_output(vc5->chip_info->model, n - 1);
1165 parent_names[0] = clk_hw_get_name(&vc5->clk_fod[idx].hw);
1166 if (n == 1)
1167 parent_names[1] = clk_hw_get_name(&vc5->clk_mux);
1168 else
1169 parent_names[1] =
1170 clk_hw_get_name(&vc5->clk_out[n - 1].hw);
1171
1172 memset(&init, 0, sizeof(init));
1173 init.name = kasprintf(GFP_KERNEL, "%pOFn.out%d",
1174 client->dev.of_node, idx + 1);
1175 if (!init.name) {
1176 ret = -ENOMEM;
1177 goto err_clk;
1178 }
1179 init.ops = &vc5_clk_out_ops;
1180 init.flags = CLK_SET_RATE_PARENT;
1181 init.parent_names = parent_names;
1182 init.num_parents = 2;
1183 vc5->clk_out[n].num = idx;
1184 vc5->clk_out[n].vc5 = vc5;
1185 vc5->clk_out[n].hw.init = &init;
1186 ret = devm_clk_hw_register(&client->dev, &vc5->clk_out[n].hw);
1187 if (ret)
1188 goto err_clk_register;
1189 kfree(init.name); /* clock framework made a copy of the name */
1190
1191 /* Fetch Clock Output configuration from DT (if specified) */
1192 ret = vc5_get_output_config(client, &vc5->clk_out[n]);
1193 if (ret)
1194 goto err_clk;
1195 }
1196
1197 ret = of_clk_add_hw_provider(client->dev.of_node, vc5_of_clk_get, vc5);
1198 if (ret) {
1199 dev_err_probe(&client->dev, ret,
1200 "unable to add clk provider\n");
1201 goto err_clk;
1202 }
1203
1204 return 0;
1205
1206err_clk_register:
1207 dev_err_probe(&client->dev, ret,
1208 "unable to register %s\n", init.name);
1209 kfree(init.name); /* clock framework made a copy of the name */
1210err_clk:
1211 if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)
1212 clk_unregister_fixed_rate(vc5->pin_xin);
1213 return ret;
1214}
1215
1216static void vc5_remove(struct i2c_client *client)
1217{
1218 struct vc5_driver_data *vc5 = i2c_get_clientdata(client);
1219
1220 of_clk_del_provider(client->dev.of_node);
1221
1222 if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)
1223 clk_unregister_fixed_rate(vc5->pin_xin);
1224}
1225
1226static int __maybe_unused vc5_suspend(struct device *dev)
1227{
1228 struct vc5_driver_data *vc5 = dev_get_drvdata(dev);
1229
1230 regcache_cache_only(vc5->regmap, true);
1231 regcache_mark_dirty(vc5->regmap);
1232
1233 return 0;
1234}
1235
1236static int __maybe_unused vc5_resume(struct device *dev)
1237{
1238 struct vc5_driver_data *vc5 = dev_get_drvdata(dev);
1239 int ret;
1240
1241 regcache_cache_only(vc5->regmap, false);
1242 ret = regcache_sync(vc5->regmap);
1243 if (ret)
1244 dev_err(dev, "Failed to restore register map: %d\n", ret);
1245 return ret;
1246}
1247
1248static const struct vc5_chip_info idt_5p49v5923_info = {
1249 .model = IDT_VC5_5P49V5923,
1250 .clk_fod_cnt = 2,
1251 .clk_out_cnt = 3,
1252 .flags = 0,
1253 .vco_max = 3000000000UL,
1254};
1255
1256static const struct vc5_chip_info idt_5p49v5925_info = {
1257 .model = IDT_VC5_5P49V5925,
1258 .clk_fod_cnt = 4,
1259 .clk_out_cnt = 5,
1260 .flags = 0,
1261 .vco_max = 3000000000UL,
1262};
1263
1264static const struct vc5_chip_info idt_5p49v5933_info = {
1265 .model = IDT_VC5_5P49V5933,
1266 .clk_fod_cnt = 2,
1267 .clk_out_cnt = 3,
1268 .flags = VC5_HAS_INTERNAL_XTAL,
1269 .vco_max = 3000000000UL,
1270};
1271
1272static const struct vc5_chip_info idt_5p49v5935_info = {
1273 .model = IDT_VC5_5P49V5935,
1274 .clk_fod_cnt = 4,
1275 .clk_out_cnt = 5,
1276 .flags = VC5_HAS_INTERNAL_XTAL,
1277 .vco_max = 3000000000UL,
1278};
1279
1280static const struct vc5_chip_info idt_5p49v60_info = {
1281 .model = IDT_VC6_5P49V60,
1282 .clk_fod_cnt = 4,
1283 .clk_out_cnt = 5,
1284 .flags = VC5_HAS_PFD_FREQ_DBL | VC5_HAS_BYPASS_SYNC_BIT,
1285 .vco_max = 2700000000UL,
1286};
1287
1288static const struct vc5_chip_info idt_5p49v6901_info = {
1289 .model = IDT_VC6_5P49V6901,
1290 .clk_fod_cnt = 4,
1291 .clk_out_cnt = 5,
1292 .flags = VC5_HAS_PFD_FREQ_DBL | VC5_HAS_BYPASS_SYNC_BIT,
1293 .vco_max = 3000000000UL,
1294};
1295
1296static const struct vc5_chip_info idt_5p49v6965_info = {
1297 .model = IDT_VC6_5P49V6965,
1298 .clk_fod_cnt = 4,
1299 .clk_out_cnt = 5,
1300 .flags = VC5_HAS_BYPASS_SYNC_BIT,
1301 .vco_max = 3000000000UL,
1302};
1303
1304static const struct vc5_chip_info idt_5p49v6975_info = {
1305 .model = IDT_VC6_5P49V6975,
1306 .clk_fod_cnt = 4,
1307 .clk_out_cnt = 5,
1308 .flags = VC5_HAS_BYPASS_SYNC_BIT | VC5_HAS_INTERNAL_XTAL,
1309 .vco_max = 3000000000UL,
1310};
1311
1312static const struct i2c_device_id vc5_id[] = {
1313 { .name = "5p49v5923", .driver_data = (kernel_ulong_t)&idt_5p49v5923_info },
1314 { .name = "5p49v5925", .driver_data = (kernel_ulong_t)&idt_5p49v5925_info },
1315 { .name = "5p49v5933", .driver_data = (kernel_ulong_t)&idt_5p49v5933_info },
1316 { .name = "5p49v5935", .driver_data = (kernel_ulong_t)&idt_5p49v5935_info },
1317 { .name = "5p49v60", .driver_data = (kernel_ulong_t)&idt_5p49v60_info },
1318 { .name = "5p49v6901", .driver_data = (kernel_ulong_t)&idt_5p49v6901_info },
1319 { .name = "5p49v6965", .driver_data = (kernel_ulong_t)&idt_5p49v6965_info },
1320 { .name = "5p49v6975", .driver_data = (kernel_ulong_t)&idt_5p49v6975_info },
1321 { }
1322};
1323MODULE_DEVICE_TABLE(i2c, vc5_id);
1324
1325static const struct of_device_id clk_vc5_of_match[] = {
1326 { .compatible = "idt,5p49v5923", .data = &idt_5p49v5923_info },
1327 { .compatible = "idt,5p49v5925", .data = &idt_5p49v5925_info },
1328 { .compatible = "idt,5p49v5933", .data = &idt_5p49v5933_info },
1329 { .compatible = "idt,5p49v5935", .data = &idt_5p49v5935_info },
1330 { .compatible = "idt,5p49v60", .data = &idt_5p49v60_info },
1331 { .compatible = "idt,5p49v6901", .data = &idt_5p49v6901_info },
1332 { .compatible = "idt,5p49v6965", .data = &idt_5p49v6965_info },
1333 { .compatible = "idt,5p49v6975", .data = &idt_5p49v6975_info },
1334 { },
1335};
1336MODULE_DEVICE_TABLE(of, clk_vc5_of_match);
1337
1338static SIMPLE_DEV_PM_OPS(vc5_pm_ops, vc5_suspend, vc5_resume);
1339
1340static struct i2c_driver vc5_driver = {
1341 .driver = {
1342 .name = "vc5",
1343 .pm = &vc5_pm_ops,
1344 .of_match_table = clk_vc5_of_match,
1345 },
1346 .probe = vc5_probe,
1347 .remove = vc5_remove,
1348 .id_table = vc5_id,
1349};
1350module_i2c_driver(vc5_driver);
1351
1352MODULE_AUTHOR("Marek Vasut <[email protected]>");
1353MODULE_DESCRIPTION("IDT VersaClock 5 driver");
1354MODULE_LICENSE("GPL");