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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * TI Clock driver internal definitions
4 *
5 * Copyright (C) 2014 Texas Instruments, Inc
6 * Tero Kristo ([email protected])
7 */
8#ifndef __DRIVERS_CLK_TI_CLOCK__
9#define __DRIVERS_CLK_TI_CLOCK__
10
11struct clk_omap_divider {
12 struct clk_hw hw;
13 struct clk_omap_reg reg;
14 u8 shift;
15 u8 flags;
16 s8 latch;
17 u16 min;
18 u16 max;
19 u16 mask;
20 const struct clk_div_table *table;
21 u32 context;
22};
23
24#define to_clk_omap_divider(_hw) container_of(_hw, struct clk_omap_divider, hw)
25
26struct clk_omap_mux {
27 struct clk_hw hw;
28 struct clk_omap_reg reg;
29 u32 *table;
30 u32 mask;
31 u8 shift;
32 s8 latch;
33 u8 flags;
34 u8 saved_parent;
35};
36
37#define to_clk_omap_mux(_hw) container_of(_hw, struct clk_omap_mux, hw)
38
39enum {
40 TI_CLK_FIXED,
41 TI_CLK_MUX,
42 TI_CLK_DIVIDER,
43 TI_CLK_COMPOSITE,
44 TI_CLK_FIXED_FACTOR,
45 TI_CLK_GATE,
46 TI_CLK_DPLL,
47};
48
49/* Global flags */
50#define CLKF_INDEX_POWER_OF_TWO (1 << 0)
51#define CLKF_INDEX_STARTS_AT_ONE (1 << 1)
52#define CLKF_SET_RATE_PARENT (1 << 2)
53#define CLKF_OMAP3 (1 << 3)
54#define CLKF_AM35XX (1 << 4)
55
56/* Gate flags */
57#define CLKF_SET_BIT_TO_DISABLE (1 << 5)
58#define CLKF_INTERFACE (1 << 6)
59#define CLKF_SSI (1 << 7)
60#define CLKF_DSS (1 << 8)
61#define CLKF_HSOTGUSB (1 << 9)
62#define CLKF_WAIT (1 << 10)
63#define CLKF_NO_WAIT (1 << 11)
64#define CLKF_HSDIV (1 << 12)
65#define CLKF_CLKDM (1 << 13)
66
67/* DPLL flags */
68#define CLKF_LOW_POWER_STOP (1 << 5)
69#define CLKF_LOCK (1 << 6)
70#define CLKF_LOW_POWER_BYPASS (1 << 7)
71#define CLKF_PER (1 << 8)
72#define CLKF_CORE (1 << 9)
73#define CLKF_J_TYPE (1 << 10)
74
75/* CLKCTRL flags */
76#define CLKF_SW_SUP BIT(5)
77#define CLKF_HW_SUP BIT(6)
78#define CLKF_NO_IDLEST BIT(7)
79
80#define CLKF_SOC_MASK GENMASK(11, 8)
81
82#define CLKF_SOC_NONSEC BIT(8)
83#define CLKF_SOC_DRA72 BIT(9)
84#define CLKF_SOC_DRA74 BIT(10)
85#define CLKF_SOC_DRA76 BIT(11)
86
87#define CLK(dev, con, ck) \
88 { \
89 .lk = { \
90 .dev_id = dev, \
91 .con_id = con, \
92 }, \
93 .clk = ck, \
94 }
95
96struct ti_clk {
97 const char *name;
98 const char *clkdm_name;
99 int type;
100 void *data;
101 struct ti_clk *patch;
102 struct clk *clk;
103};
104
105struct ti_clk_mux {
106 u8 bit_shift;
107 int num_parents;
108 u16 reg;
109 u8 module;
110 const char * const *parents;
111 u16 flags;
112};
113
114struct ti_clk_divider {
115 const char *parent;
116 u8 bit_shift;
117 u16 max_div;
118 u16 reg;
119 u8 module;
120 int *dividers;
121 int num_dividers;
122 u16 flags;
123};
124
125struct ti_clk_gate {
126 const char *parent;
127 u8 bit_shift;
128 u16 reg;
129 u8 module;
130 u16 flags;
131};
132
133/* Composite clock component types */
134enum {
135 CLK_COMPONENT_TYPE_GATE = 0,
136 CLK_COMPONENT_TYPE_DIVIDER,
137 CLK_COMPONENT_TYPE_MUX,
138 CLK_COMPONENT_TYPE_MAX,
139};
140
141/**
142 * struct ti_dt_clk - OMAP DT clock alias declarations
143 * @lk: clock lookup definition
144 * @node_name: clock DT node to map to
145 */
146struct ti_dt_clk {
147 struct clk_lookup lk;
148 char *node_name;
149};
150
151#define DT_CLK(dev, con, name) \
152 { \
153 .lk = { \
154 .dev_id = dev, \
155 .con_id = con, \
156 }, \
157 .node_name = name, \
158 }
159
160/* CLKCTRL type definitions */
161struct omap_clkctrl_div_data {
162 const int *dividers;
163 int max_div;
164 u32 flags;
165};
166
167struct omap_clkctrl_bit_data {
168 u8 bit;
169 u8 type;
170 const char * const *parents;
171 const void *data;
172};
173
174struct omap_clkctrl_reg_data {
175 u16 offset;
176 const struct omap_clkctrl_bit_data *bit_data;
177 u16 flags;
178 const char *parent;
179 const char *clkdm_name;
180};
181
182struct omap_clkctrl_data {
183 u32 addr;
184 const struct omap_clkctrl_reg_data *regs;
185};
186
187extern const struct omap_clkctrl_data omap4_clkctrl_data[];
188extern const struct omap_clkctrl_data omap5_clkctrl_data[];
189extern const struct omap_clkctrl_data dra7_clkctrl_data[];
190extern const struct omap_clkctrl_data dra7_clkctrl_compat_data[];
191extern struct ti_dt_clk dra7xx_compat_clks[];
192extern const struct omap_clkctrl_data am3_clkctrl_data[];
193extern const struct omap_clkctrl_data am3_clkctrl_compat_data[];
194extern struct ti_dt_clk am33xx_compat_clks[];
195extern const struct omap_clkctrl_data am4_clkctrl_data[];
196extern const struct omap_clkctrl_data am438x_clkctrl_data[];
197extern const struct omap_clkctrl_data dm814_clkctrl_data[];
198extern const struct omap_clkctrl_data dm816_clkctrl_data[];
199
200typedef void (*ti_of_clk_init_cb_t)(void *, struct device_node *);
201
202struct clk *of_ti_clk_register(struct device_node *node, struct clk_hw *hw,
203 const char *con);
204struct clk *of_ti_clk_register_omap_hw(struct device_node *node,
205 struct clk_hw *hw, const char *con);
206const char *ti_dt_clk_name(struct device_node *np);
207int ti_clk_add_alias(struct clk *clk, const char *con);
208void ti_clk_add_aliases(void);
209
210void ti_clk_latch(struct clk_omap_reg *reg, s8 shift);
211
212struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup);
213
214int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,
215 u8 flags, struct clk_omap_divider *div);
216
217int ti_clk_get_reg_addr(struct device_node *node, int index,
218 struct clk_omap_reg *reg);
219int ti_clk_get_legacy_bit_shift(struct device_node *node);
220void ti_dt_clocks_register(struct ti_dt_clk *oclks);
221int ti_clk_retry_init(struct device_node *node, void *user,
222 ti_of_clk_init_cb_t func);
223int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);
224
225int of_ti_clk_autoidle_setup(struct device_node *node);
226void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
227
228extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
229extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
230extern const struct clk_hw_omap_ops clkhwops_wait;
231extern const struct clk_hw_omap_ops clkhwops_iclk;
232extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
233extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait;
234extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
235extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
236extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
237extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
238extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
239extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
240
241extern const struct clk_ops ti_clk_divider_ops;
242extern const struct clk_ops ti_clk_mux_ops;
243extern const struct clk_ops omap_gate_clk_ops;
244
245extern struct ti_clk_features ti_clk_features;
246
247int omap2_init_clk_clkdm(struct clk_hw *hw);
248int omap2_clkops_enable_clkdm(struct clk_hw *hw);
249void omap2_clkops_disable_clkdm(struct clk_hw *hw);
250
251int omap2_dflt_clk_enable(struct clk_hw *hw);
252void omap2_dflt_clk_disable(struct clk_hw *hw);
253int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
254void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
255 struct clk_omap_reg *other_reg,
256 u8 *other_bit);
257void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
258 struct clk_omap_reg *idlest_reg,
259 u8 *idlest_bit, u8 *idlest_val);
260
261void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
262void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
263
264u8 omap2_init_dpll_parent(struct clk_hw *hw);
265int omap3_noncore_dpll_enable(struct clk_hw *hw);
266void omap3_noncore_dpll_disable(struct clk_hw *hw);
267int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index);
268int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
269 unsigned long parent_rate);
270int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
271 unsigned long rate,
272 unsigned long parent_rate,
273 u8 index);
274int omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
275 struct clk_rate_request *req);
276int omap2_dpll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req);
277unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
278 unsigned long parent_rate);
279
280/*
281 * OMAP3_DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
282 * that are sourced by DPLL5, and both of these require this clock
283 * to be at 120 MHz for proper operation.
284 */
285#define OMAP3_DPLL5_FREQ_FOR_USBHOST 120000000
286
287unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
288int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
289 unsigned long parent_rate);
290int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
291 unsigned long parent_rate, u8 index);
292int omap3_dpll5_set_rate(struct clk_hw *hw, unsigned long rate,
293 unsigned long parent_rate);
294void omap3_clk_lock_dpll5(void);
295
296unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
297 unsigned long parent_rate);
298int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
299 struct clk_rate_request *req);
300int omap2_clk_for_each(int (*fn)(struct clk_hw_omap *hw));
301
302extern struct ti_clk_ll_ops *ti_clk_ll_ops;
303
304#endif