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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * i8253 PIT clocksource
4 */
5#include <linux/clockchips.h>
6#include <linux/init.h>
7#include <linux/io.h>
8#include <linux/spinlock.h>
9#include <linux/timex.h>
10#include <linux/module.h>
11#include <linux/i8253.h>
12#include <linux/smp.h>
13
14/*
15 * Protects access to I/O ports
16 *
17 * 0040-0043 : timer0, i8253 / i8254
18 * 0061-0061 : NMI Control Register which contains two speaker control bits.
19 */
20DEFINE_RAW_SPINLOCK(i8253_lock);
21EXPORT_SYMBOL(i8253_lock);
22
23#ifdef CONFIG_CLKSRC_I8253
24/*
25 * Since the PIT overflows every tick, its not very useful
26 * to just read by itself. So use jiffies to emulate a free
27 * running counter:
28 */
29static u64 i8253_read(struct clocksource *cs)
30{
31 static int old_count;
32 static u32 old_jifs;
33 unsigned long flags;
34 int count;
35 u32 jifs;
36
37 raw_spin_lock_irqsave(&i8253_lock, flags);
38 /*
39 * Although our caller may have the read side of jiffies_lock,
40 * this is now a seqlock, and we are cheating in this routine
41 * by having side effects on state that we cannot undo if
42 * there is a collision on the seqlock and our caller has to
43 * retry. (Namely, old_jifs and old_count.) So we must treat
44 * jiffies as volatile despite the lock. We read jiffies
45 * before latching the timer count to guarantee that although
46 * the jiffies value might be older than the count (that is,
47 * the counter may underflow between the last point where
48 * jiffies was incremented and the point where we latch the
49 * count), it cannot be newer.
50 */
51 jifs = jiffies;
52 outb_p(0x00, PIT_MODE); /* latch the count ASAP */
53 count = inb_p(PIT_CH0); /* read the latched count */
54 count |= inb_p(PIT_CH0) << 8;
55
56 /* VIA686a test code... reset the latch if count > max + 1 */
57 if (count > PIT_LATCH) {
58 outb_p(0x34, PIT_MODE);
59 outb_p(PIT_LATCH & 0xff, PIT_CH0);
60 outb_p(PIT_LATCH >> 8, PIT_CH0);
61 count = PIT_LATCH - 1;
62 }
63
64 /*
65 * It's possible for count to appear to go the wrong way for a
66 * couple of reasons:
67 *
68 * 1. The timer counter underflows, but we haven't handled the
69 * resulting interrupt and incremented jiffies yet.
70 * 2. Hardware problem with the timer, not giving us continuous time,
71 * the counter does small "jumps" upwards on some Pentium systems,
72 * (see c't 95/10 page 335 for Neptun bug.)
73 *
74 * Previous attempts to handle these cases intelligently were
75 * buggy, so we just do the simple thing now.
76 */
77 if (count > old_count && jifs == old_jifs)
78 count = old_count;
79
80 old_count = count;
81 old_jifs = jifs;
82
83 raw_spin_unlock_irqrestore(&i8253_lock, flags);
84
85 count = (PIT_LATCH - 1) - count;
86
87 return (u64)(jifs * PIT_LATCH) + count;
88}
89
90static struct clocksource i8253_cs = {
91 .name = "pit",
92 .rating = 110,
93 .read = i8253_read,
94 .mask = CLOCKSOURCE_MASK(32),
95};
96
97int __init clocksource_i8253_init(void)
98{
99 return clocksource_register_hz(&i8253_cs, PIT_TICK_RATE);
100}
101#endif
102
103#ifdef CONFIG_CLKEVT_I8253
104void clockevent_i8253_disable(void)
105{
106 guard(raw_spinlock_irqsave)(&i8253_lock);
107
108 /*
109 * Writing the MODE register should stop the counter, according to
110 * the datasheet. This appears to work on real hardware (well, on
111 * modern Intel and AMD boxes; I didn't dig the Pegasos out of the
112 * shed).
113 *
114 * However, some virtual implementations differ, and the MODE change
115 * doesn't have any effect until either the counter is written (KVM
116 * in-kernel PIT) or the next interrupt (QEMU). And in those cases,
117 * it may not stop the *count*, only the interrupts. Although in
118 * the virt case, that probably doesn't matter, as the value of the
119 * counter will only be calculated on demand if the guest reads it;
120 * it's the interrupts which cause steal time.
121 *
122 * Hyper-V apparently has a bug where even in mode 0, the IRQ keeps
123 * firing repeatedly if the counter is running. But it *does* do the
124 * right thing when the MODE register is written.
125 *
126 * So: write the MODE and then load the counter, which ensures that
127 * the IRQ is stopped on those buggy virt implementations. And then
128 * write the MODE again, which is the right way to stop it.
129 */
130 outb_p(0x30, PIT_MODE);
131 outb_p(0, PIT_CH0);
132 outb_p(0, PIT_CH0);
133
134 outb_p(0x30, PIT_MODE);
135}
136
137static int pit_shutdown(struct clock_event_device *evt)
138{
139 if (!clockevent_state_oneshot(evt) && !clockevent_state_periodic(evt))
140 return 0;
141
142 clockevent_i8253_disable();
143 return 0;
144}
145
146static int pit_set_oneshot(struct clock_event_device *evt)
147{
148 raw_spin_lock(&i8253_lock);
149 outb_p(0x38, PIT_MODE);
150 raw_spin_unlock(&i8253_lock);
151 return 0;
152}
153
154static int pit_set_periodic(struct clock_event_device *evt)
155{
156 raw_spin_lock(&i8253_lock);
157
158 /* binary, mode 2, LSB/MSB, ch 0 */
159 outb_p(0x34, PIT_MODE);
160 outb_p(PIT_LATCH & 0xff, PIT_CH0); /* LSB */
161 outb_p(PIT_LATCH >> 8, PIT_CH0); /* MSB */
162
163 raw_spin_unlock(&i8253_lock);
164 return 0;
165}
166
167/*
168 * Program the next event in oneshot mode
169 *
170 * Delta is given in PIT ticks
171 */
172static int pit_next_event(unsigned long delta, struct clock_event_device *evt)
173{
174 raw_spin_lock(&i8253_lock);
175 outb_p(delta & 0xff , PIT_CH0); /* LSB */
176 outb_p(delta >> 8 , PIT_CH0); /* MSB */
177 raw_spin_unlock(&i8253_lock);
178
179 return 0;
180}
181
182/*
183 * On UP the PIT can serve all of the possible timer functions. On SMP systems
184 * it can be solely used for the global tick.
185 */
186struct clock_event_device i8253_clockevent = {
187 .name = "pit",
188 .features = CLOCK_EVT_FEAT_PERIODIC,
189 .set_state_shutdown = pit_shutdown,
190 .set_state_periodic = pit_set_periodic,
191 .set_next_event = pit_next_event,
192};
193
194/*
195 * Initialize the conversion factor and the min/max deltas of the clock event
196 * structure and register the clock event source with the framework.
197 */
198void __init clockevent_i8253_init(bool oneshot)
199{
200 if (oneshot) {
201 i8253_clockevent.features |= CLOCK_EVT_FEAT_ONESHOT;
202 i8253_clockevent.set_state_oneshot = pit_set_oneshot;
203 }
204 /*
205 * Start pit with the boot cpu mask. x86 might make it global
206 * when it is used as broadcast device later.
207 */
208 i8253_clockevent.cpumask = cpumask_of(smp_processor_id());
209
210 clockevents_config_and_register(&i8253_clockevent, PIT_TICK_RATE,
211 0xF, 0x7FFF);
212}
213#endif