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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * linux/arch/arm/plat-omap/dmtimer.c
4 *
5 * OMAP Dual-Mode Timers
6 *
7 * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
8 * Tarun Kanti DebBarma <[email protected]>
9 * Thara Gopinath <[email protected]>
10 *
11 * dmtimer adaptation to platform_driver.
12 *
13 * Copyright (C) 2005 Nokia Corporation
14 * OMAP2 support by Juha Yrjola
15 * API improvements and OMAP2 clock framework support by Timo Teras
16 *
17 * Copyright (C) 2009 Texas Instruments
18 * Added OMAP4 support - Santosh Shilimkar <[email protected]>
19 */
20
21#include <linux/clk.h>
22#include <linux/clk-provider.h>
23#include <linux/clocksource.h>
24#include <linux/clockchips.h>
25#include <linux/cpu_pm.h>
26#include <linux/module.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/device.h>
30#include <linux/err.h>
31#include <linux/pm_runtime.h>
32#include <linux/of.h>
33#include <linux/platform_device.h>
34#include <linux/platform_data/dmtimer-omap.h>
35#include <linux/sched_clock.h>
36
37#include <clocksource/timer-ti-dm.h>
38#include <linux/delay.h>
39
40/*
41 * timer errata flags
42 *
43 * Errata i103/i767 impacts all OMAP3/4/5 devices including AM33xx. This
44 * errata prevents us from using posted mode on these devices, unless the
45 * timer counter register is never read. For more details please refer to
46 * the OMAP3/4/5 errata documents.
47 */
48#define OMAP_TIMER_ERRATA_I103_I767 0x80000000
49
50/* posted mode types */
51#define OMAP_TIMER_NONPOSTED 0x00
52#define OMAP_TIMER_POSTED 0x01
53
54/* register offsets with the write pending bit encoded */
55#define WPSHIFT 16
56
57#define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
58 | (WP_NONE << WPSHIFT))
59
60#define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \
61 | (WP_TCLR << WPSHIFT))
62
63#define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \
64 | (WP_TCRR << WPSHIFT))
65
66#define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \
67 | (WP_TLDR << WPSHIFT))
68
69#define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \
70 | (WP_TTGR << WPSHIFT))
71
72#define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \
73 | (WP_NONE << WPSHIFT))
74
75#define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \
76 | (WP_TMAR << WPSHIFT))
77
78#define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \
79 | (WP_NONE << WPSHIFT))
80
81#define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \
82 | (WP_NONE << WPSHIFT))
83
84#define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \
85 | (WP_NONE << WPSHIFT))
86
87#define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \
88 | (WP_TPIR << WPSHIFT))
89
90#define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \
91 | (WP_TNIR << WPSHIFT))
92
93#define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \
94 | (WP_TCVR << WPSHIFT))
95
96#define OMAP_TIMER_TICK_INT_MASK_SET_REG \
97 (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
98
99#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
100 (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
101
102struct timer_regs {
103 u32 ocp_cfg;
104 u32 tidr;
105 u32 tier;
106 u32 twer;
107 u32 tclr;
108 u32 tcrr;
109 u32 tldr;
110 u32 ttrg;
111 u32 twps;
112 u32 tmar;
113 u32 tcar1;
114 u32 tsicr;
115 u32 tcar2;
116 u32 tpir;
117 u32 tnir;
118 u32 tcvr;
119 u32 tocr;
120 u32 towr;
121};
122
123struct dmtimer {
124 struct omap_dm_timer cookie;
125 int id;
126 int irq;
127 struct clk *fclk;
128
129 void __iomem *io_base;
130 int irq_stat; /* TISR/IRQSTATUS interrupt status */
131 int irq_ena; /* irq enable */
132 int irq_dis; /* irq disable, only on v2 ip */
133 void __iomem *pend; /* write pending */
134 void __iomem *func_base; /* function register base */
135
136 atomic_t enabled;
137 unsigned reserved:1;
138 unsigned posted:1;
139 unsigned omap1:1;
140 struct timer_regs context;
141 int revision;
142 u32 capability;
143 u32 errata;
144 struct platform_device *pdev;
145 struct list_head node;
146 struct notifier_block nb;
147 struct notifier_block fclk_nb;
148 unsigned long fclk_rate;
149};
150
151static u32 omap_reserved_systimers;
152static LIST_HEAD(omap_timer_list);
153static DEFINE_SPINLOCK(dm_timer_lock);
154
155struct dmtimer_clocksource {
156 struct clocksource dev;
157 struct dmtimer *timer;
158 unsigned int loadval;
159};
160
161struct omap_dm_timer_clockevent {
162 struct clock_event_device dev;
163 struct dmtimer *timer;
164 u32 period;
165};
166
167static bool omap_dm_timer_clockevent_setup;
168static void __iomem *omap_dm_timer_sched_clock_counter;
169
170enum {
171 REQUEST_ANY = 0,
172 REQUEST_BY_ID,
173 REQUEST_BY_CAP,
174 REQUEST_BY_NODE,
175};
176
177/**
178 * dmtimer_read - read timer registers in posted and non-posted mode
179 * @timer: timer pointer over which read operation to perform
180 * @reg: lowest byte holds the register offset
181 *
182 * The posted mode bit is encoded in reg. Note that in posted mode, write
183 * pending bit must be checked. Otherwise a read of a non completed write
184 * will produce an error.
185 */
186static inline u32 dmtimer_read(struct dmtimer *timer, u32 reg)
187{
188 u16 wp, offset;
189
190 wp = reg >> WPSHIFT;
191 offset = reg & 0xff;
192
193 /* Wait for a possible write pending bit in posted mode */
194 if (wp && timer->posted)
195 while (readl_relaxed(timer->pend) & wp)
196 cpu_relax();
197
198 return readl_relaxed(timer->func_base + offset);
199}
200
201/**
202 * dmtimer_write - write timer registers in posted and non-posted mode
203 * @timer: timer pointer over which write operation is to perform
204 * @reg: lowest byte holds the register offset
205 * @val: data to write into the register
206 *
207 * The posted mode bit is encoded in reg. Note that in posted mode, the write
208 * pending bit must be checked. Otherwise a write on a register which has a
209 * pending write will be lost.
210 */
211static inline void dmtimer_write(struct dmtimer *timer, u32 reg, u32 val)
212{
213 u16 wp, offset;
214
215 wp = reg >> WPSHIFT;
216 offset = reg & 0xff;
217
218 /* Wait for a possible write pending bit in posted mode */
219 if (wp && timer->posted)
220 while (readl_relaxed(timer->pend) & wp)
221 cpu_relax();
222
223 writel_relaxed(val, timer->func_base + offset);
224}
225
226static inline void __omap_dm_timer_init_regs(struct dmtimer *timer)
227{
228 u32 tidr;
229
230 /* Assume v1 ip if bits [31:16] are zero */
231 tidr = readl_relaxed(timer->io_base);
232 if (!(tidr >> 16)) {
233 timer->revision = 1;
234 timer->irq_stat = OMAP_TIMER_V1_STAT_OFFSET;
235 timer->irq_ena = OMAP_TIMER_V1_INT_EN_OFFSET;
236 timer->irq_dis = OMAP_TIMER_V1_INT_EN_OFFSET;
237 timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
238 timer->func_base = timer->io_base;
239 } else {
240 timer->revision = 2;
241 timer->irq_stat = OMAP_TIMER_V2_IRQSTATUS - OMAP_TIMER_V2_FUNC_OFFSET;
242 timer->irq_ena = OMAP_TIMER_V2_IRQENABLE_SET - OMAP_TIMER_V2_FUNC_OFFSET;
243 timer->irq_dis = OMAP_TIMER_V2_IRQENABLE_CLR - OMAP_TIMER_V2_FUNC_OFFSET;
244 timer->pend = timer->io_base +
245 _OMAP_TIMER_WRITE_PEND_OFFSET +
246 OMAP_TIMER_V2_FUNC_OFFSET;
247 timer->func_base = timer->io_base + OMAP_TIMER_V2_FUNC_OFFSET;
248 }
249}
250
251/*
252 * __omap_dm_timer_enable_posted - enables write posted mode
253 * @timer: pointer to timer instance handle
254 *
255 * Enables the write posted mode for the timer. When posted mode is enabled
256 * writes to certain timer registers are immediately acknowledged by the
257 * internal bus and hence prevents stalling the CPU waiting for the write to
258 * complete. Enabling this feature can improve performance for writing to the
259 * timer registers.
260 */
261static inline void __omap_dm_timer_enable_posted(struct dmtimer *timer)
262{
263 if (timer->posted)
264 return;
265
266 if (timer->errata & OMAP_TIMER_ERRATA_I103_I767) {
267 timer->posted = OMAP_TIMER_NONPOSTED;
268 dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0);
269 return;
270 }
271
272 dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, OMAP_TIMER_CTRL_POSTED);
273 timer->context.tsicr = OMAP_TIMER_CTRL_POSTED;
274 timer->posted = OMAP_TIMER_POSTED;
275}
276
277static inline void __omap_dm_timer_stop(struct dmtimer *timer)
278{
279 u32 l;
280
281 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
282 if (l & OMAP_TIMER_CTRL_ST) {
283 l &= ~0x1;
284 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
285#ifdef CONFIG_ARCH_OMAP2PLUS
286 /* Readback to make sure write has completed */
287 dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
288 /*
289 * Wait for functional clock period x 3.5 to make sure that
290 * timer is stopped
291 */
292 udelay(3500000 / timer->fclk_rate + 1);
293#endif
294 }
295
296 /* Ack possibly pending interrupt */
297 dmtimer_write(timer, timer->irq_stat, OMAP_TIMER_INT_OVERFLOW);
298}
299
300static inline void __omap_dm_timer_int_enable(struct dmtimer *timer,
301 unsigned int value)
302{
303 dmtimer_write(timer, timer->irq_ena, value);
304 dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value);
305}
306
307static inline unsigned int
308__omap_dm_timer_read_counter(struct dmtimer *timer)
309{
310 return dmtimer_read(timer, OMAP_TIMER_COUNTER_REG);
311}
312
313static inline void __omap_dm_timer_write_status(struct dmtimer *timer,
314 unsigned int value)
315{
316 dmtimer_write(timer, timer->irq_stat, value);
317}
318
319static void omap_timer_restore_context(struct dmtimer *timer)
320{
321 dmtimer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, timer->context.ocp_cfg);
322
323 dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, timer->context.twer);
324 dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, timer->context.tcrr);
325 dmtimer_write(timer, OMAP_TIMER_LOAD_REG, timer->context.tldr);
326 dmtimer_write(timer, OMAP_TIMER_MATCH_REG, timer->context.tmar);
327 dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, timer->context.tsicr);
328 dmtimer_write(timer, timer->irq_ena, timer->context.tier);
329 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, timer->context.tclr);
330}
331
332static void omap_timer_save_context(struct dmtimer *timer)
333{
334 timer->context.ocp_cfg = dmtimer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET);
335
336 timer->context.tclr = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
337 timer->context.twer = dmtimer_read(timer, OMAP_TIMER_WAKEUP_EN_REG);
338 timer->context.tldr = dmtimer_read(timer, OMAP_TIMER_LOAD_REG);
339 timer->context.tmar = dmtimer_read(timer, OMAP_TIMER_MATCH_REG);
340 timer->context.tier = dmtimer_read(timer, timer->irq_ena);
341 timer->context.tsicr = dmtimer_read(timer, OMAP_TIMER_IF_CTRL_REG);
342}
343
344static int omap_timer_context_notifier(struct notifier_block *nb,
345 unsigned long cmd, void *v)
346{
347 struct dmtimer *timer;
348
349 timer = container_of(nb, struct dmtimer, nb);
350
351 switch (cmd) {
352 case CPU_CLUSTER_PM_ENTER:
353 if ((timer->capability & OMAP_TIMER_ALWON) ||
354 !atomic_read(&timer->enabled))
355 break;
356 omap_timer_save_context(timer);
357 break;
358 case CPU_CLUSTER_PM_ENTER_FAILED: /* No need to restore context */
359 break;
360 case CPU_CLUSTER_PM_EXIT:
361 if ((timer->capability & OMAP_TIMER_ALWON) ||
362 !atomic_read(&timer->enabled))
363 break;
364 omap_timer_restore_context(timer);
365 break;
366 }
367
368 return NOTIFY_OK;
369}
370
371static int omap_timer_fclk_notifier(struct notifier_block *nb,
372 unsigned long event, void *data)
373{
374 struct clk_notifier_data *clk_data = data;
375 struct dmtimer *timer = container_of(nb, struct dmtimer, fclk_nb);
376
377 switch (event) {
378 case POST_RATE_CHANGE:
379 timer->fclk_rate = clk_data->new_rate;
380 return NOTIFY_OK;
381 default:
382 return NOTIFY_DONE;
383 }
384}
385
386static int omap_dm_timer_reset(struct dmtimer *timer)
387{
388 u32 l, timeout = 100000;
389
390 if (timer->revision != 1)
391 return -EINVAL;
392
393 dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
394
395 do {
396 l = dmtimer_read(timer, OMAP_TIMER_V1_SYS_STAT_OFFSET);
397 } while (!l && timeout--);
398
399 if (!timeout) {
400 dev_err(&timer->pdev->dev, "Timer failed to reset\n");
401 return -ETIMEDOUT;
402 }
403
404 /* Configure timer for smart-idle mode */
405 l = dmtimer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET);
406 l |= 0x2 << 0x3;
407 dmtimer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l);
408
409 timer->posted = 0;
410
411 return 0;
412}
413
414/*
415 * Functions exposed to PWM and remoteproc drivers via platform_data.
416 * Do not use these in the driver, these will get deprecated and will
417 * will be replaced by Linux generic framework functions such as
418 * chained interrupts and clock framework.
419 */
420static struct dmtimer *to_dmtimer(struct omap_dm_timer *cookie)
421{
422 if (!cookie)
423 return NULL;
424
425 return container_of(cookie, struct dmtimer, cookie);
426}
427
428static int omap_dm_timer_set_source(struct omap_dm_timer *cookie, int source)
429{
430 int ret;
431 const char *parent_name;
432 struct clk *parent;
433 struct dmtimer_platform_data *pdata;
434 struct dmtimer *timer;
435
436 timer = to_dmtimer(cookie);
437 if (unlikely(!timer) || IS_ERR(timer->fclk))
438 return -EINVAL;
439
440 switch (source) {
441 case OMAP_TIMER_SRC_SYS_CLK:
442 parent_name = "timer_sys_ck";
443 break;
444 case OMAP_TIMER_SRC_32_KHZ:
445 parent_name = "timer_32k_ck";
446 break;
447 case OMAP_TIMER_SRC_EXT_CLK:
448 parent_name = "timer_ext_ck";
449 break;
450 default:
451 return -EINVAL;
452 }
453
454 pdata = timer->pdev->dev.platform_data;
455
456 /*
457 * FIXME: Used for OMAP1 devices only because they do not currently
458 * use the clock framework to set the parent clock. To be removed
459 * once OMAP1 migrated to using clock framework for dmtimers
460 */
461 if (timer->omap1 && pdata && pdata->set_timer_src)
462 return pdata->set_timer_src(timer->pdev, source);
463
464#if defined(CONFIG_COMMON_CLK)
465 /* Check if the clock has configurable parents */
466 if (clk_hw_get_num_parents(__clk_get_hw(timer->fclk)) < 2)
467 return 0;
468#endif
469
470 parent = clk_get(&timer->pdev->dev, parent_name);
471 if (IS_ERR(parent)) {
472 pr_err("%s: %s not found\n", __func__, parent_name);
473 return -EINVAL;
474 }
475
476 ret = clk_set_parent(timer->fclk, parent);
477 if (ret < 0)
478 pr_err("%s: failed to set %s as parent\n", __func__,
479 parent_name);
480
481 clk_put(parent);
482
483 return ret;
484}
485
486static void omap_dm_timer_enable(struct omap_dm_timer *cookie)
487{
488 struct dmtimer *timer = to_dmtimer(cookie);
489 struct device *dev = &timer->pdev->dev;
490 int rc;
491
492 rc = pm_runtime_resume_and_get(dev);
493 if (rc)
494 dev_err(dev, "could not enable timer\n");
495}
496
497static void omap_dm_timer_disable(struct omap_dm_timer *cookie)
498{
499 struct dmtimer *timer = to_dmtimer(cookie);
500 struct device *dev = &timer->pdev->dev;
501
502 pm_runtime_put_sync(dev);
503}
504
505static int omap_dm_timer_prepare(struct dmtimer *timer)
506{
507 struct device *dev = &timer->pdev->dev;
508 int rc;
509
510 rc = pm_runtime_resume_and_get(dev);
511 if (rc)
512 return rc;
513
514 if (timer->capability & OMAP_TIMER_NEEDS_RESET) {
515 rc = omap_dm_timer_reset(timer);
516 if (rc) {
517 pm_runtime_put_sync(dev);
518 return rc;
519 }
520 }
521
522 __omap_dm_timer_enable_posted(timer);
523 pm_runtime_put_sync(dev);
524
525 return 0;
526}
527
528static inline u32 omap_dm_timer_reserved_systimer(int id)
529{
530 return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0;
531}
532
533static struct dmtimer *_omap_dm_timer_request(int req_type, void *data)
534{
535 struct dmtimer *timer = NULL, *t;
536 struct device_node *np = NULL;
537 unsigned long flags;
538 u32 cap = 0;
539 int id = 0;
540
541 switch (req_type) {
542 case REQUEST_BY_ID:
543 id = *(int *)data;
544 break;
545 case REQUEST_BY_CAP:
546 cap = *(u32 *)data;
547 break;
548 case REQUEST_BY_NODE:
549 np = (struct device_node *)data;
550 break;
551 default:
552 /* REQUEST_ANY */
553 break;
554 }
555
556 spin_lock_irqsave(&dm_timer_lock, flags);
557 list_for_each_entry(t, &omap_timer_list, node) {
558 if (t->reserved)
559 continue;
560
561 switch (req_type) {
562 case REQUEST_BY_ID:
563 if (id == t->pdev->id) {
564 timer = t;
565 timer->reserved = 1;
566 goto found;
567 }
568 break;
569 case REQUEST_BY_CAP:
570 if (cap == (t->capability & cap)) {
571 /*
572 * If timer is not NULL, we have already found
573 * one timer. But it was not an exact match
574 * because it had more capabilities than what
575 * was required. Therefore, unreserve the last
576 * timer found and see if this one is a better
577 * match.
578 */
579 if (timer)
580 timer->reserved = 0;
581 timer = t;
582 timer->reserved = 1;
583
584 /* Exit loop early if we find an exact match */
585 if (t->capability == cap)
586 goto found;
587 }
588 break;
589 case REQUEST_BY_NODE:
590 if (np == t->pdev->dev.of_node) {
591 timer = t;
592 timer->reserved = 1;
593 goto found;
594 }
595 break;
596 default:
597 /* REQUEST_ANY */
598 timer = t;
599 timer->reserved = 1;
600 goto found;
601 }
602 }
603found:
604 spin_unlock_irqrestore(&dm_timer_lock, flags);
605
606 if (timer && omap_dm_timer_prepare(timer)) {
607 timer->reserved = 0;
608 timer = NULL;
609 }
610
611 if (!timer)
612 pr_debug("%s: timer request failed!\n", __func__);
613
614 return timer;
615}
616
617static struct omap_dm_timer *omap_dm_timer_request(void)
618{
619 struct dmtimer *timer;
620
621 timer = _omap_dm_timer_request(REQUEST_ANY, NULL);
622 if (!timer)
623 return NULL;
624
625 return &timer->cookie;
626}
627
628static struct omap_dm_timer *omap_dm_timer_request_specific(int id)
629{
630 struct dmtimer *timer;
631
632 /* Requesting timer by ID is not supported when device tree is used */
633 if (of_have_populated_dt()) {
634 pr_warn("%s: Please use omap_dm_timer_request_by_node()\n",
635 __func__);
636 return NULL;
637 }
638
639 timer = _omap_dm_timer_request(REQUEST_BY_ID, &id);
640 if (!timer)
641 return NULL;
642
643 return &timer->cookie;
644}
645
646/**
647 * omap_dm_timer_request_by_node - Request a timer by device-tree node
648 * @np: Pointer to device-tree timer node
649 *
650 * Request a timer based upon a device node pointer. Returns pointer to
651 * timer handle on success and a NULL pointer on failure.
652 */
653static struct omap_dm_timer *omap_dm_timer_request_by_node(struct device_node *np)
654{
655 struct dmtimer *timer;
656
657 if (!np)
658 return NULL;
659
660 timer = _omap_dm_timer_request(REQUEST_BY_NODE, np);
661 if (!timer)
662 return NULL;
663
664 return &timer->cookie;
665}
666
667static int omap_dm_timer_free(struct omap_dm_timer *cookie)
668{
669 struct dmtimer *timer;
670 struct device *dev;
671 int rc;
672
673 timer = to_dmtimer(cookie);
674 if (unlikely(!timer))
675 return -EINVAL;
676
677 WARN_ON(!timer->reserved);
678 timer->reserved = 0;
679
680 dev = &timer->pdev->dev;
681 rc = pm_runtime_resume_and_get(dev);
682 if (rc)
683 return rc;
684
685 /* Clear timer configuration */
686 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, 0);
687
688 pm_runtime_put_sync(dev);
689
690 return 0;
691}
692
693static int omap_dm_timer_get_irq(struct omap_dm_timer *cookie)
694{
695 struct dmtimer *timer = to_dmtimer(cookie);
696 if (timer)
697 return timer->irq;
698 return -EINVAL;
699}
700
701#if defined(CONFIG_ARCH_OMAP1)
702#include <linux/soc/ti/omap1-io.h>
703
704static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *cookie)
705{
706 return NULL;
707}
708
709/**
710 * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
711 * @inputmask: current value of idlect mask
712 */
713__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
714{
715 int i = 0;
716 struct dmtimer *timer = NULL;
717 unsigned long flags;
718
719 /* If ARMXOR cannot be idled this function call is unnecessary */
720 if (!(inputmask & (1 << 1)))
721 return inputmask;
722
723 /* If any active timer is using ARMXOR return modified mask */
724 spin_lock_irqsave(&dm_timer_lock, flags);
725 list_for_each_entry(timer, &omap_timer_list, node) {
726 u32 l;
727
728 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
729 if (l & OMAP_TIMER_CTRL_ST) {
730 if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
731 inputmask &= ~(1 << 1);
732 else
733 inputmask &= ~(1 << 2);
734 }
735 i++;
736 }
737 spin_unlock_irqrestore(&dm_timer_lock, flags);
738
739 return inputmask;
740}
741
742#else
743
744static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *cookie)
745{
746 struct dmtimer *timer = to_dmtimer(cookie);
747
748 if (timer && !IS_ERR(timer->fclk))
749 return timer->fclk;
750 return NULL;
751}
752
753__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
754{
755 BUG();
756
757 return 0;
758}
759
760#endif
761
762static int omap_dm_timer_start(struct omap_dm_timer *cookie)
763{
764 struct dmtimer *timer;
765 struct device *dev;
766 int rc;
767 u32 l;
768
769 timer = to_dmtimer(cookie);
770 if (unlikely(!timer))
771 return -EINVAL;
772
773 dev = &timer->pdev->dev;
774
775 rc = pm_runtime_resume_and_get(dev);
776 if (rc)
777 return rc;
778
779 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
780 if (!(l & OMAP_TIMER_CTRL_ST)) {
781 l |= OMAP_TIMER_CTRL_ST;
782 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
783 }
784
785 return 0;
786}
787
788static int omap_dm_timer_stop(struct omap_dm_timer *cookie)
789{
790 struct dmtimer *timer;
791 struct device *dev;
792
793 timer = to_dmtimer(cookie);
794 if (unlikely(!timer))
795 return -EINVAL;
796
797 dev = &timer->pdev->dev;
798
799 __omap_dm_timer_stop(timer);
800
801 pm_runtime_put_sync(dev);
802
803 return 0;
804}
805
806static int omap_dm_timer_set_load(struct omap_dm_timer *cookie,
807 unsigned int load)
808{
809 struct dmtimer *timer;
810 struct device *dev;
811 int rc;
812
813 timer = to_dmtimer(cookie);
814 if (unlikely(!timer))
815 return -EINVAL;
816
817 dev = &timer->pdev->dev;
818 rc = pm_runtime_resume_and_get(dev);
819 if (rc)
820 return rc;
821
822 dmtimer_write(timer, OMAP_TIMER_LOAD_REG, load);
823
824 pm_runtime_put_sync(dev);
825
826 return 0;
827}
828
829static int omap_dm_timer_set_match(struct omap_dm_timer *cookie, int enable,
830 unsigned int match)
831{
832 struct dmtimer *timer;
833 struct device *dev;
834 int rc;
835 u32 l;
836
837 timer = to_dmtimer(cookie);
838 if (unlikely(!timer))
839 return -EINVAL;
840
841 dev = &timer->pdev->dev;
842 rc = pm_runtime_resume_and_get(dev);
843 if (rc)
844 return rc;
845
846 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
847 if (enable)
848 l |= OMAP_TIMER_CTRL_CE;
849 else
850 l &= ~OMAP_TIMER_CTRL_CE;
851 dmtimer_write(timer, OMAP_TIMER_MATCH_REG, match);
852 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
853
854 pm_runtime_put_sync(dev);
855
856 return 0;
857}
858
859static int omap_dm_timer_set_cap(struct omap_dm_timer *cookie,
860 int autoreload, bool config_period)
861{
862 struct dmtimer *timer;
863 struct device *dev;
864 int rc;
865 u32 l;
866
867 timer = to_dmtimer(cookie);
868 if (unlikely(!timer))
869 return -EINVAL;
870
871 dev = &timer->pdev->dev;
872 rc = pm_runtime_resume_and_get(dev);
873 if (rc)
874 return rc;
875 /*
876 * 1. Select autoreload mode. TIMER_TCLR[1] AR bit.
877 * 2. TIMER_TCLR[14]: Sets the functionality of the TIMER IO pin.
878 * 3. TIMER_TCLR[13] : Capture mode select bit.
879 * 3. TIMER_TCLR[9-8] : Select transition capture mode.
880 */
881
882 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
883
884 if (autoreload)
885 l |= OMAP_TIMER_CTRL_AR;
886
887 l |= OMAP_TIMER_CTRL_CAPTMODE | OMAP_TIMER_CTRL_GPOCFG;
888
889 if (config_period == true)
890 l |= OMAP_TIMER_CTRL_TCM_LOWTOHIGH; /* Time Period config */
891 else
892 l |= OMAP_TIMER_CTRL_TCM_BOTHEDGES; /* Duty Cycle config */
893
894 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
895
896 pm_runtime_put_sync(dev);
897
898 return 0;
899}
900
901static int omap_dm_timer_set_pwm(struct omap_dm_timer *cookie, int def_on,
902 int toggle, int trigger, int autoreload)
903{
904 struct dmtimer *timer;
905 struct device *dev;
906 int rc;
907 u32 l;
908
909 timer = to_dmtimer(cookie);
910 if (unlikely(!timer))
911 return -EINVAL;
912
913 dev = &timer->pdev->dev;
914 rc = pm_runtime_resume_and_get(dev);
915 if (rc)
916 return rc;
917
918 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
919 l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
920 OMAP_TIMER_CTRL_PT | (0x03 << 10) | OMAP_TIMER_CTRL_AR);
921 if (def_on)
922 l |= OMAP_TIMER_CTRL_SCPWM;
923 if (toggle)
924 l |= OMAP_TIMER_CTRL_PT;
925 l |= trigger << 10;
926 if (autoreload)
927 l |= OMAP_TIMER_CTRL_AR;
928 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
929
930 pm_runtime_put_sync(dev);
931
932 return 0;
933}
934
935static int omap_dm_timer_get_pwm_status(struct omap_dm_timer *cookie)
936{
937 struct dmtimer *timer;
938 struct device *dev;
939 int rc;
940 u32 l;
941
942 timer = to_dmtimer(cookie);
943 if (unlikely(!timer))
944 return -EINVAL;
945
946 dev = &timer->pdev->dev;
947 rc = pm_runtime_resume_and_get(dev);
948 if (rc)
949 return rc;
950
951 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
952
953 pm_runtime_put_sync(dev);
954
955 return l;
956}
957
958static int omap_dm_timer_set_prescaler(struct omap_dm_timer *cookie,
959 int prescaler)
960{
961 struct dmtimer *timer;
962 struct device *dev;
963 int rc;
964 u32 l;
965
966 timer = to_dmtimer(cookie);
967 if (unlikely(!timer) || prescaler < -1 || prescaler > 7)
968 return -EINVAL;
969
970 dev = &timer->pdev->dev;
971 rc = pm_runtime_resume_and_get(dev);
972 if (rc)
973 return rc;
974
975 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
976 l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
977 if (prescaler >= 0) {
978 l |= OMAP_TIMER_CTRL_PRE;
979 l |= prescaler << 2;
980 }
981 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
982
983 pm_runtime_put_sync(dev);
984
985 return 0;
986}
987
988static int omap_dm_timer_set_int_enable(struct omap_dm_timer *cookie,
989 unsigned int value)
990{
991 struct dmtimer *timer;
992 struct device *dev;
993 int rc;
994
995 timer = to_dmtimer(cookie);
996 if (unlikely(!timer))
997 return -EINVAL;
998
999 dev = &timer->pdev->dev;
1000 rc = pm_runtime_resume_and_get(dev);
1001 if (rc)
1002 return rc;
1003
1004 __omap_dm_timer_int_enable(timer, value);
1005
1006 pm_runtime_put_sync(dev);
1007
1008 return 0;
1009}
1010
1011/**
1012 * omap_dm_timer_set_int_disable - disable timer interrupts
1013 * @cookie: pointer to timer cookie
1014 * @mask: bit mask of interrupts to be disabled
1015 *
1016 * Disables the specified timer interrupts for a timer.
1017 */
1018static int omap_dm_timer_set_int_disable(struct omap_dm_timer *cookie, u32 mask)
1019{
1020 struct dmtimer *timer;
1021 struct device *dev;
1022 u32 l = mask;
1023 int rc;
1024
1025 timer = to_dmtimer(cookie);
1026 if (unlikely(!timer))
1027 return -EINVAL;
1028
1029 dev = &timer->pdev->dev;
1030 rc = pm_runtime_resume_and_get(dev);
1031 if (rc)
1032 return rc;
1033
1034 if (timer->revision == 1)
1035 l = dmtimer_read(timer, timer->irq_ena) & ~mask;
1036
1037 dmtimer_write(timer, timer->irq_dis, l);
1038 l = dmtimer_read(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask;
1039 dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, l);
1040
1041 pm_runtime_put_sync(dev);
1042
1043 return 0;
1044}
1045
1046static unsigned int omap_dm_timer_read_status(struct omap_dm_timer *cookie)
1047{
1048 struct dmtimer *timer;
1049 unsigned int l;
1050
1051 timer = to_dmtimer(cookie);
1052 if (unlikely(!timer || !atomic_read(&timer->enabled))) {
1053 pr_err("%s: timer not available or enabled.\n", __func__);
1054 return 0;
1055 }
1056
1057 l = dmtimer_read(timer, timer->irq_stat);
1058
1059 return l;
1060}
1061
1062static int omap_dm_timer_write_status(struct omap_dm_timer *cookie, unsigned int value)
1063{
1064 struct dmtimer *timer;
1065
1066 timer = to_dmtimer(cookie);
1067 if (unlikely(!timer || !atomic_read(&timer->enabled)))
1068 return -EINVAL;
1069
1070 __omap_dm_timer_write_status(timer, value);
1071
1072 return 0;
1073}
1074
1075static unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *cookie)
1076{
1077 struct dmtimer *timer;
1078
1079 timer = to_dmtimer(cookie);
1080 if (unlikely(!timer || !atomic_read(&timer->enabled))) {
1081 pr_err("%s: timer not iavailable or enabled.\n", __func__);
1082 return 0;
1083 }
1084
1085 return __omap_dm_timer_read_counter(timer);
1086}
1087
1088static inline unsigned int __omap_dm_timer_cap(struct dmtimer *timer, int idx)
1089{
1090 return idx == 0 ? dmtimer_read(timer, OMAP_TIMER_CAPTURE_REG) :
1091 dmtimer_read(timer, OMAP_TIMER_CAPTURE2_REG);
1092}
1093
1094static int omap_dm_timer_write_counter(struct omap_dm_timer *cookie, unsigned int value)
1095{
1096 struct dmtimer *timer;
1097 struct device *dev;
1098
1099 timer = to_dmtimer(cookie);
1100 if (unlikely(!timer)) {
1101 pr_err("%s: timer not available.\n", __func__);
1102 return -EINVAL;
1103 }
1104
1105 dev = &timer->pdev->dev;
1106
1107 pm_runtime_resume_and_get(dev);
1108 dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, value);
1109 pm_runtime_put_sync(dev);
1110
1111 /* Save the context */
1112 timer->context.tcrr = value;
1113 return 0;
1114}
1115
1116/**
1117 * omap_dm_timer_cap_counter() - Calculate the high count or period count depending on the
1118 * configuration.
1119 * @cookie:Pointer to OMAP DM timer
1120 * @is_period:Whether to configure timer in period or duty cycle mode
1121 *
1122 * Return high count or period count if timer is enabled else appropriate error.
1123 */
1124static unsigned int omap_dm_timer_cap_counter(struct omap_dm_timer *cookie, bool is_period)
1125{
1126 struct dmtimer *timer;
1127 unsigned int cap1 = 0;
1128 unsigned int cap2 = 0;
1129 u32 l, ret;
1130
1131 timer = to_dmtimer(cookie);
1132 if (unlikely(!timer || !atomic_read(&timer->enabled))) {
1133 pr_err("%s:timer is not available or enabled.%p\n", __func__, (void *)timer);
1134 return -EINVAL;
1135 }
1136
1137 /* Stop the timer */
1138 omap_dm_timer_stop(cookie);
1139
1140 /* Clear the timer counter value to 0 */
1141 ret = omap_dm_timer_write_counter(cookie, 0);
1142 if (ret)
1143 return ret;
1144
1145 /* Sets the timer capture configuration for period/duty cycle calculation */
1146 ret = omap_dm_timer_set_cap(cookie, true, is_period);
1147 if (ret) {
1148 pr_err("%s: Failed to set timer capture configuration.\n", __func__);
1149 return ret;
1150 }
1151 /* Start the timer */
1152 omap_dm_timer_start(cookie);
1153
1154 /*
1155 * 1 sec delay is given so as to provide
1156 * enough time to capture low frequency signals.
1157 */
1158 msleep(1000);
1159
1160 cap1 = __omap_dm_timer_cap(timer, 0);
1161 cap2 = __omap_dm_timer_cap(timer, 1);
1162
1163 /*
1164 * Clears the TCLR configuration.
1165 * The start bit must be set to 1 as the timer is already in start mode.
1166 */
1167 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
1168 l &= ~(0xffff) | 0x1;
1169 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
1170
1171 return (cap2-cap1);
1172}
1173
1174static int __maybe_unused omap_dm_timer_runtime_suspend(struct device *dev)
1175{
1176 struct dmtimer *timer = dev_get_drvdata(dev);
1177
1178 atomic_set(&timer->enabled, 0);
1179
1180 if (timer->capability & OMAP_TIMER_ALWON || !timer->func_base)
1181 return 0;
1182
1183 omap_timer_save_context(timer);
1184
1185 return 0;
1186}
1187
1188static int __maybe_unused omap_dm_timer_runtime_resume(struct device *dev)
1189{
1190 struct dmtimer *timer = dev_get_drvdata(dev);
1191
1192 if (!(timer->capability & OMAP_TIMER_ALWON) && timer->func_base)
1193 omap_timer_restore_context(timer);
1194
1195 atomic_set(&timer->enabled, 1);
1196
1197 return 0;
1198}
1199
1200static const struct dev_pm_ops omap_dm_timer_pm_ops = {
1201 SET_RUNTIME_PM_OPS(omap_dm_timer_runtime_suspend,
1202 omap_dm_timer_runtime_resume, NULL)
1203};
1204
1205static const struct of_device_id omap_timer_match[];
1206
1207static struct dmtimer_clocksource *omap_dm_timer_to_clocksource(struct clocksource *cs)
1208{
1209 return container_of(cs, struct dmtimer_clocksource, dev);
1210}
1211
1212static u64 omap_dm_timer_read_cycles(struct clocksource *cs)
1213{
1214 struct dmtimer_clocksource *clksrc = omap_dm_timer_to_clocksource(cs);
1215 struct dmtimer *timer = clksrc->timer;
1216
1217 return (u64)__omap_dm_timer_read_counter(timer);
1218}
1219
1220static u64 notrace omap_dm_timer_read_sched_clock(void)
1221{
1222 /* Posted mode is not active here, so we can read directly */
1223 return readl_relaxed(omap_dm_timer_sched_clock_counter);
1224}
1225
1226static void omap_dm_timer_clocksource_suspend(struct clocksource *cs)
1227{
1228 struct dmtimer_clocksource *clksrc = omap_dm_timer_to_clocksource(cs);
1229 struct dmtimer *timer = clksrc->timer;
1230
1231 clksrc->loadval = __omap_dm_timer_read_counter(timer);
1232 __omap_dm_timer_stop(timer);
1233}
1234
1235static void omap_dm_timer_clocksource_resume(struct clocksource *cs)
1236{
1237 struct dmtimer_clocksource *clksrc = omap_dm_timer_to_clocksource(cs);
1238 struct dmtimer *timer = clksrc->timer;
1239
1240 dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, clksrc->loadval);
1241 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR);
1242}
1243
1244static void omap_dm_timer_clocksource_unregister(void *data)
1245{
1246 struct clocksource *cs = data;
1247
1248 clocksource_unregister(cs);
1249}
1250
1251static int omap_dm_timer_setup_clocksource(struct dmtimer *timer)
1252{
1253 struct device *dev = &timer->pdev->dev;
1254 struct dmtimer_clocksource *clksrc;
1255 int err;
1256
1257 __omap_dm_timer_init_regs(timer);
1258
1259 timer->reserved = 1;
1260
1261 clksrc = devm_kzalloc(dev, sizeof(*clksrc), GFP_KERNEL);
1262 if (!clksrc)
1263 return -ENOMEM;
1264
1265 clksrc->timer = timer;
1266
1267 clksrc->dev.name = "omap_dm_timer";
1268 clksrc->dev.rating = 300;
1269 clksrc->dev.read = omap_dm_timer_read_cycles;
1270 clksrc->dev.mask = CLOCKSOURCE_MASK(32);
1271 clksrc->dev.flags = CLOCK_SOURCE_IS_CONTINUOUS;
1272 clksrc->dev.suspend = omap_dm_timer_clocksource_suspend;
1273 clksrc->dev.resume = omap_dm_timer_clocksource_resume;
1274
1275 dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, 0);
1276 dmtimer_write(timer, OMAP_TIMER_LOAD_REG, 0);
1277 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR);
1278
1279 omap_dm_timer_sched_clock_counter = timer->func_base + _OMAP_TIMER_COUNTER_OFFSET;
1280 sched_clock_register(omap_dm_timer_read_sched_clock, 32, timer->fclk_rate);
1281
1282 err = clocksource_register_hz(&clksrc->dev, timer->fclk_rate);
1283 if (err)
1284 return dev_err_probe(dev, err, "Could not register as clocksource\n");
1285
1286 err = devm_add_action_or_reset(dev, omap_dm_timer_clocksource_unregister, &clksrc->dev);
1287 if (err)
1288 return dev_err_probe(dev, err, "Could not register clocksource_unregister action\n");
1289
1290 return 0;
1291}
1292
1293static struct omap_dm_timer_clockevent *to_dm_timer_clockevent(struct clock_event_device *evt)
1294{
1295 return container_of(evt, struct omap_dm_timer_clockevent, dev);
1296}
1297
1298static int omap_dm_timer_evt_set_next_event(unsigned long cycles,
1299 struct clock_event_device *evt)
1300{
1301 struct omap_dm_timer_clockevent *clkevt = to_dm_timer_clockevent(evt);
1302 struct dmtimer *timer = clkevt->timer;
1303
1304 dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, 0xffffffff - cycles);
1305 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, OMAP_TIMER_CTRL_ST);
1306
1307 return 0;
1308}
1309
1310static int omap_dm_timer_evt_shutdown(struct clock_event_device *evt)
1311{
1312 struct omap_dm_timer_clockevent *clkevt = to_dm_timer_clockevent(evt);
1313 struct dmtimer *timer = clkevt->timer;
1314
1315 __omap_dm_timer_stop(timer);
1316
1317 return 0;
1318}
1319
1320static int omap_dm_timer_evt_set_periodic(struct clock_event_device *evt)
1321{
1322 struct omap_dm_timer_clockevent *clkevt = to_dm_timer_clockevent(evt);
1323 struct dmtimer *timer = clkevt->timer;
1324
1325 omap_dm_timer_evt_shutdown(evt);
1326
1327 omap_dm_timer_set_load(&timer->cookie, clkevt->period);
1328 dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, clkevt->period);
1329 dmtimer_write(timer, OMAP_TIMER_CTRL_REG,
1330 OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST);
1331
1332 return 0;
1333}
1334
1335static irqreturn_t omap_dm_timer_evt_interrupt(int irq, void *dev_id)
1336{
1337 struct omap_dm_timer_clockevent *clkevt = dev_id;
1338 struct dmtimer *timer = clkevt->timer;
1339
1340 __omap_dm_timer_write_status(timer, OMAP_TIMER_INT_OVERFLOW);
1341
1342 clkevt->dev.event_handler(&clkevt->dev);
1343
1344 return IRQ_HANDLED;
1345}
1346
1347static int omap_dm_timer_setup_clockevent(struct dmtimer *timer)
1348{
1349 struct device *dev = &timer->pdev->dev;
1350 struct omap_dm_timer_clockevent *clkevt;
1351 int ret;
1352
1353 clkevt = devm_kzalloc(dev, sizeof(*clkevt), GFP_KERNEL);
1354 if (!clkevt)
1355 return -ENOMEM;
1356
1357 timer->reserved = 1;
1358 clkevt->timer = timer;
1359
1360 clkevt->dev.name = "omap_dm_timer";
1361 clkevt->dev.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
1362 clkevt->dev.rating = 300;
1363 clkevt->dev.set_next_event = omap_dm_timer_evt_set_next_event;
1364 clkevt->dev.set_state_shutdown = omap_dm_timer_evt_shutdown;
1365 clkevt->dev.set_state_periodic = omap_dm_timer_evt_set_periodic;
1366 clkevt->dev.set_state_oneshot = omap_dm_timer_evt_shutdown;
1367 clkevt->dev.set_state_oneshot_stopped = omap_dm_timer_evt_shutdown;
1368 clkevt->dev.tick_resume = omap_dm_timer_evt_shutdown;
1369 clkevt->dev.cpumask = cpu_possible_mask;
1370 clkevt->period = 0xffffffff - DIV_ROUND_CLOSEST(timer->fclk_rate, HZ);
1371
1372 __omap_dm_timer_init_regs(timer);
1373 __omap_dm_timer_stop(timer);
1374 __omap_dm_timer_enable_posted(timer);
1375
1376 ret = devm_request_irq(dev, timer->irq, omap_dm_timer_evt_interrupt,
1377 IRQF_TIMER, "omap_dm_timer_clockevent", clkevt);
1378 if (ret)
1379 return ret;
1380
1381 __omap_dm_timer_int_enable(timer, OMAP_TIMER_INT_OVERFLOW);
1382
1383 clockevents_config_and_register(&clkevt->dev, timer->fclk_rate,
1384 3,
1385 0xffffffff);
1386
1387 omap_dm_timer_clockevent_setup = true;
1388 return 0;
1389}
1390
1391/**
1392 * omap_dm_timer_probe - probe function called for every registered device
1393 * @pdev: pointer to current timer platform device
1394 *
1395 * Called by driver framework at the end of device registration for all
1396 * timer devices.
1397 */
1398static int omap_dm_timer_probe(struct platform_device *pdev)
1399{
1400 unsigned long flags;
1401 struct dmtimer *timer;
1402 struct device *dev = &pdev->dev;
1403 const struct dmtimer_platform_data *pdata;
1404 int ret;
1405
1406 pdata = of_device_get_match_data(dev);
1407 if (!pdata)
1408 pdata = dev_get_platdata(dev);
1409 else
1410 dev->platform_data = (void *)pdata;
1411
1412 if (!pdata) {
1413 dev_err(dev, "%s: no platform data.\n", __func__);
1414 return -ENODEV;
1415 }
1416
1417 timer = devm_kzalloc(dev, sizeof(*timer), GFP_KERNEL);
1418 if (!timer)
1419 return -ENOMEM;
1420
1421 timer->irq = platform_get_irq(pdev, 0);
1422 if (timer->irq < 0) {
1423 if (of_property_read_bool(dev->of_node, "ti,timer-pwm"))
1424 dev_info(dev, "Did not find timer interrupt, timer usable in PWM mode only\n");
1425 else
1426 return timer->irq;
1427 }
1428
1429 timer->io_base = devm_platform_ioremap_resource(pdev, 0);
1430 if (IS_ERR(timer->io_base))
1431 return PTR_ERR(timer->io_base);
1432
1433 platform_set_drvdata(pdev, timer);
1434
1435 if (dev->of_node) {
1436 if (of_property_read_bool(dev->of_node, "ti,timer-alwon"))
1437 timer->capability |= OMAP_TIMER_ALWON;
1438 if (of_property_read_bool(dev->of_node, "ti,timer-dsp"))
1439 timer->capability |= OMAP_TIMER_HAS_DSP_IRQ;
1440 if (of_property_read_bool(dev->of_node, "ti,timer-pwm"))
1441 timer->capability |= OMAP_TIMER_HAS_PWM;
1442 if (of_property_read_bool(dev->of_node, "ti,timer-secure"))
1443 timer->capability |= OMAP_TIMER_SECURE;
1444 } else {
1445 timer->id = pdev->id;
1446 timer->capability = pdata->timer_capability;
1447 timer->reserved = omap_dm_timer_reserved_systimer(timer->id);
1448 }
1449
1450 timer->omap1 = timer->capability & OMAP_TIMER_NEEDS_RESET;
1451
1452 /* OMAP1 devices do not yet use the clock framework for dmtimers */
1453 if (!timer->omap1) {
1454 timer->fclk = devm_clk_get(dev, "fck");
1455 if (IS_ERR(timer->fclk))
1456 return PTR_ERR(timer->fclk);
1457
1458 timer->fclk_nb.notifier_call = omap_timer_fclk_notifier;
1459 ret = devm_clk_notifier_register(dev, timer->fclk,
1460 &timer->fclk_nb);
1461 if (ret)
1462 return ret;
1463
1464 timer->fclk_rate = clk_get_rate(timer->fclk);
1465 } else {
1466 timer->fclk = ERR_PTR(-ENODEV);
1467 }
1468
1469 if (!(timer->capability & OMAP_TIMER_ALWON)) {
1470 timer->nb.notifier_call = omap_timer_context_notifier;
1471 cpu_pm_register_notifier(&timer->nb);
1472 }
1473
1474 timer->errata = pdata->timer_errata;
1475
1476 timer->pdev = pdev;
1477
1478 if (timer->capability & OMAP_TIMER_ALWON && !IS_ERR_OR_NULL(timer->fclk)) {
1479 if (!omap_dm_timer_sched_clock_counter) {
1480 ret = omap_dm_timer_setup_clocksource(timer);
1481 if (ret)
1482 return ret;
1483 } else if (!omap_dm_timer_clockevent_setup) {
1484 ret = omap_dm_timer_setup_clockevent(timer);
1485 if (ret)
1486 return ret;
1487 }
1488 }
1489
1490 pm_runtime_enable(dev);
1491
1492 if (!timer->reserved) {
1493 ret = pm_runtime_resume_and_get(dev);
1494 if (ret) {
1495 dev_err(dev, "%s: pm_runtime_get_sync failed!\n",
1496 __func__);
1497 goto err_disable;
1498 }
1499 __omap_dm_timer_init_regs(timer);
1500
1501 /* Clear timer configuration */
1502 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, 0);
1503
1504 pm_runtime_put(dev);
1505 }
1506
1507 /* add the timer element to the list */
1508 spin_lock_irqsave(&dm_timer_lock, flags);
1509 list_add_tail(&timer->node, &omap_timer_list);
1510 spin_unlock_irqrestore(&dm_timer_lock, flags);
1511
1512 dev_dbg(dev, "Device Probed.\n");
1513
1514 return 0;
1515
1516err_disable:
1517 pm_runtime_disable(dev);
1518 return ret;
1519}
1520
1521/**
1522 * omap_dm_timer_remove - cleanup a registered timer device
1523 * @pdev: pointer to current timer platform device
1524 *
1525 * Called by driver framework whenever a timer device is unregistered.
1526 * In addition to freeing platform resources it also deletes the timer
1527 * entry from the local list.
1528 */
1529static void omap_dm_timer_remove(struct platform_device *pdev)
1530{
1531 struct dmtimer *timer;
1532 unsigned long flags;
1533 int ret = -EINVAL;
1534
1535 spin_lock_irqsave(&dm_timer_lock, flags);
1536 list_for_each_entry(timer, &omap_timer_list, node)
1537 if (!strcmp(dev_name(&timer->pdev->dev),
1538 dev_name(&pdev->dev))) {
1539 if (!(timer->capability & OMAP_TIMER_ALWON))
1540 cpu_pm_unregister_notifier(&timer->nb);
1541 list_del(&timer->node);
1542 ret = 0;
1543 break;
1544 }
1545 spin_unlock_irqrestore(&dm_timer_lock, flags);
1546
1547 pm_runtime_disable(&pdev->dev);
1548
1549 if (ret)
1550 dev_err(&pdev->dev, "Unable to determine timer entry in list of drivers on remove\n");
1551}
1552
1553static const struct omap_dm_timer_ops dmtimer_ops = {
1554 .request_by_node = omap_dm_timer_request_by_node,
1555 .request_specific = omap_dm_timer_request_specific,
1556 .request = omap_dm_timer_request,
1557 .set_source = omap_dm_timer_set_source,
1558 .get_irq = omap_dm_timer_get_irq,
1559 .set_int_enable = omap_dm_timer_set_int_enable,
1560 .set_int_disable = omap_dm_timer_set_int_disable,
1561 .free = omap_dm_timer_free,
1562 .enable = omap_dm_timer_enable,
1563 .disable = omap_dm_timer_disable,
1564 .get_fclk = omap_dm_timer_get_fclk,
1565 .start = omap_dm_timer_start,
1566 .stop = omap_dm_timer_stop,
1567 .set_load = omap_dm_timer_set_load,
1568 .set_match = omap_dm_timer_set_match,
1569 .set_pwm = omap_dm_timer_set_pwm,
1570 .get_pwm_status = omap_dm_timer_get_pwm_status,
1571 .set_prescaler = omap_dm_timer_set_prescaler,
1572 .read_counter = omap_dm_timer_read_counter,
1573 .write_counter = omap_dm_timer_write_counter,
1574 .read_status = omap_dm_timer_read_status,
1575 .write_status = omap_dm_timer_write_status,
1576 .set_cap = omap_dm_timer_set_cap,
1577 .get_cap_status = omap_dm_timer_get_pwm_status,
1578 .read_cap = omap_dm_timer_cap_counter,
1579};
1580
1581static const struct dmtimer_platform_data omap3plus_pdata = {
1582 .timer_errata = OMAP_TIMER_ERRATA_I103_I767,
1583 .timer_ops = &dmtimer_ops,
1584};
1585
1586static const struct dmtimer_platform_data am6_pdata = {
1587 .timer_ops = &dmtimer_ops,
1588};
1589
1590static const struct of_device_id omap_timer_match[] = {
1591 {
1592 .compatible = "ti,omap2420-timer",
1593 },
1594 {
1595 .compatible = "ti,omap3430-timer",
1596 .data = &omap3plus_pdata,
1597 },
1598 {
1599 .compatible = "ti,omap4430-timer",
1600 .data = &omap3plus_pdata,
1601 },
1602 {
1603 .compatible = "ti,omap5430-timer",
1604 .data = &omap3plus_pdata,
1605 },
1606 {
1607 .compatible = "ti,am335x-timer",
1608 .data = &omap3plus_pdata,
1609 },
1610 {
1611 .compatible = "ti,am335x-timer-1ms",
1612 .data = &omap3plus_pdata,
1613 },
1614 {
1615 .compatible = "ti,dm816-timer",
1616 .data = &omap3plus_pdata,
1617 },
1618 {
1619 .compatible = "ti,am654-timer",
1620 .data = &am6_pdata,
1621 },
1622 {},
1623};
1624MODULE_DEVICE_TABLE(of, omap_timer_match);
1625
1626static struct platform_driver omap_dm_timer_driver = {
1627 .probe = omap_dm_timer_probe,
1628 .remove = omap_dm_timer_remove,
1629 .driver = {
1630 .name = "omap_timer",
1631 .of_match_table = omap_timer_match,
1632 .pm = &omap_dm_timer_pm_ops,
1633 },
1634};
1635
1636module_platform_driver(omap_dm_timer_driver);
1637
1638MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver");
1639MODULE_AUTHOR("Texas Instruments Inc");