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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * CPU frequency scaling support for Armada 37xx platform.
4 *
5 * Copyright (C) 2017 Marvell
6 *
7 * Gregory CLEMENT <[email protected]>
8 */
9
10#include <linux/clk.h>
11#include <linux/cpu.h>
12#include <linux/cpufreq.h>
13#include <linux/err.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <linux/mfd/syscon.h>
17#include <linux/module.h>
18#include <linux/platform_device.h>
19#include <linux/pm_opp.h>
20#include <linux/regmap.h>
21#include <linux/slab.h>
22
23#include "cpufreq-dt.h"
24
25/* Clk register set */
26#define ARMADA_37XX_CLK_TBG_SEL 0
27#define ARMADA_37XX_CLK_TBG_SEL_CPU_OFF 22
28
29/* Power management in North Bridge register set */
30#define ARMADA_37XX_NB_L0L1 0x18
31#define ARMADA_37XX_NB_L2L3 0x1C
32#define ARMADA_37XX_NB_TBG_DIV_OFF 13
33#define ARMADA_37XX_NB_TBG_DIV_MASK 0x7
34#define ARMADA_37XX_NB_CLK_SEL_OFF 11
35#define ARMADA_37XX_NB_CLK_SEL_MASK 0x1
36#define ARMADA_37XX_NB_CLK_SEL_TBG 0x1
37#define ARMADA_37XX_NB_TBG_SEL_OFF 9
38#define ARMADA_37XX_NB_TBG_SEL_MASK 0x3
39#define ARMADA_37XX_NB_VDD_SEL_OFF 6
40#define ARMADA_37XX_NB_VDD_SEL_MASK 0x3
41#define ARMADA_37XX_NB_CONFIG_SHIFT 16
42#define ARMADA_37XX_NB_DYN_MOD 0x24
43#define ARMADA_37XX_NB_CLK_SEL_EN BIT(26)
44#define ARMADA_37XX_NB_TBG_EN BIT(28)
45#define ARMADA_37XX_NB_DIV_EN BIT(29)
46#define ARMADA_37XX_NB_VDD_EN BIT(30)
47#define ARMADA_37XX_NB_DFS_EN BIT(31)
48#define ARMADA_37XX_NB_CPU_LOAD 0x30
49#define ARMADA_37XX_NB_CPU_LOAD_MASK 0x3
50#define ARMADA_37XX_DVFS_LOAD_0 0
51#define ARMADA_37XX_DVFS_LOAD_1 1
52#define ARMADA_37XX_DVFS_LOAD_2 2
53#define ARMADA_37XX_DVFS_LOAD_3 3
54
55/* AVS register set */
56#define ARMADA_37XX_AVS_CTL0 0x0
57#define ARMADA_37XX_AVS_ENABLE BIT(30)
58#define ARMADA_37XX_AVS_HIGH_VDD_LIMIT 16
59#define ARMADA_37XX_AVS_LOW_VDD_LIMIT 22
60#define ARMADA_37XX_AVS_VDD_MASK 0x3F
61#define ARMADA_37XX_AVS_CTL2 0x8
62#define ARMADA_37XX_AVS_LOW_VDD_EN BIT(6)
63#define ARMADA_37XX_AVS_VSET(x) (0x1C + 4 * (x))
64
65/*
66 * On Armada 37xx the Power management manages 4 level of CPU load,
67 * each level can be associated with a CPU clock source, a CPU
68 * divider, a VDD level, etc...
69 */
70#define LOAD_LEVEL_NR 4
71
72#define MIN_VOLT_MV 1000
73#define MIN_VOLT_MV_FOR_L1_1000MHZ 1108
74#define MIN_VOLT_MV_FOR_L1_1200MHZ 1155
75
76/* AVS value for the corresponding voltage (in mV) */
77static int avs_map[] = {
78 747, 758, 770, 782, 793, 805, 817, 828, 840, 852, 863, 875, 887, 898,
79 910, 922, 933, 945, 957, 968, 980, 992, 1003, 1015, 1027, 1038, 1050,
80 1062, 1073, 1085, 1097, 1108, 1120, 1132, 1143, 1155, 1167, 1178, 1190,
81 1202, 1213, 1225, 1237, 1248, 1260, 1272, 1283, 1295, 1307, 1318, 1330,
82 1342
83};
84
85struct armada37xx_cpufreq_state {
86 struct platform_device *pdev;
87 struct device *cpu_dev;
88 struct regmap *regmap;
89 u32 nb_l0l1;
90 u32 nb_l2l3;
91 u32 nb_dyn_mod;
92 u32 nb_cpu_load;
93};
94
95static struct armada37xx_cpufreq_state *armada37xx_cpufreq_state;
96
97struct armada_37xx_dvfs {
98 u32 cpu_freq_max;
99 u8 divider[LOAD_LEVEL_NR];
100 u32 avs[LOAD_LEVEL_NR];
101};
102
103static struct armada_37xx_dvfs armada_37xx_dvfs[] = {
104 {.cpu_freq_max = 1200*1000*1000, .divider = {1, 2, 4, 6} },
105 {.cpu_freq_max = 1000*1000*1000, .divider = {1, 2, 4, 5} },
106 {.cpu_freq_max = 800*1000*1000, .divider = {1, 2, 3, 4} },
107 {.cpu_freq_max = 600*1000*1000, .divider = {2, 4, 5, 6} },
108};
109
110static struct armada_37xx_dvfs *armada_37xx_cpu_freq_info_get(u32 freq)
111{
112 int i;
113
114 for (i = 0; i < ARRAY_SIZE(armada_37xx_dvfs); i++) {
115 if (freq == armada_37xx_dvfs[i].cpu_freq_max)
116 return &armada_37xx_dvfs[i];
117 }
118
119 pr_err("Unsupported CPU frequency %d MHz\n", freq/1000000);
120 return NULL;
121}
122
123/*
124 * Setup the four level managed by the hardware. Once the four level
125 * will be configured then the DVFS will be enabled.
126 */
127static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base,
128 struct regmap *clk_base, u8 *divider)
129{
130 u32 cpu_tbg_sel;
131 int load_lvl;
132
133 /* Determine to which TBG clock is CPU connected */
134 regmap_read(clk_base, ARMADA_37XX_CLK_TBG_SEL, &cpu_tbg_sel);
135 cpu_tbg_sel >>= ARMADA_37XX_CLK_TBG_SEL_CPU_OFF;
136 cpu_tbg_sel &= ARMADA_37XX_NB_TBG_SEL_MASK;
137
138 for (load_lvl = 0; load_lvl < LOAD_LEVEL_NR; load_lvl++) {
139 unsigned int reg, mask, val, offset = 0;
140
141 if (load_lvl <= ARMADA_37XX_DVFS_LOAD_1)
142 reg = ARMADA_37XX_NB_L0L1;
143 else
144 reg = ARMADA_37XX_NB_L2L3;
145
146 if (load_lvl == ARMADA_37XX_DVFS_LOAD_0 ||
147 load_lvl == ARMADA_37XX_DVFS_LOAD_2)
148 offset += ARMADA_37XX_NB_CONFIG_SHIFT;
149
150 /* Set cpu clock source, for all the level we use TBG */
151 val = ARMADA_37XX_NB_CLK_SEL_TBG << ARMADA_37XX_NB_CLK_SEL_OFF;
152 mask = (ARMADA_37XX_NB_CLK_SEL_MASK
153 << ARMADA_37XX_NB_CLK_SEL_OFF);
154
155 /* Set TBG index, for all levels we use the same TBG */
156 val = cpu_tbg_sel << ARMADA_37XX_NB_TBG_SEL_OFF;
157 mask = (ARMADA_37XX_NB_TBG_SEL_MASK
158 << ARMADA_37XX_NB_TBG_SEL_OFF);
159
160 /*
161 * Set cpu divider based on the pre-computed array in
162 * order to have balanced step.
163 */
164 val |= divider[load_lvl] << ARMADA_37XX_NB_TBG_DIV_OFF;
165 mask |= (ARMADA_37XX_NB_TBG_DIV_MASK
166 << ARMADA_37XX_NB_TBG_DIV_OFF);
167
168 /* Set VDD divider which is actually the load level. */
169 val |= load_lvl << ARMADA_37XX_NB_VDD_SEL_OFF;
170 mask |= (ARMADA_37XX_NB_VDD_SEL_MASK
171 << ARMADA_37XX_NB_VDD_SEL_OFF);
172
173 val <<= offset;
174 mask <<= offset;
175
176 regmap_update_bits(base, reg, mask, val);
177 }
178}
179
180/*
181 * Find out the armada 37x supported AVS value whose voltage value is
182 * the round-up closest to the target voltage value.
183 */
184static u32 armada_37xx_avs_val_match(int target_vm)
185{
186 u32 avs;
187
188 /* Find out the round-up closest supported voltage value */
189 for (avs = 0; avs < ARRAY_SIZE(avs_map); avs++)
190 if (avs_map[avs] >= target_vm)
191 break;
192
193 /*
194 * If all supported voltages are smaller than target one,
195 * choose the largest supported voltage
196 */
197 if (avs == ARRAY_SIZE(avs_map))
198 avs = ARRAY_SIZE(avs_map) - 1;
199
200 return avs;
201}
202
203/*
204 * For Armada 37xx soc, L0(VSET0) VDD AVS value is set to SVC revision
205 * value or a default value when SVC is not supported.
206 * - L0 can be read out from the register of AVS_CTRL_0 and L0 voltage
207 * can be got from the mapping table of avs_map.
208 * - L1 voltage should be about 100mv smaller than L0 voltage
209 * - L2 & L3 voltage should be about 150mv smaller than L0 voltage.
210 * This function calculates L1 & L2 & L3 AVS values dynamically based
211 * on L0 voltage and fill all AVS values to the AVS value table.
212 * When base CPU frequency is 1000 or 1200 MHz then there is additional
213 * minimal avs value for load L1.
214 */
215static void __init armada37xx_cpufreq_avs_configure(struct regmap *base,
216 struct armada_37xx_dvfs *dvfs)
217{
218 unsigned int target_vm;
219 int load_level = 0;
220 u32 l0_vdd_min;
221
222 if (base == NULL)
223 return;
224
225 /* Get L0 VDD min value */
226 regmap_read(base, ARMADA_37XX_AVS_CTL0, &l0_vdd_min);
227 l0_vdd_min = (l0_vdd_min >> ARMADA_37XX_AVS_LOW_VDD_LIMIT) &
228 ARMADA_37XX_AVS_VDD_MASK;
229 if (l0_vdd_min >= ARRAY_SIZE(avs_map)) {
230 pr_err("L0 VDD MIN %d is not correct.\n", l0_vdd_min);
231 return;
232 }
233 dvfs->avs[0] = l0_vdd_min;
234
235 if (avs_map[l0_vdd_min] <= MIN_VOLT_MV) {
236 /*
237 * If L0 voltage is smaller than 1000mv, then all VDD sets
238 * use L0 voltage;
239 */
240 u32 avs_min = armada_37xx_avs_val_match(MIN_VOLT_MV);
241
242 for (load_level = 1; load_level < LOAD_LEVEL_NR; load_level++)
243 dvfs->avs[load_level] = avs_min;
244
245 /*
246 * Set the avs values for load L0 and L1 when base CPU frequency
247 * is 1000/1200 MHz to its typical initial values according to
248 * the Armada 3700 Hardware Specifications.
249 */
250 if (dvfs->cpu_freq_max >= 1000*1000*1000) {
251 if (dvfs->cpu_freq_max >= 1200*1000*1000)
252 avs_min = armada_37xx_avs_val_match(MIN_VOLT_MV_FOR_L1_1200MHZ);
253 else
254 avs_min = armada_37xx_avs_val_match(MIN_VOLT_MV_FOR_L1_1000MHZ);
255 dvfs->avs[0] = dvfs->avs[1] = avs_min;
256 }
257
258 return;
259 }
260
261 /*
262 * L1 voltage is equal to L0 voltage - 100mv and it must be
263 * larger than 1000mv
264 */
265
266 target_vm = avs_map[l0_vdd_min] - 100;
267 target_vm = max(target_vm, MIN_VOLT_MV);
268 dvfs->avs[1] = armada_37xx_avs_val_match(target_vm);
269
270 /*
271 * L2 & L3 voltage is equal to L0 voltage - 150mv and it must
272 * be larger than 1000mv
273 */
274 target_vm = avs_map[l0_vdd_min] - 150;
275 target_vm = max(target_vm, MIN_VOLT_MV);
276 dvfs->avs[2] = dvfs->avs[3] = armada_37xx_avs_val_match(target_vm);
277
278 /*
279 * Fix the avs value for load L1 when base CPU frequency is 1000/1200 MHz,
280 * otherwise the CPU gets stuck when switching from load L1 to load L0.
281 * Also ensure that avs value for load L1 is not higher than for L0.
282 */
283 if (dvfs->cpu_freq_max >= 1000*1000*1000) {
284 u32 avs_min_l1;
285
286 if (dvfs->cpu_freq_max >= 1200*1000*1000)
287 avs_min_l1 = armada_37xx_avs_val_match(MIN_VOLT_MV_FOR_L1_1200MHZ);
288 else
289 avs_min_l1 = armada_37xx_avs_val_match(MIN_VOLT_MV_FOR_L1_1000MHZ);
290
291 if (avs_min_l1 > dvfs->avs[0])
292 avs_min_l1 = dvfs->avs[0];
293
294 if (dvfs->avs[1] < avs_min_l1)
295 dvfs->avs[1] = avs_min_l1;
296 }
297}
298
299static void __init armada37xx_cpufreq_avs_setup(struct regmap *base,
300 struct armada_37xx_dvfs *dvfs)
301{
302 unsigned int avs_val = 0;
303 int load_level = 0;
304
305 if (base == NULL)
306 return;
307
308 /* Disable AVS before the configuration */
309 regmap_update_bits(base, ARMADA_37XX_AVS_CTL0,
310 ARMADA_37XX_AVS_ENABLE, 0);
311
312
313 /* Enable low voltage mode */
314 regmap_update_bits(base, ARMADA_37XX_AVS_CTL2,
315 ARMADA_37XX_AVS_LOW_VDD_EN,
316 ARMADA_37XX_AVS_LOW_VDD_EN);
317
318
319 for (load_level = 1; load_level < LOAD_LEVEL_NR; load_level++) {
320 avs_val = dvfs->avs[load_level];
321 regmap_update_bits(base, ARMADA_37XX_AVS_VSET(load_level-1),
322 ARMADA_37XX_AVS_VDD_MASK << ARMADA_37XX_AVS_HIGH_VDD_LIMIT |
323 ARMADA_37XX_AVS_VDD_MASK << ARMADA_37XX_AVS_LOW_VDD_LIMIT,
324 avs_val << ARMADA_37XX_AVS_HIGH_VDD_LIMIT |
325 avs_val << ARMADA_37XX_AVS_LOW_VDD_LIMIT);
326 }
327
328 /* Enable AVS after the configuration */
329 regmap_update_bits(base, ARMADA_37XX_AVS_CTL0,
330 ARMADA_37XX_AVS_ENABLE,
331 ARMADA_37XX_AVS_ENABLE);
332
333}
334
335static void armada37xx_cpufreq_disable_dvfs(struct regmap *base)
336{
337 unsigned int reg = ARMADA_37XX_NB_DYN_MOD,
338 mask = ARMADA_37XX_NB_DFS_EN;
339
340 regmap_update_bits(base, reg, mask, 0);
341}
342
343static void __init armada37xx_cpufreq_enable_dvfs(struct regmap *base)
344{
345 unsigned int val, reg = ARMADA_37XX_NB_CPU_LOAD,
346 mask = ARMADA_37XX_NB_CPU_LOAD_MASK;
347
348 /* Start with the highest load (0) */
349 val = ARMADA_37XX_DVFS_LOAD_0;
350 regmap_update_bits(base, reg, mask, val);
351
352 /* Now enable DVFS for the CPUs */
353 reg = ARMADA_37XX_NB_DYN_MOD;
354 mask = ARMADA_37XX_NB_CLK_SEL_EN | ARMADA_37XX_NB_TBG_EN |
355 ARMADA_37XX_NB_DIV_EN | ARMADA_37XX_NB_VDD_EN |
356 ARMADA_37XX_NB_DFS_EN;
357
358 regmap_update_bits(base, reg, mask, mask);
359}
360
361static int armada37xx_cpufreq_suspend(struct cpufreq_policy *policy)
362{
363 struct armada37xx_cpufreq_state *state = armada37xx_cpufreq_state;
364
365 regmap_read(state->regmap, ARMADA_37XX_NB_L0L1, &state->nb_l0l1);
366 regmap_read(state->regmap, ARMADA_37XX_NB_L2L3, &state->nb_l2l3);
367 regmap_read(state->regmap, ARMADA_37XX_NB_CPU_LOAD,
368 &state->nb_cpu_load);
369 regmap_read(state->regmap, ARMADA_37XX_NB_DYN_MOD, &state->nb_dyn_mod);
370
371 return 0;
372}
373
374static int armada37xx_cpufreq_resume(struct cpufreq_policy *policy)
375{
376 struct armada37xx_cpufreq_state *state = armada37xx_cpufreq_state;
377
378 /* Ensure DVFS is disabled otherwise the following registers are RO */
379 armada37xx_cpufreq_disable_dvfs(state->regmap);
380
381 regmap_write(state->regmap, ARMADA_37XX_NB_L0L1, state->nb_l0l1);
382 regmap_write(state->regmap, ARMADA_37XX_NB_L2L3, state->nb_l2l3);
383 regmap_write(state->regmap, ARMADA_37XX_NB_CPU_LOAD,
384 state->nb_cpu_load);
385
386 /*
387 * NB_DYN_MOD register is the one that actually enable back DVFS if it
388 * was enabled before the suspend operation. This must be done last
389 * otherwise other registers are not writable.
390 */
391 regmap_write(state->regmap, ARMADA_37XX_NB_DYN_MOD, state->nb_dyn_mod);
392
393 return 0;
394}
395
396static int __init armada37xx_cpufreq_driver_init(void)
397{
398 struct cpufreq_dt_platform_data pdata;
399 struct armada_37xx_dvfs *dvfs;
400 struct platform_device *pdev;
401 unsigned long freq;
402 unsigned int base_frequency;
403 struct regmap *nb_clk_base, *nb_pm_base, *avs_base;
404 struct device *cpu_dev;
405 int load_lvl, ret;
406 struct clk *clk, *parent;
407
408 nb_clk_base =
409 syscon_regmap_lookup_by_compatible("marvell,armada-3700-periph-clock-nb");
410 if (IS_ERR(nb_clk_base))
411 return -ENODEV;
412
413 nb_pm_base =
414 syscon_regmap_lookup_by_compatible("marvell,armada-3700-nb-pm");
415
416 if (IS_ERR(nb_pm_base))
417 return -ENODEV;
418
419 avs_base =
420 syscon_regmap_lookup_by_compatible("marvell,armada-3700-avs");
421
422 /* if AVS is not present don't use it but still try to setup dvfs */
423 if (IS_ERR(avs_base)) {
424 pr_info("Syscon failed for Adapting Voltage Scaling: skip it\n");
425 avs_base = NULL;
426 }
427 /* Before doing any configuration on the DVFS first, disable it */
428 armada37xx_cpufreq_disable_dvfs(nb_pm_base);
429
430 /*
431 * On CPU 0 register the operating points supported (which are
432 * the nominal CPU frequency and full integer divisions of
433 * it).
434 */
435 cpu_dev = get_cpu_device(0);
436 if (!cpu_dev) {
437 dev_err(cpu_dev, "Cannot get CPU\n");
438 return -ENODEV;
439 }
440
441 clk = clk_get(cpu_dev, NULL);
442 if (IS_ERR(clk)) {
443 dev_err(cpu_dev, "Cannot get clock for CPU0\n");
444 return PTR_ERR(clk);
445 }
446
447 parent = clk_get_parent(clk);
448 if (IS_ERR(parent)) {
449 dev_err(cpu_dev, "Cannot get parent clock for CPU0\n");
450 clk_put(clk);
451 return PTR_ERR(parent);
452 }
453
454 /* Get parent CPU frequency */
455 base_frequency = clk_get_rate(parent);
456
457 if (!base_frequency) {
458 dev_err(cpu_dev, "Failed to get parent clock rate for CPU\n");
459 clk_put(clk);
460 return -EINVAL;
461 }
462
463 dvfs = armada_37xx_cpu_freq_info_get(base_frequency);
464 if (!dvfs) {
465 clk_put(clk);
466 return -EINVAL;
467 }
468
469 armada37xx_cpufreq_state = kmalloc_obj(*armada37xx_cpufreq_state);
470 if (!armada37xx_cpufreq_state) {
471 clk_put(clk);
472 return -ENOMEM;
473 }
474
475 armada37xx_cpufreq_state->regmap = nb_pm_base;
476
477 armada37xx_cpufreq_avs_configure(avs_base, dvfs);
478 armada37xx_cpufreq_avs_setup(avs_base, dvfs);
479
480 armada37xx_cpufreq_dvfs_setup(nb_pm_base, nb_clk_base, dvfs->divider);
481 clk_put(clk);
482
483 for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR;
484 load_lvl++) {
485 unsigned long u_volt = avs_map[dvfs->avs[load_lvl]] * 1000;
486 freq = base_frequency / dvfs->divider[load_lvl];
487 ret = dev_pm_opp_add(cpu_dev, freq, u_volt);
488 if (ret)
489 goto remove_opp;
490
491
492 }
493
494 /* Now that everything is setup, enable the DVFS at hardware level */
495 armada37xx_cpufreq_enable_dvfs(nb_pm_base);
496
497 memset(&pdata, 0, sizeof(pdata));
498 pdata.suspend = armada37xx_cpufreq_suspend;
499 pdata.resume = armada37xx_cpufreq_resume;
500
501 pdev = platform_device_register_data(NULL, "cpufreq-dt", -1, &pdata,
502 sizeof(pdata));
503 ret = PTR_ERR_OR_ZERO(pdev);
504 if (ret)
505 goto disable_dvfs;
506
507 armada37xx_cpufreq_state->cpu_dev = cpu_dev;
508 armada37xx_cpufreq_state->pdev = pdev;
509 platform_set_drvdata(pdev, dvfs);
510 return 0;
511
512disable_dvfs:
513 armada37xx_cpufreq_disable_dvfs(nb_pm_base);
514remove_opp:
515 /* clean-up the already added opp before leaving */
516 while (load_lvl-- > ARMADA_37XX_DVFS_LOAD_0) {
517 freq = base_frequency / dvfs->divider[load_lvl];
518 dev_pm_opp_remove(cpu_dev, freq);
519 }
520
521 kfree(armada37xx_cpufreq_state);
522
523 return ret;
524}
525/* late_initcall, to guarantee the driver is loaded after A37xx clock driver */
526late_initcall(armada37xx_cpufreq_driver_init);
527
528static void __exit armada37xx_cpufreq_driver_exit(void)
529{
530 struct platform_device *pdev = armada37xx_cpufreq_state->pdev;
531 struct armada_37xx_dvfs *dvfs = platform_get_drvdata(pdev);
532 unsigned long freq;
533 int load_lvl;
534
535 platform_device_unregister(pdev);
536
537 armada37xx_cpufreq_disable_dvfs(armada37xx_cpufreq_state->regmap);
538
539 for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR; load_lvl++) {
540 freq = dvfs->cpu_freq_max / dvfs->divider[load_lvl];
541 dev_pm_opp_remove(armada37xx_cpufreq_state->cpu_dev, freq);
542 }
543
544 kfree(armada37xx_cpufreq_state);
545}
546module_exit(armada37xx_cpufreq_driver_exit);
547
548static const struct of_device_id __maybe_unused armada37xx_cpufreq_of_match[] = {
549 { .compatible = "marvell,armada-3700-nb-pm" },
550 { },
551};
552MODULE_DEVICE_TABLE(of, armada37xx_cpufreq_of_match);
553
554MODULE_AUTHOR("Gregory CLEMENT <[email protected]>");
555MODULE_DESCRIPTION("Armada 37xx cpufreq driver");
556MODULE_LICENSE("GPL");