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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Driver for the Atmel AHB DMA Controller (aka HDMA or DMAC on AT91 systems)
4 *
5 * Copyright (C) 2008 Atmel Corporation
6 * Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
7 *
8 * This supports the Atmel AHB DMA Controller found in several Atmel SoCs.
9 * The only Atmel DMA Controller that is not covered by this driver is the one
10 * found on AT91SAM9263.
11 */
12
13#include <dt-bindings/dma/at91.h>
14#include <linux/bitfield.h>
15#include <linux/clk.h>
16#include <linux/dmaengine.h>
17#include <linux/dmapool.h>
18#include <linux/dma-mapping.h>
19#include <linux/interrupt.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/overflow.h>
23#include <linux/of_platform.h>
24#include <linux/of_dma.h>
25#include <linux/platform_device.h>
26#include <linux/slab.h>
27
28#include "dmaengine.h"
29#include "virt-dma.h"
30
31/*
32 * Glossary
33 * --------
34 *
35 * at_hdmac : Name of the ATmel AHB DMA Controller
36 * at_dma_ / atdma : ATmel DMA controller entity related
37 * atc_ / atchan : ATmel DMA Channel entity related
38 */
39
40#define AT_DMA_MAX_NR_CHANNELS 8
41
42/* Global Configuration Register */
43#define AT_DMA_GCFG 0x00
44#define AT_DMA_IF_BIGEND(i) BIT((i)) /* AHB-Lite Interface i in Big-endian mode */
45#define AT_DMA_ARB_CFG BIT(4) /* Arbiter mode. */
46
47/* Controller Enable Register */
48#define AT_DMA_EN 0x04
49#define AT_DMA_ENABLE BIT(0)
50
51/* Software Single Request Register */
52#define AT_DMA_SREQ 0x08
53#define AT_DMA_SSREQ(x) BIT((x) << 1) /* Request a source single transfer on channel x */
54#define AT_DMA_DSREQ(x) BIT(1 + ((x) << 1)) /* Request a destination single transfer on channel x */
55
56/* Software Chunk Transfer Request Register */
57#define AT_DMA_CREQ 0x0c
58#define AT_DMA_SCREQ(x) BIT((x) << 1) /* Request a source chunk transfer on channel x */
59#define AT_DMA_DCREQ(x) BIT(1 + ((x) << 1)) /* Request a destination chunk transfer on channel x */
60
61/* Software Last Transfer Flag Register */
62#define AT_DMA_LAST 0x10
63#define AT_DMA_SLAST(x) BIT((x) << 1) /* This src rq is last tx of buffer on channel x */
64#define AT_DMA_DLAST(x) BIT(1 + ((x) << 1)) /* This dst rq is last tx of buffer on channel x */
65
66/* Request Synchronization Register */
67#define AT_DMA_SYNC 0x14
68#define AT_DMA_SYR(h) BIT((h)) /* Synchronize handshake line h */
69
70/* Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt registers */
71#define AT_DMA_EBCIER 0x18 /* Enable register */
72#define AT_DMA_EBCIDR 0x1c /* Disable register */
73#define AT_DMA_EBCIMR 0x20 /* Mask Register */
74#define AT_DMA_EBCISR 0x24 /* Status Register */
75#define AT_DMA_CBTC_OFFSET 8
76#define AT_DMA_ERR_OFFSET 16
77#define AT_DMA_BTC(x) BIT((x))
78#define AT_DMA_CBTC(x) BIT(AT_DMA_CBTC_OFFSET + (x))
79#define AT_DMA_ERR(x) BIT(AT_DMA_ERR_OFFSET + (x))
80
81/* Channel Handler Enable Register */
82#define AT_DMA_CHER 0x28
83#define AT_DMA_ENA(x) BIT((x))
84#define AT_DMA_SUSP(x) BIT(8 + (x))
85#define AT_DMA_KEEP(x) BIT(24 + (x))
86
87/* Channel Handler Disable Register */
88#define AT_DMA_CHDR 0x2c
89#define AT_DMA_DIS(x) BIT(x)
90#define AT_DMA_RES(x) BIT(8 + (x))
91
92/* Channel Handler Status Register */
93#define AT_DMA_CHSR 0x30
94#define AT_DMA_EMPT(x) BIT(16 + (x))
95#define AT_DMA_STAL(x) BIT(24 + (x))
96
97/* Channel registers base address */
98#define AT_DMA_CH_REGS_BASE 0x3c
99#define ch_regs(x) (AT_DMA_CH_REGS_BASE + (x) * 0x28) /* Channel x base addr */
100
101/* Hardware register offset for each channel */
102#define ATC_SADDR_OFFSET 0x00 /* Source Address Register */
103#define ATC_DADDR_OFFSET 0x04 /* Destination Address Register */
104#define ATC_DSCR_OFFSET 0x08 /* Descriptor Address Register */
105#define ATC_CTRLA_OFFSET 0x0c /* Control A Register */
106#define ATC_CTRLB_OFFSET 0x10 /* Control B Register */
107#define ATC_CFG_OFFSET 0x14 /* Configuration Register */
108#define ATC_SPIP_OFFSET 0x18 /* Src PIP Configuration Register */
109#define ATC_DPIP_OFFSET 0x1c /* Dst PIP Configuration Register */
110
111
112/* Bitfield definitions */
113
114/* Bitfields in DSCR */
115#define ATC_DSCR_IF GENMASK(1, 0) /* Dsc feched via AHB-Lite Interface */
116
117/* Bitfields in CTRLA */
118#define ATC_BTSIZE_MAX GENMASK(15, 0) /* Maximum Buffer Transfer Size */
119#define ATC_BTSIZE GENMASK(15, 0) /* Buffer Transfer Size */
120#define ATC_SCSIZE GENMASK(18, 16) /* Source Chunk Transfer Size */
121#define ATC_DCSIZE GENMASK(22, 20) /* Destination Chunk Transfer Size */
122#define ATC_SRC_WIDTH GENMASK(25, 24) /* Source Single Transfer Size */
123#define ATC_DST_WIDTH GENMASK(29, 28) /* Destination Single Transfer Size */
124#define ATC_DONE BIT(31) /* Tx Done (only written back in descriptor) */
125
126/* Bitfields in CTRLB */
127#define ATC_SIF GENMASK(1, 0) /* Src tx done via AHB-Lite Interface i */
128#define ATC_DIF GENMASK(5, 4) /* Dst tx done via AHB-Lite Interface i */
129#define AT_DMA_MEM_IF 0x0 /* interface 0 as memory interface */
130#define AT_DMA_PER_IF 0x1 /* interface 1 as peripheral interface */
131#define ATC_SRC_PIP BIT(8) /* Source Picture-in-Picture enabled */
132#define ATC_DST_PIP BIT(12) /* Destination Picture-in-Picture enabled */
133#define ATC_SRC_DSCR_DIS BIT(16) /* Src Descriptor fetch disable */
134#define ATC_DST_DSCR_DIS BIT(20) /* Dst Descriptor fetch disable */
135#define ATC_FC GENMASK(23, 21) /* Choose Flow Controller */
136#define ATC_FC_MEM2MEM 0x0 /* Mem-to-Mem (DMA) */
137#define ATC_FC_MEM2PER 0x1 /* Mem-to-Periph (DMA) */
138#define ATC_FC_PER2MEM 0x2 /* Periph-to-Mem (DMA) */
139#define ATC_FC_PER2PER 0x3 /* Periph-to-Periph (DMA) */
140#define ATC_FC_PER2MEM_PER 0x4 /* Periph-to-Mem (Peripheral) */
141#define ATC_FC_MEM2PER_PER 0x5 /* Mem-to-Periph (Peripheral) */
142#define ATC_FC_PER2PER_SRCPER 0x6 /* Periph-to-Periph (Src Peripheral) */
143#define ATC_FC_PER2PER_DSTPER 0x7 /* Periph-to-Periph (Dst Peripheral) */
144#define ATC_SRC_ADDR_MODE GENMASK(25, 24)
145#define ATC_SRC_ADDR_MODE_INCR 0x0 /* Incrementing Mode */
146#define ATC_SRC_ADDR_MODE_DECR 0x1 /* Decrementing Mode */
147#define ATC_SRC_ADDR_MODE_FIXED 0x2 /* Fixed Mode */
148#define ATC_DST_ADDR_MODE GENMASK(29, 28)
149#define ATC_DST_ADDR_MODE_INCR 0x0 /* Incrementing Mode */
150#define ATC_DST_ADDR_MODE_DECR 0x1 /* Decrementing Mode */
151#define ATC_DST_ADDR_MODE_FIXED 0x2 /* Fixed Mode */
152#define ATC_IEN BIT(30) /* BTC interrupt enable (active low) */
153#define ATC_AUTO BIT(31) /* Auto multiple buffer tx enable */
154
155/* Bitfields in CFG */
156#define ATC_SRC_PER GENMASK(3, 0) /* Channel src rq associated with periph handshaking ifc h */
157#define ATC_DST_PER GENMASK(7, 4) /* Channel dst rq associated with periph handshaking ifc h */
158#define ATC_SRC_REP BIT(8) /* Source Replay Mod */
159#define ATC_SRC_H2SEL BIT(9) /* Source Handshaking Mod */
160#define ATC_SRC_PER_MSB GENMASK(11, 10) /* Channel src rq (most significant bits) */
161#define ATC_DST_REP BIT(12) /* Destination Replay Mod */
162#define ATC_DST_H2SEL BIT(13) /* Destination Handshaking Mod */
163#define ATC_DST_PER_MSB GENMASK(15, 14) /* Channel dst rq (most significant bits) */
164#define ATC_SOD BIT(16) /* Stop On Done */
165#define ATC_LOCK_IF BIT(20) /* Interface Lock */
166#define ATC_LOCK_B BIT(21) /* AHB Bus Lock */
167#define ATC_LOCK_IF_L BIT(22) /* Master Interface Arbiter Lock */
168#define ATC_AHB_PROT GENMASK(26, 24) /* AHB Protection */
169#define ATC_FIFOCFG GENMASK(29, 28) /* FIFO Request Configuration */
170#define ATC_FIFOCFG_LARGESTBURST 0x0
171#define ATC_FIFOCFG_HALFFIFO 0x1
172#define ATC_FIFOCFG_ENOUGHSPACE 0x2
173
174/* Bitfields in SPIP */
175#define ATC_SPIP_HOLE GENMASK(15, 0)
176#define ATC_SPIP_BOUNDARY GENMASK(25, 16)
177
178/* Bitfields in DPIP */
179#define ATC_DPIP_HOLE GENMASK(15, 0)
180#define ATC_DPIP_BOUNDARY GENMASK(25, 16)
181
182#define ATC_PER_MSB GENMASK(5, 4) /* Extract MSBs of a handshaking identifier */
183#define ATC_SRC_PER_ID(id) \
184 ({ typeof(id) _id = (id); \
185 FIELD_PREP(ATC_SRC_PER_MSB, FIELD_GET(ATC_PER_MSB, _id)) | \
186 FIELD_PREP(ATC_SRC_PER, _id); })
187#define ATC_DST_PER_ID(id) \
188 ({ typeof(id) _id = (id); \
189 FIELD_PREP(ATC_DST_PER_MSB, FIELD_GET(ATC_PER_MSB, _id)) | \
190 FIELD_PREP(ATC_DST_PER, _id); })
191
192
193
194/*-- descriptors -----------------------------------------------------*/
195
196/* LLI == Linked List Item; aka DMA buffer descriptor */
197struct at_lli {
198 /* values that are not changed by hardware */
199 u32 saddr;
200 u32 daddr;
201 /* value that may get written back: */
202 u32 ctrla;
203 /* more values that are not changed by hardware */
204 u32 ctrlb;
205 u32 dscr; /* chain to next lli */
206};
207
208/**
209 * struct atdma_sg - atdma scatter gather entry
210 * @len: length of the current Linked List Item.
211 * @lli: linked list item that is passed to the DMA controller
212 * @lli_phys: physical address of the LLI.
213 */
214struct atdma_sg {
215 unsigned int len;
216 struct at_lli *lli;
217 dma_addr_t lli_phys;
218};
219
220/**
221 * struct at_desc - software descriptor
222 * @vd: pointer to the virtual dma descriptor.
223 * @atchan: pointer to the atmel dma channel.
224 * @total_len: total transaction byte count
225 * @sglen: number of sg entries.
226 * @sg: array of sgs.
227 * @boundary: number of transfers to perform before the automatic address increment operation
228 * @dst_hole: value to add to the destination address when the boundary has been reached
229 * @src_hole: value to add to the source address when the boundary has been reached
230 * @memset_buffer: buffer used for the memset operation
231 * @memset_paddr: physical address of the buffer used for the memset operation
232 * @memset_vaddr: virtual address of the buffer used for the memset operation
233 */
234struct at_desc {
235 struct virt_dma_desc vd;
236 struct at_dma_chan *atchan;
237 size_t total_len;
238 unsigned int sglen;
239 /* Interleaved data */
240 size_t boundary;
241 size_t dst_hole;
242 size_t src_hole;
243
244 /* Memset temporary buffer */
245 bool memset_buffer;
246 dma_addr_t memset_paddr;
247 int *memset_vaddr;
248 struct atdma_sg sg[] __counted_by(sglen);
249};
250
251/*-- Channels --------------------------------------------------------*/
252
253/**
254 * enum atc_status - information bits stored in channel status flag
255 *
256 * @ATC_IS_PAUSED: If channel is pauses
257 * @ATC_IS_CYCLIC: If channel is cyclic
258 *
259 * Manipulated with atomic operations.
260 */
261enum atc_status {
262 ATC_IS_PAUSED = 1,
263 ATC_IS_CYCLIC = 24,
264};
265
266/**
267 * struct at_dma_chan - internal representation of an Atmel HDMAC channel
268 * @vc: virtual dma channel entry.
269 * @atdma: pointer to the driver data.
270 * @ch_regs: memory mapped register base
271 * @mask: channel index in a mask
272 * @per_if: peripheral interface
273 * @mem_if: memory interface
274 * @status: transmit status information from irq/prep* functions
275 * to tasklet (use atomic operations)
276 * @save_cfg: configuration register that is saved on suspend/resume cycle
277 * @save_dscr: for cyclic operations, preserve next descriptor address in
278 * the cyclic list on suspend/resume cycle
279 * @dma_sconfig: configuration for slave transfers, passed via
280 * .device_config
281 * @desc: pointer to the atmel dma descriptor.
282 */
283struct at_dma_chan {
284 struct virt_dma_chan vc;
285 struct at_dma *atdma;
286 void __iomem *ch_regs;
287 u8 mask;
288 u8 per_if;
289 u8 mem_if;
290 unsigned long status;
291 u32 save_cfg;
292 u32 save_dscr;
293 struct dma_slave_config dma_sconfig;
294 struct at_desc *desc;
295};
296
297#define channel_readl(atchan, name) \
298 __raw_readl((atchan)->ch_regs + ATC_##name##_OFFSET)
299
300#define channel_writel(atchan, name, val) \
301 __raw_writel((val), (atchan)->ch_regs + ATC_##name##_OFFSET)
302
303/*
304 * Fix sconfig's burst size according to at_hdmac. We need to convert them as:
305 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3, 32 -> 4, 64 -> 5, 128 -> 6, 256 -> 7.
306 *
307 * This can be done by finding most significant bit set.
308 */
309static inline void convert_burst(u32 *maxburst)
310{
311 if (*maxburst > 1)
312 *maxburst = fls(*maxburst) - 2;
313 else
314 *maxburst = 0;
315}
316
317/*
318 * Fix sconfig's bus width according to at_hdmac.
319 * 1 byte -> 0, 2 bytes -> 1, 4 bytes -> 2.
320 */
321static inline u8 convert_buswidth(enum dma_slave_buswidth addr_width)
322{
323 switch (addr_width) {
324 case DMA_SLAVE_BUSWIDTH_2_BYTES:
325 return 1;
326 case DMA_SLAVE_BUSWIDTH_4_BYTES:
327 return 2;
328 default:
329 /* For 1 byte width or fallback */
330 return 0;
331 }
332}
333
334/*-- Controller ------------------------------------------------------*/
335
336/**
337 * struct at_dma - internal representation of an Atmel HDMA Controller
338 * @dma_device: dmaengine dma_device object members
339 * @regs: memory mapped register base
340 * @clk: dma controller clock
341 * @save_imr: interrupt mask register that is saved on suspend/resume cycle
342 * @all_chan_mask: all channels available in a mask
343 * @lli_pool: hw lli table
344 * @memset_pool: hw memset pool
345 * @chan: channels table to store at_dma_chan structures
346 */
347struct at_dma {
348 struct dma_device dma_device;
349 void __iomem *regs;
350 struct clk *clk;
351 u32 save_imr;
352
353 u8 all_chan_mask;
354
355 struct dma_pool *lli_pool;
356 struct dma_pool *memset_pool;
357 /* AT THE END channels table */
358 struct at_dma_chan chan[];
359};
360
361#define dma_readl(atdma, name) \
362 __raw_readl((atdma)->regs + AT_DMA_##name)
363#define dma_writel(atdma, name, val) \
364 __raw_writel((val), (atdma)->regs + AT_DMA_##name)
365
366static inline struct at_desc *to_atdma_desc(struct dma_async_tx_descriptor *t)
367{
368 return container_of(t, struct at_desc, vd.tx);
369}
370
371static inline struct at_dma_chan *to_at_dma_chan(struct dma_chan *chan)
372{
373 return container_of(chan, struct at_dma_chan, vc.chan);
374}
375
376static inline struct at_dma *to_at_dma(struct dma_device *ddev)
377{
378 return container_of(ddev, struct at_dma, dma_device);
379}
380
381
382/*-- Helper functions ------------------------------------------------*/
383
384static struct device *chan2dev(struct dma_chan *chan)
385{
386 return &chan->dev->device;
387}
388
389#if defined(VERBOSE_DEBUG)
390static void vdbg_dump_regs(struct at_dma_chan *atchan)
391{
392 struct at_dma *atdma = to_at_dma(atchan->vc.chan.device);
393
394 dev_err(chan2dev(&atchan->vc.chan),
395 " channel %d : imr = 0x%x, chsr = 0x%x\n",
396 atchan->vc.chan.chan_id,
397 dma_readl(atdma, EBCIMR),
398 dma_readl(atdma, CHSR));
399
400 dev_err(chan2dev(&atchan->vc.chan),
401 " channel: s0x%x d0x%x ctrl0x%x:0x%x cfg0x%x l0x%x\n",
402 channel_readl(atchan, SADDR),
403 channel_readl(atchan, DADDR),
404 channel_readl(atchan, CTRLA),
405 channel_readl(atchan, CTRLB),
406 channel_readl(atchan, CFG),
407 channel_readl(atchan, DSCR));
408}
409#else
410static void vdbg_dump_regs(struct at_dma_chan *atchan) {}
411#endif
412
413static void atc_dump_lli(struct at_dma_chan *atchan, struct at_lli *lli)
414{
415 dev_crit(chan2dev(&atchan->vc.chan),
416 "desc: s%pad d%pad ctrl0x%x:0x%x l%pad\n",
417 &lli->saddr, &lli->daddr,
418 lli->ctrla, lli->ctrlb, &lli->dscr);
419}
420
421
422static void atc_setup_irq(struct at_dma *atdma, int chan_id, int on)
423{
424 u32 ebci;
425
426 /* enable interrupts on buffer transfer completion & error */
427 ebci = AT_DMA_BTC(chan_id)
428 | AT_DMA_ERR(chan_id);
429 if (on)
430 dma_writel(atdma, EBCIER, ebci);
431 else
432 dma_writel(atdma, EBCIDR, ebci);
433}
434
435static void atc_enable_chan_irq(struct at_dma *atdma, int chan_id)
436{
437 atc_setup_irq(atdma, chan_id, 1);
438}
439
440static void atc_disable_chan_irq(struct at_dma *atdma, int chan_id)
441{
442 atc_setup_irq(atdma, chan_id, 0);
443}
444
445
446/**
447 * atc_chan_is_enabled - test if given channel is enabled
448 * @atchan: channel we want to test status
449 */
450static inline int atc_chan_is_enabled(struct at_dma_chan *atchan)
451{
452 struct at_dma *atdma = to_at_dma(atchan->vc.chan.device);
453
454 return !!(dma_readl(atdma, CHSR) & atchan->mask);
455}
456
457/**
458 * atc_chan_is_paused - test channel pause/resume status
459 * @atchan: channel we want to test status
460 */
461static inline int atc_chan_is_paused(struct at_dma_chan *atchan)
462{
463 return test_bit(ATC_IS_PAUSED, &atchan->status);
464}
465
466/**
467 * atc_chan_is_cyclic - test if given channel has cyclic property set
468 * @atchan: channel we want to test status
469 */
470static inline int atc_chan_is_cyclic(struct at_dma_chan *atchan)
471{
472 return test_bit(ATC_IS_CYCLIC, &atchan->status);
473}
474
475/**
476 * set_lli_eol - set end-of-link to descriptor so it will end transfer
477 * @desc: descriptor, signle or at the end of a chain, to end chain on
478 * @i: index of the atmel scatter gather entry that is at the end of the chain.
479 */
480static void set_lli_eol(struct at_desc *desc, unsigned int i)
481{
482 u32 ctrlb = desc->sg[i].lli->ctrlb;
483
484 ctrlb &= ~ATC_IEN;
485 ctrlb |= ATC_SRC_DSCR_DIS | ATC_DST_DSCR_DIS;
486
487 desc->sg[i].lli->ctrlb = ctrlb;
488 desc->sg[i].lli->dscr = 0;
489}
490
491#define ATC_DEFAULT_CFG FIELD_PREP(ATC_FIFOCFG, ATC_FIFOCFG_HALFFIFO)
492#define ATC_DEFAULT_CTRLB (FIELD_PREP(ATC_SIF, AT_DMA_MEM_IF) | \
493 FIELD_PREP(ATC_DIF, AT_DMA_MEM_IF))
494#define ATC_DMA_BUSWIDTHS\
495 (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) |\
496 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |\
497 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |\
498 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
499
500#define ATC_MAX_DSCR_TRIALS 10
501
502/*
503 * Initial number of descriptors to allocate for each channel. This could
504 * be increased during dma usage.
505 */
506static unsigned int init_nr_desc_per_channel = 64;
507module_param(init_nr_desc_per_channel, uint, 0644);
508MODULE_PARM_DESC(init_nr_desc_per_channel,
509 "initial descriptors per channel (default: 64)");
510
511/**
512 * struct at_dma_platform_data - Controller configuration parameters
513 * @nr_channels: Number of channels supported by hardware (max 8)
514 * @cap_mask: dma_capability flags supported by the platform
515 */
516struct at_dma_platform_data {
517 unsigned int nr_channels;
518 dma_cap_mask_t cap_mask;
519};
520
521/**
522 * struct at_dma_slave - Controller-specific information about a slave
523 * @dma_dev: required DMA master device
524 * @cfg: Platform-specific initializer for the CFG register
525 */
526struct at_dma_slave {
527 struct device *dma_dev;
528 u32 cfg;
529};
530
531static inline unsigned int atc_get_xfer_width(dma_addr_t src, dma_addr_t dst,
532 size_t len)
533{
534 unsigned int width;
535
536 if (!((src | dst | len) & 3))
537 width = 2;
538 else if (!((src | dst | len) & 1))
539 width = 1;
540 else
541 width = 0;
542
543 return width;
544}
545
546static void atdma_lli_chain(struct at_desc *desc, unsigned int i)
547{
548 struct atdma_sg *atdma_sg = &desc->sg[i];
549
550 if (i)
551 desc->sg[i - 1].lli->dscr = atdma_sg->lli_phys;
552}
553
554/**
555 * atc_dostart - starts the DMA engine for real
556 * @atchan: the channel we want to start
557 */
558static void atc_dostart(struct at_dma_chan *atchan)
559{
560 struct virt_dma_desc *vd = vchan_next_desc(&atchan->vc);
561 struct at_desc *desc;
562
563 if (!vd) {
564 atchan->desc = NULL;
565 return;
566 }
567
568 vdbg_dump_regs(atchan);
569
570 list_del(&vd->node);
571 atchan->desc = desc = to_atdma_desc(&vd->tx);
572
573 channel_writel(atchan, SADDR, 0);
574 channel_writel(atchan, DADDR, 0);
575 channel_writel(atchan, CTRLA, 0);
576 channel_writel(atchan, CTRLB, 0);
577 channel_writel(atchan, DSCR, desc->sg[0].lli_phys);
578 channel_writel(atchan, SPIP,
579 FIELD_PREP(ATC_SPIP_HOLE, desc->src_hole) |
580 FIELD_PREP(ATC_SPIP_BOUNDARY, desc->boundary));
581 channel_writel(atchan, DPIP,
582 FIELD_PREP(ATC_DPIP_HOLE, desc->dst_hole) |
583 FIELD_PREP(ATC_DPIP_BOUNDARY, desc->boundary));
584
585 /* Don't allow CPU to reorder channel enable. */
586 wmb();
587 dma_writel(atchan->atdma, CHER, atchan->mask);
588
589 vdbg_dump_regs(atchan);
590}
591
592static void atdma_desc_free(struct virt_dma_desc *vd)
593{
594 struct at_dma *atdma = to_at_dma(vd->tx.chan->device);
595 struct at_desc *desc = to_atdma_desc(&vd->tx);
596 unsigned int i;
597
598 for (i = 0; i < desc->sglen; i++) {
599 if (desc->sg[i].lli)
600 dma_pool_free(atdma->lli_pool, desc->sg[i].lli,
601 desc->sg[i].lli_phys);
602 }
603
604 /* If the transfer was a memset, free our temporary buffer */
605 if (desc->memset_buffer) {
606 dma_pool_free(atdma->memset_pool, desc->memset_vaddr,
607 desc->memset_paddr);
608 desc->memset_buffer = false;
609 }
610
611 kfree(desc);
612}
613
614/**
615 * atc_calc_bytes_left - calculates the number of bytes left according to the
616 * value read from CTRLA.
617 *
618 * @current_len: the number of bytes left before reading CTRLA
619 * @ctrla: the value of CTRLA
620 */
621static inline u32 atc_calc_bytes_left(u32 current_len, u32 ctrla)
622{
623 u32 btsize = FIELD_GET(ATC_BTSIZE, ctrla);
624 u32 src_width = FIELD_GET(ATC_SRC_WIDTH, ctrla);
625
626 /*
627 * According to the datasheet, when reading the Control A Register
628 * (ctrla), the Buffer Transfer Size (btsize) bitfield refers to the
629 * number of transfers completed on the Source Interface.
630 * So btsize is always a number of source width transfers.
631 */
632 return current_len - (btsize << src_width);
633}
634
635/**
636 * atc_get_llis_residue - Get residue for a hardware linked list transfer
637 * @atchan: pointer to an atmel hdmac channel.
638 * @desc: pointer to the descriptor for which the residue is calculated.
639 * @residue: residue to be set to dma_tx_state.
640 *
641 * Calculate the residue by removing the length of the Linked List Item (LLI)
642 * already transferred from the total length. To get the current LLI we can use
643 * the value of the channel's DSCR register and compare it against the DSCR
644 * value of each LLI.
645 *
646 * The CTRLA register provides us with the amount of data already read from the
647 * source for the LLI. So we can compute a more accurate residue by also
648 * removing the number of bytes corresponding to this amount of data.
649 *
650 * However, the DSCR and CTRLA registers cannot be read both atomically. Hence a
651 * race condition may occur: the first read register may refer to one LLI
652 * whereas the second read may refer to a later LLI in the list because of the
653 * DMA transfer progression inbetween the two reads.
654 *
655 * One solution could have been to pause the DMA transfer, read the DSCR and
656 * CTRLA then resume the DMA transfer. Nonetheless, this approach presents some
657 * drawbacks:
658 * - If the DMA transfer is paused, RX overruns or TX underruns are more likey
659 * to occur depending on the system latency. Taking the USART driver as an
660 * example, it uses a cyclic DMA transfer to read data from the Receive
661 * Holding Register (RHR) to avoid RX overruns since the RHR is not protected
662 * by any FIFO on most Atmel SoCs. So pausing the DMA transfer to compute the
663 * residue would break the USART driver design.
664 * - The atc_pause() function masks interrupts but we'd rather avoid to do so
665 * for system latency purpose.
666 *
667 * Then we'd rather use another solution: the DSCR is read a first time, the
668 * CTRLA is read in turn, next the DSCR is read a second time. If the two
669 * consecutive read values of the DSCR are the same then we assume both refers
670 * to the very same LLI as well as the CTRLA value read inbetween does. For
671 * cyclic transfers, the assumption is that a full loop is "not so fast". If the
672 * two DSCR values are different, we read again the CTRLA then the DSCR till two
673 * consecutive read values from DSCR are equal or till the maximum trials is
674 * reach. This algorithm is very unlikely not to find a stable value for DSCR.
675 *
676 * Returns: %0 on success, -errno otherwise.
677 */
678static int atc_get_llis_residue(struct at_dma_chan *atchan,
679 struct at_desc *desc, u32 *residue)
680{
681 u32 len, ctrla, dscr;
682 unsigned int i;
683
684 len = desc->total_len;
685 dscr = channel_readl(atchan, DSCR);
686 rmb(); /* ensure DSCR is read before CTRLA */
687 ctrla = channel_readl(atchan, CTRLA);
688 for (i = 0; i < ATC_MAX_DSCR_TRIALS; ++i) {
689 u32 new_dscr;
690
691 rmb(); /* ensure DSCR is read after CTRLA */
692 new_dscr = channel_readl(atchan, DSCR);
693
694 /*
695 * If the DSCR register value has not changed inside the DMA
696 * controller since the previous read, we assume that both the
697 * dscr and ctrla values refers to the very same descriptor.
698 */
699 if (likely(new_dscr == dscr))
700 break;
701
702 /*
703 * DSCR has changed inside the DMA controller, so the previously
704 * read value of CTRLA may refer to an already processed
705 * descriptor hence could be outdated. We need to update ctrla
706 * to match the current descriptor.
707 */
708 dscr = new_dscr;
709 rmb(); /* ensure DSCR is read before CTRLA */
710 ctrla = channel_readl(atchan, CTRLA);
711 }
712 if (unlikely(i == ATC_MAX_DSCR_TRIALS))
713 return -ETIMEDOUT;
714
715 /* For the first descriptor we can be more accurate. */
716 if (desc->sg[0].lli->dscr == dscr) {
717 *residue = atc_calc_bytes_left(len, ctrla);
718 return 0;
719 }
720 len -= desc->sg[0].len;
721
722 for (i = 1; i < desc->sglen; i++) {
723 if (desc->sg[i].lli && desc->sg[i].lli->dscr == dscr)
724 break;
725 len -= desc->sg[i].len;
726 }
727
728 /*
729 * For the current LLI in the chain we can calculate the remaining bytes
730 * using the channel's CTRLA register.
731 */
732 *residue = atc_calc_bytes_left(len, ctrla);
733 return 0;
734
735}
736
737/**
738 * atc_get_residue - get the number of bytes residue for a cookie.
739 * The residue is passed by address and updated on success.
740 * @chan: DMA channel
741 * @cookie: transaction identifier to check status of
742 * @residue: residue to be updated.
743 *
744 * Return: %0 on success, -errno otherwise.
745 */
746static int atc_get_residue(struct dma_chan *chan, dma_cookie_t cookie,
747 u32 *residue)
748{
749 struct at_dma_chan *atchan = to_at_dma_chan(chan);
750 struct virt_dma_desc *vd;
751 struct at_desc *desc = NULL;
752 u32 len, ctrla;
753
754 vd = vchan_find_desc(&atchan->vc, cookie);
755 if (vd)
756 desc = to_atdma_desc(&vd->tx);
757 else if (atchan->desc && atchan->desc->vd.tx.cookie == cookie)
758 desc = atchan->desc;
759
760 if (!desc)
761 return -EINVAL;
762
763 if (desc->sg[0].lli->dscr)
764 /* hardware linked list transfer */
765 return atc_get_llis_residue(atchan, desc, residue);
766
767 /* single transfer */
768 len = desc->total_len;
769 ctrla = channel_readl(atchan, CTRLA);
770 *residue = atc_calc_bytes_left(len, ctrla);
771 return 0;
772}
773
774/**
775 * atc_handle_error - handle errors reported by DMA controller
776 * @atchan: channel where error occurs.
777 * @i: channel index
778 */
779static void atc_handle_error(struct at_dma_chan *atchan, unsigned int i)
780{
781 struct at_desc *desc = atchan->desc;
782
783 /* Disable channel on AHB error */
784 dma_writel(atchan->atdma, CHDR, AT_DMA_RES(i) | atchan->mask);
785
786 /*
787 * KERN_CRITICAL may seem harsh, but since this only happens
788 * when someone submits a bad physical address in a
789 * descriptor, we should consider ourselves lucky that the
790 * controller flagged an error instead of scribbling over
791 * random memory locations.
792 */
793 dev_crit(chan2dev(&atchan->vc.chan), "Bad descriptor submitted for DMA!\n");
794 dev_crit(chan2dev(&atchan->vc.chan), "cookie: %d\n",
795 desc->vd.tx.cookie);
796 for (i = 0; i < desc->sglen; i++)
797 atc_dump_lli(atchan, desc->sg[i].lli);
798}
799
800static void atdma_handle_chan_done(struct at_dma_chan *atchan, u32 pending,
801 unsigned int i)
802{
803 struct at_desc *desc;
804
805 spin_lock(&atchan->vc.lock);
806 desc = atchan->desc;
807
808 if (desc) {
809 if (pending & AT_DMA_ERR(i)) {
810 atc_handle_error(atchan, i);
811 /* Pretend the descriptor completed successfully */
812 }
813
814 if (atc_chan_is_cyclic(atchan)) {
815 vchan_cyclic_callback(&desc->vd);
816 } else {
817 vchan_cookie_complete(&desc->vd);
818 atchan->desc = NULL;
819 if (!(atc_chan_is_enabled(atchan)))
820 atc_dostart(atchan);
821 }
822 }
823 spin_unlock(&atchan->vc.lock);
824}
825
826static irqreturn_t at_dma_interrupt(int irq, void *dev_id)
827{
828 struct at_dma *atdma = dev_id;
829 struct at_dma_chan *atchan;
830 int i;
831 u32 status, pending, imr;
832 int ret = IRQ_NONE;
833
834 do {
835 imr = dma_readl(atdma, EBCIMR);
836 status = dma_readl(atdma, EBCISR);
837 pending = status & imr;
838
839 if (!pending)
840 break;
841
842 dev_vdbg(atdma->dma_device.dev,
843 "interrupt: status = 0x%08x, 0x%08x, 0x%08x\n",
844 status, imr, pending);
845
846 for (i = 0; i < atdma->dma_device.chancnt; i++) {
847 atchan = &atdma->chan[i];
848 if (!(pending & (AT_DMA_BTC(i) | AT_DMA_ERR(i))))
849 continue;
850 atdma_handle_chan_done(atchan, pending, i);
851 ret = IRQ_HANDLED;
852 }
853
854 } while (pending);
855
856 return ret;
857}
858
859/*-- DMA Engine API --------------------------------------------------*/
860/**
861 * atc_prep_dma_interleaved - prepare memory to memory interleaved operation
862 * @chan: the channel to prepare operation on
863 * @xt: Interleaved transfer template
864 * @flags: tx descriptor status flags
865 */
866static struct dma_async_tx_descriptor *
867atc_prep_dma_interleaved(struct dma_chan *chan,
868 struct dma_interleaved_template *xt,
869 unsigned long flags)
870{
871 struct at_dma *atdma = to_at_dma(chan->device);
872 struct at_dma_chan *atchan = to_at_dma_chan(chan);
873 struct data_chunk *first;
874 struct atdma_sg *atdma_sg;
875 struct at_desc *desc;
876 struct at_lli *lli;
877 size_t xfer_count;
878 unsigned int dwidth;
879 u32 ctrla;
880 u32 ctrlb;
881 size_t len = 0;
882 int i;
883
884 if (unlikely(!xt || xt->numf != 1 || !xt->frame_size))
885 return NULL;
886
887 first = xt->sgl;
888
889 dev_info(chan2dev(chan),
890 "%s: src=%pad, dest=%pad, numf=%zu, frame_size=%zu, flags=0x%lx\n",
891 __func__, &xt->src_start, &xt->dst_start, xt->numf,
892 xt->frame_size, flags);
893
894 /*
895 * The controller can only "skip" X bytes every Y bytes, so we
896 * need to make sure we are given a template that fit that
897 * description, ie a template with chunks that always have the
898 * same size, with the same ICGs.
899 */
900 for (i = 0; i < xt->frame_size; i++) {
901 struct data_chunk *chunk = xt->sgl + i;
902
903 if ((chunk->size != xt->sgl->size) ||
904 (dmaengine_get_dst_icg(xt, chunk) != dmaengine_get_dst_icg(xt, first)) ||
905 (dmaengine_get_src_icg(xt, chunk) != dmaengine_get_src_icg(xt, first))) {
906 dev_err(chan2dev(chan),
907 "%s: the controller can transfer only identical chunks\n",
908 __func__);
909 return NULL;
910 }
911
912 len += chunk->size;
913 }
914
915 dwidth = atc_get_xfer_width(xt->src_start, xt->dst_start, len);
916
917 xfer_count = len >> dwidth;
918 if (xfer_count > ATC_BTSIZE_MAX) {
919 dev_err(chan2dev(chan), "%s: buffer is too big\n", __func__);
920 return NULL;
921 }
922
923 ctrla = FIELD_PREP(ATC_SRC_WIDTH, dwidth) |
924 FIELD_PREP(ATC_DST_WIDTH, dwidth);
925
926 ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN |
927 FIELD_PREP(ATC_SRC_ADDR_MODE, ATC_SRC_ADDR_MODE_INCR) |
928 FIELD_PREP(ATC_DST_ADDR_MODE, ATC_DST_ADDR_MODE_INCR) |
929 ATC_SRC_PIP | ATC_DST_PIP |
930 FIELD_PREP(ATC_FC, ATC_FC_MEM2MEM);
931
932 desc = kzalloc_flex(*desc, sg, 1, GFP_ATOMIC);
933 if (!desc)
934 return NULL;
935 desc->sglen = 1;
936
937 atdma_sg = desc->sg;
938 atdma_sg->lli = dma_pool_alloc(atdma->lli_pool, GFP_NOWAIT,
939 &atdma_sg->lli_phys);
940 if (!atdma_sg->lli) {
941 kfree(desc);
942 return NULL;
943 }
944 lli = atdma_sg->lli;
945
946 lli->saddr = xt->src_start;
947 lli->daddr = xt->dst_start;
948 lli->ctrla = ctrla | xfer_count;
949 lli->ctrlb = ctrlb;
950
951 desc->boundary = first->size >> dwidth;
952 desc->dst_hole = (dmaengine_get_dst_icg(xt, first) >> dwidth) + 1;
953 desc->src_hole = (dmaengine_get_src_icg(xt, first) >> dwidth) + 1;
954
955 atdma_sg->len = len;
956 desc->total_len = len;
957
958 set_lli_eol(desc, 0);
959 return vchan_tx_prep(&atchan->vc, &desc->vd, flags);
960}
961
962/**
963 * atc_prep_dma_memcpy - prepare a memcpy operation
964 * @chan: the channel to prepare operation on
965 * @dest: operation virtual destination address
966 * @src: operation virtual source address
967 * @len: operation length
968 * @flags: tx descriptor status flags
969 */
970static struct dma_async_tx_descriptor *
971atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
972 size_t len, unsigned long flags)
973{
974 struct at_dma *atdma = to_at_dma(chan->device);
975 struct at_dma_chan *atchan = to_at_dma_chan(chan);
976 struct at_desc *desc = NULL;
977 size_t xfer_count;
978 size_t offset;
979 size_t sg_len;
980 unsigned int src_width;
981 unsigned int dst_width;
982 unsigned int i;
983 u32 ctrla;
984 u32 ctrlb;
985
986 dev_dbg(chan2dev(chan), "prep_dma_memcpy: d%pad s%pad l0x%zx f0x%lx\n",
987 &dest, &src, len, flags);
988
989 if (unlikely(!len)) {
990 dev_err(chan2dev(chan), "prep_dma_memcpy: length is zero!\n");
991 return NULL;
992 }
993
994 sg_len = DIV_ROUND_UP(len, ATC_BTSIZE_MAX);
995 desc = kzalloc_flex(*desc, sg, sg_len, GFP_ATOMIC);
996 if (!desc)
997 return NULL;
998 desc->sglen = sg_len;
999
1000 ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN |
1001 FIELD_PREP(ATC_SRC_ADDR_MODE, ATC_SRC_ADDR_MODE_INCR) |
1002 FIELD_PREP(ATC_DST_ADDR_MODE, ATC_DST_ADDR_MODE_INCR) |
1003 FIELD_PREP(ATC_FC, ATC_FC_MEM2MEM);
1004
1005 /*
1006 * We can be a lot more clever here, but this should take care
1007 * of the most common optimization.
1008 */
1009 src_width = dst_width = atc_get_xfer_width(src, dest, len);
1010
1011 ctrla = FIELD_PREP(ATC_SRC_WIDTH, src_width) |
1012 FIELD_PREP(ATC_DST_WIDTH, dst_width);
1013
1014 for (offset = 0, i = 0; offset < len;
1015 offset += xfer_count << src_width, i++) {
1016 struct atdma_sg *atdma_sg = &desc->sg[i];
1017 struct at_lli *lli;
1018
1019 atdma_sg->lli = dma_pool_alloc(atdma->lli_pool, GFP_NOWAIT,
1020 &atdma_sg->lli_phys);
1021 if (!atdma_sg->lli)
1022 goto err_desc_get;
1023 lli = atdma_sg->lli;
1024
1025 xfer_count = min_t(size_t, (len - offset) >> src_width,
1026 ATC_BTSIZE_MAX);
1027
1028 lli->saddr = src + offset;
1029 lli->daddr = dest + offset;
1030 lli->ctrla = ctrla | xfer_count;
1031 lli->ctrlb = ctrlb;
1032
1033 desc->sg[i].len = xfer_count << src_width;
1034
1035 atdma_lli_chain(desc, i);
1036 }
1037
1038 desc->total_len = len;
1039
1040 /* set end-of-link to the last link descriptor of list*/
1041 set_lli_eol(desc, i - 1);
1042
1043 return vchan_tx_prep(&atchan->vc, &desc->vd, flags);
1044
1045err_desc_get:
1046 atdma_desc_free(&desc->vd);
1047 return NULL;
1048}
1049
1050static int atdma_create_memset_lli(struct dma_chan *chan,
1051 struct atdma_sg *atdma_sg,
1052 dma_addr_t psrc, dma_addr_t pdst, size_t len)
1053{
1054 struct at_dma *atdma = to_at_dma(chan->device);
1055 struct at_lli *lli;
1056 size_t xfer_count;
1057 u32 ctrla = FIELD_PREP(ATC_SRC_WIDTH, 2) | FIELD_PREP(ATC_DST_WIDTH, 2);
1058 u32 ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN |
1059 FIELD_PREP(ATC_SRC_ADDR_MODE, ATC_SRC_ADDR_MODE_FIXED) |
1060 FIELD_PREP(ATC_DST_ADDR_MODE, ATC_DST_ADDR_MODE_INCR) |
1061 FIELD_PREP(ATC_FC, ATC_FC_MEM2MEM);
1062
1063 xfer_count = len >> 2;
1064 if (xfer_count > ATC_BTSIZE_MAX) {
1065 dev_err(chan2dev(chan), "%s: buffer is too big\n", __func__);
1066 return -EINVAL;
1067 }
1068
1069 atdma_sg->lli = dma_pool_alloc(atdma->lli_pool, GFP_NOWAIT,
1070 &atdma_sg->lli_phys);
1071 if (!atdma_sg->lli)
1072 return -ENOMEM;
1073 lli = atdma_sg->lli;
1074
1075 lli->saddr = psrc;
1076 lli->daddr = pdst;
1077 lli->ctrla = ctrla | xfer_count;
1078 lli->ctrlb = ctrlb;
1079
1080 atdma_sg->len = len;
1081
1082 return 0;
1083}
1084
1085/**
1086 * atc_prep_dma_memset - prepare a memcpy operation
1087 * @chan: the channel to prepare operation on
1088 * @dest: operation virtual destination address
1089 * @value: value to set memory buffer to
1090 * @len: operation length
1091 * @flags: tx descriptor status flags
1092 */
1093static struct dma_async_tx_descriptor *
1094atc_prep_dma_memset(struct dma_chan *chan, dma_addr_t dest, int value,
1095 size_t len, unsigned long flags)
1096{
1097 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1098 struct at_dma *atdma = to_at_dma(chan->device);
1099 struct at_desc *desc;
1100 void __iomem *vaddr;
1101 dma_addr_t paddr;
1102 char fill_pattern;
1103 int ret;
1104
1105 dev_vdbg(chan2dev(chan), "%s: d%pad v0x%x l0x%zx f0x%lx\n", __func__,
1106 &dest, value, len, flags);
1107
1108 if (unlikely(!len)) {
1109 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
1110 return NULL;
1111 }
1112
1113 if (!is_dma_fill_aligned(chan->device, dest, 0, len)) {
1114 dev_dbg(chan2dev(chan), "%s: buffer is not aligned\n",
1115 __func__);
1116 return NULL;
1117 }
1118
1119 vaddr = dma_pool_alloc(atdma->memset_pool, GFP_NOWAIT, &paddr);
1120 if (!vaddr) {
1121 dev_err(chan2dev(chan), "%s: couldn't allocate buffer\n",
1122 __func__);
1123 return NULL;
1124 }
1125
1126 /* Only the first byte of value is to be used according to dmaengine */
1127 fill_pattern = (char)value;
1128
1129 *(u32*)vaddr = (fill_pattern << 24) |
1130 (fill_pattern << 16) |
1131 (fill_pattern << 8) |
1132 fill_pattern;
1133
1134 desc = kzalloc_flex(*desc, sg, 1, GFP_ATOMIC);
1135 if (!desc)
1136 goto err_free_buffer;
1137 desc->sglen = 1;
1138
1139 ret = atdma_create_memset_lli(chan, desc->sg, paddr, dest, len);
1140 if (ret)
1141 goto err_free_desc;
1142
1143 desc->memset_paddr = paddr;
1144 desc->memset_vaddr = vaddr;
1145 desc->memset_buffer = true;
1146
1147 desc->total_len = len;
1148
1149 /* set end-of-link on the descriptor */
1150 set_lli_eol(desc, 0);
1151
1152 return vchan_tx_prep(&atchan->vc, &desc->vd, flags);
1153
1154err_free_desc:
1155 kfree(desc);
1156err_free_buffer:
1157 dma_pool_free(atdma->memset_pool, vaddr, paddr);
1158 return NULL;
1159}
1160
1161static struct dma_async_tx_descriptor *
1162atc_prep_dma_memset_sg(struct dma_chan *chan,
1163 struct scatterlist *sgl,
1164 unsigned int sg_len, int value,
1165 unsigned long flags)
1166{
1167 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1168 struct at_dma *atdma = to_at_dma(chan->device);
1169 struct at_desc *desc;
1170 struct scatterlist *sg;
1171 void __iomem *vaddr;
1172 dma_addr_t paddr;
1173 size_t total_len = 0;
1174 int i;
1175 int ret;
1176
1177 dev_vdbg(chan2dev(chan), "%s: v0x%x l0x%x f0x%lx\n", __func__,
1178 value, sg_len, flags);
1179
1180 if (unlikely(!sgl || !sg_len)) {
1181 dev_dbg(chan2dev(chan), "%s: scatterlist is empty!\n",
1182 __func__);
1183 return NULL;
1184 }
1185
1186 vaddr = dma_pool_alloc(atdma->memset_pool, GFP_NOWAIT, &paddr);
1187 if (!vaddr) {
1188 dev_err(chan2dev(chan), "%s: couldn't allocate buffer\n",
1189 __func__);
1190 return NULL;
1191 }
1192 *(u32*)vaddr = value;
1193
1194 desc = kzalloc_flex(*desc, sg, sg_len, GFP_ATOMIC);
1195 if (!desc)
1196 goto err_free_dma_buf;
1197 desc->sglen = sg_len;
1198
1199 for_each_sg(sgl, sg, sg_len, i) {
1200 dma_addr_t dest = sg_dma_address(sg);
1201 size_t len = sg_dma_len(sg);
1202
1203 dev_vdbg(chan2dev(chan), "%s: d%pad, l0x%zx\n",
1204 __func__, &dest, len);
1205
1206 if (!is_dma_fill_aligned(chan->device, dest, 0, len)) {
1207 dev_err(chan2dev(chan), "%s: buffer is not aligned\n",
1208 __func__);
1209 goto err_free_desc;
1210 }
1211
1212 ret = atdma_create_memset_lli(chan, &desc->sg[i], paddr, dest,
1213 len);
1214 if (ret)
1215 goto err_free_desc;
1216
1217 atdma_lli_chain(desc, i);
1218 total_len += len;
1219 }
1220
1221 desc->memset_paddr = paddr;
1222 desc->memset_vaddr = vaddr;
1223 desc->memset_buffer = true;
1224
1225 desc->total_len = total_len;
1226
1227 /* set end-of-link on the descriptor */
1228 set_lli_eol(desc, i - 1);
1229
1230 return vchan_tx_prep(&atchan->vc, &desc->vd, flags);
1231
1232err_free_desc:
1233 atdma_desc_free(&desc->vd);
1234err_free_dma_buf:
1235 dma_pool_free(atdma->memset_pool, vaddr, paddr);
1236 return NULL;
1237}
1238
1239/**
1240 * atc_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
1241 * @chan: DMA channel
1242 * @sgl: scatterlist to transfer to/from
1243 * @sg_len: number of entries in @scatterlist
1244 * @direction: DMA direction
1245 * @flags: tx descriptor status flags
1246 * @context: transaction context (ignored)
1247 */
1248static struct dma_async_tx_descriptor *
1249atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
1250 unsigned int sg_len, enum dma_transfer_direction direction,
1251 unsigned long flags, void *context)
1252{
1253 struct at_dma *atdma = to_at_dma(chan->device);
1254 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1255 struct at_dma_slave *atslave = chan->private;
1256 struct dma_slave_config *sconfig = &atchan->dma_sconfig;
1257 struct at_desc *desc;
1258 u32 ctrla;
1259 u32 ctrlb;
1260 dma_addr_t reg;
1261 unsigned int reg_width;
1262 unsigned int mem_width;
1263 unsigned int i;
1264 struct scatterlist *sg;
1265 size_t total_len = 0;
1266
1267 dev_vdbg(chan2dev(chan), "prep_slave_sg (%d): %s f0x%lx\n",
1268 sg_len,
1269 direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE",
1270 flags);
1271
1272 if (unlikely(!atslave || !sg_len)) {
1273 dev_dbg(chan2dev(chan), "prep_slave_sg: sg length is zero!\n");
1274 return NULL;
1275 }
1276
1277 desc = kzalloc_flex(*desc, sg, sg_len, GFP_ATOMIC);
1278 if (!desc)
1279 return NULL;
1280 desc->sglen = sg_len;
1281
1282 ctrla = FIELD_PREP(ATC_SCSIZE, sconfig->src_maxburst) |
1283 FIELD_PREP(ATC_DCSIZE, sconfig->dst_maxburst);
1284 ctrlb = ATC_IEN;
1285
1286 switch (direction) {
1287 case DMA_MEM_TO_DEV:
1288 reg_width = convert_buswidth(sconfig->dst_addr_width);
1289 ctrla |= FIELD_PREP(ATC_DST_WIDTH, reg_width);
1290 ctrlb |= FIELD_PREP(ATC_DST_ADDR_MODE,
1291 ATC_DST_ADDR_MODE_FIXED) |
1292 FIELD_PREP(ATC_SRC_ADDR_MODE, ATC_SRC_ADDR_MODE_INCR) |
1293 FIELD_PREP(ATC_FC, ATC_FC_MEM2PER) |
1294 FIELD_PREP(ATC_SIF, atchan->mem_if) |
1295 FIELD_PREP(ATC_DIF, atchan->per_if);
1296 reg = sconfig->dst_addr;
1297 for_each_sg(sgl, sg, sg_len, i) {
1298 struct atdma_sg *atdma_sg = &desc->sg[i];
1299 struct at_lli *lli;
1300 u32 len;
1301 u32 mem;
1302
1303 atdma_sg->lli = dma_pool_alloc(atdma->lli_pool,
1304 GFP_NOWAIT,
1305 &atdma_sg->lli_phys);
1306 if (!atdma_sg->lli)
1307 goto err_desc_get;
1308 lli = atdma_sg->lli;
1309
1310 mem = sg_dma_address(sg);
1311 len = sg_dma_len(sg);
1312 if (unlikely(!len)) {
1313 dev_dbg(chan2dev(chan),
1314 "prep_slave_sg: sg(%d) data length is zero\n", i);
1315 goto err;
1316 }
1317 mem_width = 2;
1318 if (unlikely(mem & 3 || len & 3))
1319 mem_width = 0;
1320
1321 lli->saddr = mem;
1322 lli->daddr = reg;
1323 lli->ctrla = ctrla |
1324 FIELD_PREP(ATC_SRC_WIDTH, mem_width) |
1325 len >> mem_width;
1326 lli->ctrlb = ctrlb;
1327
1328 atdma_sg->len = len;
1329 total_len += len;
1330
1331 desc->sg[i].len = len;
1332 atdma_lli_chain(desc, i);
1333 }
1334 break;
1335 case DMA_DEV_TO_MEM:
1336 reg_width = convert_buswidth(sconfig->src_addr_width);
1337 ctrla |= FIELD_PREP(ATC_SRC_WIDTH, reg_width);
1338 ctrlb |= FIELD_PREP(ATC_DST_ADDR_MODE, ATC_DST_ADDR_MODE_INCR) |
1339 FIELD_PREP(ATC_SRC_ADDR_MODE,
1340 ATC_SRC_ADDR_MODE_FIXED) |
1341 FIELD_PREP(ATC_FC, ATC_FC_PER2MEM) |
1342 FIELD_PREP(ATC_SIF, atchan->per_if) |
1343 FIELD_PREP(ATC_DIF, atchan->mem_if);
1344
1345 reg = sconfig->src_addr;
1346 for_each_sg(sgl, sg, sg_len, i) {
1347 struct atdma_sg *atdma_sg = &desc->sg[i];
1348 struct at_lli *lli;
1349 u32 len;
1350 u32 mem;
1351
1352 atdma_sg->lli = dma_pool_alloc(atdma->lli_pool,
1353 GFP_NOWAIT,
1354 &atdma_sg->lli_phys);
1355 if (!atdma_sg->lli)
1356 goto err_desc_get;
1357 lli = atdma_sg->lli;
1358
1359 mem = sg_dma_address(sg);
1360 len = sg_dma_len(sg);
1361 if (unlikely(!len)) {
1362 dev_dbg(chan2dev(chan),
1363 "prep_slave_sg: sg(%d) data length is zero\n", i);
1364 goto err;
1365 }
1366 mem_width = 2;
1367 if (unlikely(mem & 3 || len & 3))
1368 mem_width = 0;
1369
1370 lli->saddr = reg;
1371 lli->daddr = mem;
1372 lli->ctrla = ctrla |
1373 FIELD_PREP(ATC_DST_WIDTH, mem_width) |
1374 len >> reg_width;
1375 lli->ctrlb = ctrlb;
1376
1377 desc->sg[i].len = len;
1378 total_len += len;
1379
1380 atdma_lli_chain(desc, i);
1381 }
1382 break;
1383 default:
1384 return NULL;
1385 }
1386
1387 /* set end-of-link to the last link descriptor of list*/
1388 set_lli_eol(desc, i - 1);
1389
1390 desc->total_len = total_len;
1391
1392 return vchan_tx_prep(&atchan->vc, &desc->vd, flags);
1393
1394err_desc_get:
1395 dev_err(chan2dev(chan), "not enough descriptors available\n");
1396err:
1397 atdma_desc_free(&desc->vd);
1398 return NULL;
1399}
1400
1401/*
1402 * atc_dma_cyclic_check_values
1403 * Check for too big/unaligned periods and unaligned DMA buffer
1404 */
1405static int
1406atc_dma_cyclic_check_values(unsigned int reg_width, dma_addr_t buf_addr,
1407 size_t period_len)
1408{
1409 if (period_len > (ATC_BTSIZE_MAX << reg_width))
1410 goto err_out;
1411 if (unlikely(period_len & ((1 << reg_width) - 1)))
1412 goto err_out;
1413 if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1414 goto err_out;
1415
1416 return 0;
1417
1418err_out:
1419 return -EINVAL;
1420}
1421
1422/*
1423 * atc_dma_cyclic_fill_desc - Fill one period descriptor
1424 */
1425static int
1426atc_dma_cyclic_fill_desc(struct dma_chan *chan, struct at_desc *desc,
1427 unsigned int i, dma_addr_t buf_addr,
1428 unsigned int reg_width, size_t period_len,
1429 enum dma_transfer_direction direction)
1430{
1431 struct at_dma *atdma = to_at_dma(chan->device);
1432 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1433 struct dma_slave_config *sconfig = &atchan->dma_sconfig;
1434 struct atdma_sg *atdma_sg = &desc->sg[i];
1435 struct at_lli *lli;
1436
1437 atdma_sg->lli = dma_pool_alloc(atdma->lli_pool, GFP_ATOMIC,
1438 &atdma_sg->lli_phys);
1439 if (!atdma_sg->lli)
1440 return -ENOMEM;
1441 lli = atdma_sg->lli;
1442
1443 switch (direction) {
1444 case DMA_MEM_TO_DEV:
1445 lli->saddr = buf_addr + (period_len * i);
1446 lli->daddr = sconfig->dst_addr;
1447 lli->ctrlb = FIELD_PREP(ATC_DST_ADDR_MODE,
1448 ATC_DST_ADDR_MODE_FIXED) |
1449 FIELD_PREP(ATC_SRC_ADDR_MODE,
1450 ATC_SRC_ADDR_MODE_INCR) |
1451 FIELD_PREP(ATC_FC, ATC_FC_MEM2PER) |
1452 FIELD_PREP(ATC_SIF, atchan->mem_if) |
1453 FIELD_PREP(ATC_DIF, atchan->per_if);
1454
1455 break;
1456
1457 case DMA_DEV_TO_MEM:
1458 lli->saddr = sconfig->src_addr;
1459 lli->daddr = buf_addr + (period_len * i);
1460 lli->ctrlb = FIELD_PREP(ATC_DST_ADDR_MODE,
1461 ATC_DST_ADDR_MODE_INCR) |
1462 FIELD_PREP(ATC_SRC_ADDR_MODE,
1463 ATC_SRC_ADDR_MODE_FIXED) |
1464 FIELD_PREP(ATC_FC, ATC_FC_PER2MEM) |
1465 FIELD_PREP(ATC_SIF, atchan->per_if) |
1466 FIELD_PREP(ATC_DIF, atchan->mem_if);
1467 break;
1468
1469 default:
1470 return -EINVAL;
1471 }
1472
1473 lli->ctrla = FIELD_PREP(ATC_SCSIZE, sconfig->src_maxburst) |
1474 FIELD_PREP(ATC_DCSIZE, sconfig->dst_maxburst) |
1475 FIELD_PREP(ATC_DST_WIDTH, reg_width) |
1476 FIELD_PREP(ATC_SRC_WIDTH, reg_width) |
1477 period_len >> reg_width;
1478 desc->sg[i].len = period_len;
1479
1480 return 0;
1481}
1482
1483/**
1484 * atc_prep_dma_cyclic - prepare the cyclic DMA transfer
1485 * @chan: the DMA channel to prepare
1486 * @buf_addr: physical DMA address where the buffer starts
1487 * @buf_len: total number of bytes for the entire buffer
1488 * @period_len: number of bytes for each period
1489 * @direction: transfer direction, to or from device
1490 * @flags: tx descriptor status flags
1491 */
1492static struct dma_async_tx_descriptor *
1493atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
1494 size_t period_len, enum dma_transfer_direction direction,
1495 unsigned long flags)
1496{
1497 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1498 struct at_dma_slave *atslave = chan->private;
1499 struct dma_slave_config *sconfig = &atchan->dma_sconfig;
1500 struct at_desc *desc;
1501 unsigned long was_cyclic;
1502 unsigned int reg_width;
1503 unsigned int periods = buf_len / period_len;
1504 unsigned int i;
1505
1506 dev_vdbg(chan2dev(chan), "prep_dma_cyclic: %s buf@%pad - %d (%zu/%zu)\n",
1507 direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE",
1508 &buf_addr,
1509 periods, buf_len, period_len);
1510
1511 if (unlikely(!atslave || !buf_len || !period_len)) {
1512 dev_dbg(chan2dev(chan), "prep_dma_cyclic: length is zero!\n");
1513 return NULL;
1514 }
1515
1516 was_cyclic = test_and_set_bit(ATC_IS_CYCLIC, &atchan->status);
1517 if (was_cyclic) {
1518 dev_dbg(chan2dev(chan), "prep_dma_cyclic: channel in use!\n");
1519 return NULL;
1520 }
1521
1522 if (unlikely(!is_slave_direction(direction)))
1523 goto err_out;
1524
1525 if (direction == DMA_MEM_TO_DEV)
1526 reg_width = convert_buswidth(sconfig->dst_addr_width);
1527 else
1528 reg_width = convert_buswidth(sconfig->src_addr_width);
1529
1530 /* Check for too big/unaligned periods and unaligned DMA buffer */
1531 if (atc_dma_cyclic_check_values(reg_width, buf_addr, period_len))
1532 goto err_out;
1533
1534 desc = kzalloc_flex(*desc, sg, periods, GFP_ATOMIC);
1535 if (!desc)
1536 goto err_out;
1537 desc->sglen = periods;
1538
1539 /* build cyclic linked list */
1540 for (i = 0; i < periods; i++) {
1541 if (atc_dma_cyclic_fill_desc(chan, desc, i, buf_addr,
1542 reg_width, period_len, direction))
1543 goto err_fill_desc;
1544 atdma_lli_chain(desc, i);
1545 }
1546 desc->total_len = buf_len;
1547 /* lets make a cyclic list */
1548 desc->sg[i - 1].lli->dscr = desc->sg[0].lli_phys;
1549
1550 return vchan_tx_prep(&atchan->vc, &desc->vd, flags);
1551
1552err_fill_desc:
1553 atdma_desc_free(&desc->vd);
1554err_out:
1555 clear_bit(ATC_IS_CYCLIC, &atchan->status);
1556 return NULL;
1557}
1558
1559static int atc_config(struct dma_chan *chan,
1560 struct dma_slave_config *sconfig)
1561{
1562 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1563
1564 dev_vdbg(chan2dev(chan), "%s\n", __func__);
1565
1566 /* Check if it is chan is configured for slave transfers */
1567 if (!chan->private)
1568 return -EINVAL;
1569
1570 memcpy(&atchan->dma_sconfig, sconfig, sizeof(*sconfig));
1571
1572 convert_burst(&atchan->dma_sconfig.src_maxburst);
1573 convert_burst(&atchan->dma_sconfig.dst_maxburst);
1574
1575 return 0;
1576}
1577
1578static int atc_pause(struct dma_chan *chan)
1579{
1580 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1581 struct at_dma *atdma = to_at_dma(chan->device);
1582 int chan_id = atchan->vc.chan.chan_id;
1583 unsigned long flags;
1584
1585 dev_vdbg(chan2dev(chan), "%s\n", __func__);
1586
1587 spin_lock_irqsave(&atchan->vc.lock, flags);
1588
1589 dma_writel(atdma, CHER, AT_DMA_SUSP(chan_id));
1590 set_bit(ATC_IS_PAUSED, &atchan->status);
1591
1592 spin_unlock_irqrestore(&atchan->vc.lock, flags);
1593
1594 return 0;
1595}
1596
1597static int atc_resume(struct dma_chan *chan)
1598{
1599 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1600 struct at_dma *atdma = to_at_dma(chan->device);
1601 int chan_id = atchan->vc.chan.chan_id;
1602 unsigned long flags;
1603
1604 dev_vdbg(chan2dev(chan), "%s\n", __func__);
1605
1606 if (!atc_chan_is_paused(atchan))
1607 return 0;
1608
1609 spin_lock_irqsave(&atchan->vc.lock, flags);
1610
1611 dma_writel(atdma, CHDR, AT_DMA_RES(chan_id));
1612 clear_bit(ATC_IS_PAUSED, &atchan->status);
1613
1614 spin_unlock_irqrestore(&atchan->vc.lock, flags);
1615
1616 return 0;
1617}
1618
1619static int atc_terminate_all(struct dma_chan *chan)
1620{
1621 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1622 struct at_dma *atdma = to_at_dma(chan->device);
1623 int chan_id = atchan->vc.chan.chan_id;
1624 unsigned long flags;
1625
1626 LIST_HEAD(list);
1627
1628 dev_vdbg(chan2dev(chan), "%s\n", __func__);
1629
1630 /*
1631 * This is only called when something went wrong elsewhere, so
1632 * we don't really care about the data. Just disable the
1633 * channel. We still have to poll the channel enable bit due
1634 * to AHB/HSB limitations.
1635 */
1636 spin_lock_irqsave(&atchan->vc.lock, flags);
1637
1638 /* disabling channel: must also remove suspend state */
1639 dma_writel(atdma, CHDR, AT_DMA_RES(chan_id) | atchan->mask);
1640
1641 /* confirm that this channel is disabled */
1642 while (dma_readl(atdma, CHSR) & atchan->mask)
1643 cpu_relax();
1644
1645 if (atchan->desc) {
1646 vchan_terminate_vdesc(&atchan->desc->vd);
1647 atchan->desc = NULL;
1648 }
1649
1650 vchan_get_all_descriptors(&atchan->vc, &list);
1651
1652 clear_bit(ATC_IS_PAUSED, &atchan->status);
1653 /* if channel dedicated to cyclic operations, free it */
1654 clear_bit(ATC_IS_CYCLIC, &atchan->status);
1655
1656 spin_unlock_irqrestore(&atchan->vc.lock, flags);
1657
1658 vchan_dma_desc_free_list(&atchan->vc, &list);
1659
1660 return 0;
1661}
1662
1663/**
1664 * atc_tx_status - poll for transaction completion
1665 * @chan: DMA channel
1666 * @cookie: transaction identifier to check status of
1667 * @txstate: if not %NULL updated with transaction state
1668 *
1669 * If @txstate is passed in, upon return it reflect the driver
1670 * internal state and can be used with dma_async_is_complete() to check
1671 * the status of multiple cookies without re-checking hardware state.
1672 */
1673static enum dma_status
1674atc_tx_status(struct dma_chan *chan,
1675 dma_cookie_t cookie,
1676 struct dma_tx_state *txstate)
1677{
1678 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1679 unsigned long flags;
1680 enum dma_status dma_status;
1681 u32 residue;
1682 int ret;
1683
1684 dma_status = dma_cookie_status(chan, cookie, txstate);
1685 if (dma_status == DMA_COMPLETE || !txstate)
1686 return dma_status;
1687
1688 spin_lock_irqsave(&atchan->vc.lock, flags);
1689 /* Get number of bytes left in the active transactions */
1690 ret = atc_get_residue(chan, cookie, &residue);
1691 spin_unlock_irqrestore(&atchan->vc.lock, flags);
1692
1693 if (unlikely(ret < 0)) {
1694 dev_vdbg(chan2dev(chan), "get residual bytes error\n");
1695 return DMA_ERROR;
1696 } else {
1697 dma_set_residue(txstate, residue);
1698 }
1699
1700 dev_vdbg(chan2dev(chan), "tx_status %d: cookie = %d residue = %u\n",
1701 dma_status, cookie, residue);
1702
1703 return dma_status;
1704}
1705
1706static void atc_issue_pending(struct dma_chan *chan)
1707{
1708 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1709 unsigned long flags;
1710
1711 spin_lock_irqsave(&atchan->vc.lock, flags);
1712 if (vchan_issue_pending(&atchan->vc) && !atchan->desc) {
1713 if (!(atc_chan_is_enabled(atchan)))
1714 atc_dostart(atchan);
1715 }
1716 spin_unlock_irqrestore(&atchan->vc.lock, flags);
1717}
1718
1719/**
1720 * atc_alloc_chan_resources - allocate resources for DMA channel
1721 * @chan: allocate descriptor resources for this channel
1722 *
1723 * Return: the number of allocated descriptors
1724 */
1725static int atc_alloc_chan_resources(struct dma_chan *chan)
1726{
1727 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1728 struct at_dma *atdma = to_at_dma(chan->device);
1729 struct at_dma_slave *atslave;
1730 u32 cfg;
1731
1732 dev_vdbg(chan2dev(chan), "alloc_chan_resources\n");
1733
1734 /* ASSERT: channel is idle */
1735 if (atc_chan_is_enabled(atchan)) {
1736 dev_dbg(chan2dev(chan), "DMA channel not idle ?\n");
1737 return -EIO;
1738 }
1739
1740 cfg = ATC_DEFAULT_CFG;
1741
1742 atslave = chan->private;
1743 if (atslave) {
1744 /*
1745 * We need controller-specific data to set up slave
1746 * transfers.
1747 */
1748 BUG_ON(!atslave->dma_dev || atslave->dma_dev != atdma->dma_device.dev);
1749
1750 /* if cfg configuration specified take it instead of default */
1751 if (atslave->cfg)
1752 cfg = atslave->cfg;
1753 }
1754
1755 /* channel parameters */
1756 channel_writel(atchan, CFG, cfg);
1757
1758 return 0;
1759}
1760
1761/**
1762 * atc_free_chan_resources - free all channel resources
1763 * @chan: DMA channel
1764 */
1765static void atc_free_chan_resources(struct dma_chan *chan)
1766{
1767 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1768 struct at_dma_slave *atslave;
1769
1770 BUG_ON(atc_chan_is_enabled(atchan));
1771
1772 vchan_free_chan_resources(to_virt_chan(chan));
1773 atchan->status = 0;
1774
1775 /*
1776 * Free atslave allocated in at_dma_xlate()
1777 */
1778 atslave = chan->private;
1779 if (atslave) {
1780 put_device(atslave->dma_dev);
1781 kfree(atslave);
1782 chan->private = NULL;
1783 }
1784
1785 dev_vdbg(chan2dev(chan), "free_chan_resources: done\n");
1786}
1787
1788#ifdef CONFIG_OF
1789static bool at_dma_filter(struct dma_chan *chan, void *slave)
1790{
1791 struct at_dma_slave *atslave = slave;
1792
1793 if (atslave->dma_dev == chan->device->dev) {
1794 chan->private = atslave;
1795 return true;
1796 } else {
1797 return false;
1798 }
1799}
1800
1801static struct dma_chan *at_dma_xlate(struct of_phandle_args *dma_spec,
1802 struct of_dma *of_dma)
1803{
1804 struct dma_chan *chan;
1805 struct at_dma_chan *atchan;
1806 struct at_dma_slave *atslave;
1807 dma_cap_mask_t mask;
1808 unsigned int per_id;
1809 struct platform_device *dmac_pdev;
1810
1811 if (dma_spec->args_count != 2)
1812 return NULL;
1813
1814 dmac_pdev = of_find_device_by_node(dma_spec->np);
1815 if (!dmac_pdev)
1816 return NULL;
1817
1818 dma_cap_zero(mask);
1819 dma_cap_set(DMA_SLAVE, mask);
1820
1821 atslave = kmalloc_obj(*atslave);
1822 if (!atslave) {
1823 put_device(&dmac_pdev->dev);
1824 return NULL;
1825 }
1826
1827 atslave->cfg = ATC_DST_H2SEL | ATC_SRC_H2SEL;
1828 /*
1829 * We can fill both SRC_PER and DST_PER, one of these fields will be
1830 * ignored depending on DMA transfer direction.
1831 */
1832 per_id = dma_spec->args[1] & AT91_DMA_CFG_PER_ID_MASK;
1833 atslave->cfg |= ATC_DST_PER_ID(per_id) | ATC_SRC_PER_ID(per_id);
1834 /*
1835 * We have to translate the value we get from the device tree since
1836 * the half FIFO configuration value had to be 0 to keep backward
1837 * compatibility.
1838 */
1839 switch (dma_spec->args[1] & AT91_DMA_CFG_FIFOCFG_MASK) {
1840 case AT91_DMA_CFG_FIFOCFG_ALAP:
1841 atslave->cfg |= FIELD_PREP(ATC_FIFOCFG,
1842 ATC_FIFOCFG_LARGESTBURST);
1843 break;
1844 case AT91_DMA_CFG_FIFOCFG_ASAP:
1845 atslave->cfg |= FIELD_PREP(ATC_FIFOCFG,
1846 ATC_FIFOCFG_ENOUGHSPACE);
1847 break;
1848 case AT91_DMA_CFG_FIFOCFG_HALF:
1849 default:
1850 atslave->cfg |= FIELD_PREP(ATC_FIFOCFG, ATC_FIFOCFG_HALFFIFO);
1851 }
1852 atslave->dma_dev = &dmac_pdev->dev;
1853
1854 chan = dma_request_channel(mask, at_dma_filter, atslave);
1855 if (!chan) {
1856 put_device(&dmac_pdev->dev);
1857 kfree(atslave);
1858 return NULL;
1859 }
1860
1861 atchan = to_at_dma_chan(chan);
1862 atchan->per_if = dma_spec->args[0] & 0xff;
1863 atchan->mem_if = (dma_spec->args[0] >> 16) & 0xff;
1864
1865 return chan;
1866}
1867#else
1868static struct dma_chan *at_dma_xlate(struct of_phandle_args *dma_spec,
1869 struct of_dma *of_dma)
1870{
1871 return NULL;
1872}
1873#endif
1874
1875/*-- Module Management -----------------------------------------------*/
1876
1877/* cap_mask is a multi-u32 bitfield, fill it with proper C code. */
1878static struct at_dma_platform_data at91sam9rl_config = {
1879 .nr_channels = 2,
1880};
1881static struct at_dma_platform_data at91sam9g45_config = {
1882 .nr_channels = 8,
1883};
1884
1885#if defined(CONFIG_OF)
1886static const struct of_device_id atmel_dma_dt_ids[] = {
1887 {
1888 .compatible = "atmel,at91sam9rl-dma",
1889 .data = &at91sam9rl_config,
1890 }, {
1891 .compatible = "atmel,at91sam9g45-dma",
1892 .data = &at91sam9g45_config,
1893 }, {
1894 /* sentinel */
1895 }
1896};
1897
1898MODULE_DEVICE_TABLE(of, atmel_dma_dt_ids);
1899#endif
1900
1901static const struct platform_device_id atdma_devtypes[] = {
1902 {
1903 .name = "at91sam9rl_dma",
1904 .driver_data = (unsigned long) &at91sam9rl_config,
1905 }, {
1906 .name = "at91sam9g45_dma",
1907 .driver_data = (unsigned long) &at91sam9g45_config,
1908 }, {
1909 /* sentinel */
1910 }
1911};
1912
1913static inline const struct at_dma_platform_data * __init at_dma_get_driver_data(
1914 struct platform_device *pdev)
1915{
1916 if (pdev->dev.of_node) {
1917 const struct of_device_id *match;
1918 match = of_match_node(atmel_dma_dt_ids, pdev->dev.of_node);
1919 if (match == NULL)
1920 return NULL;
1921 return match->data;
1922 }
1923 return (struct at_dma_platform_data *)
1924 platform_get_device_id(pdev)->driver_data;
1925}
1926
1927/**
1928 * at_dma_off - disable DMA controller
1929 * @atdma: the Atmel HDAMC device
1930 */
1931static void at_dma_off(struct at_dma *atdma)
1932{
1933 dma_writel(atdma, EN, 0);
1934
1935 /* disable all interrupts */
1936 dma_writel(atdma, EBCIDR, -1L);
1937
1938 /* confirm that all channels are disabled */
1939 while (dma_readl(atdma, CHSR) & atdma->all_chan_mask)
1940 cpu_relax();
1941}
1942
1943static int __init at_dma_probe(struct platform_device *pdev)
1944{
1945 struct at_dma *atdma;
1946 int irq;
1947 int err;
1948 int i;
1949 const struct at_dma_platform_data *plat_dat;
1950
1951 /* setup platform data for each SoC */
1952 dma_cap_set(DMA_MEMCPY, at91sam9rl_config.cap_mask);
1953 dma_cap_set(DMA_INTERLEAVE, at91sam9g45_config.cap_mask);
1954 dma_cap_set(DMA_MEMCPY, at91sam9g45_config.cap_mask);
1955 dma_cap_set(DMA_MEMSET, at91sam9g45_config.cap_mask);
1956 dma_cap_set(DMA_MEMSET_SG, at91sam9g45_config.cap_mask);
1957 dma_cap_set(DMA_PRIVATE, at91sam9g45_config.cap_mask);
1958 dma_cap_set(DMA_SLAVE, at91sam9g45_config.cap_mask);
1959
1960 /* get DMA parameters from controller type */
1961 plat_dat = at_dma_get_driver_data(pdev);
1962 if (!plat_dat)
1963 return -ENODEV;
1964
1965 atdma = devm_kzalloc(&pdev->dev,
1966 struct_size(atdma, chan, plat_dat->nr_channels),
1967 GFP_KERNEL);
1968 if (!atdma)
1969 return -ENOMEM;
1970
1971 atdma->regs = devm_platform_ioremap_resource(pdev, 0);
1972 if (IS_ERR(atdma->regs))
1973 return PTR_ERR(atdma->regs);
1974
1975 irq = platform_get_irq(pdev, 0);
1976 if (irq < 0)
1977 return irq;
1978
1979 /* discover transaction capabilities */
1980 atdma->dma_device.cap_mask = plat_dat->cap_mask;
1981 atdma->all_chan_mask = (1 << plat_dat->nr_channels) - 1;
1982
1983 atdma->clk = devm_clk_get(&pdev->dev, "dma_clk");
1984 if (IS_ERR(atdma->clk))
1985 return PTR_ERR(atdma->clk);
1986
1987 err = clk_prepare_enable(atdma->clk);
1988 if (err)
1989 return err;
1990
1991 /* force dma off, just in case */
1992 at_dma_off(atdma);
1993
1994 err = request_irq(irq, at_dma_interrupt, 0, "at_hdmac", atdma);
1995 if (err)
1996 goto err_irq;
1997
1998 platform_set_drvdata(pdev, atdma);
1999
2000 /* create a pool of consistent memory blocks for hardware descriptors */
2001 atdma->lli_pool = dma_pool_create("at_hdmac_lli_pool",
2002 &pdev->dev, sizeof(struct at_lli),
2003 4 /* word alignment */, 0);
2004 if (!atdma->lli_pool) {
2005 dev_err(&pdev->dev, "Unable to allocate DMA LLI descriptor pool\n");
2006 err = -ENOMEM;
2007 goto err_desc_pool_create;
2008 }
2009
2010 /* create a pool of consistent memory blocks for memset blocks */
2011 atdma->memset_pool = dma_pool_create("at_hdmac_memset_pool",
2012 &pdev->dev, sizeof(int), 4, 0);
2013 if (!atdma->memset_pool) {
2014 dev_err(&pdev->dev, "No memory for memset dma pool\n");
2015 err = -ENOMEM;
2016 goto err_memset_pool_create;
2017 }
2018
2019 /* clear any pending interrupt */
2020 while (dma_readl(atdma, EBCISR))
2021 cpu_relax();
2022
2023 /* initialize channels related values */
2024 INIT_LIST_HEAD(&atdma->dma_device.channels);
2025 for (i = 0; i < plat_dat->nr_channels; i++) {
2026 struct at_dma_chan *atchan = &atdma->chan[i];
2027
2028 atchan->mem_if = AT_DMA_MEM_IF;
2029 atchan->per_if = AT_DMA_PER_IF;
2030
2031 atchan->ch_regs = atdma->regs + ch_regs(i);
2032 atchan->mask = 1 << i;
2033
2034 atchan->atdma = atdma;
2035 atchan->vc.desc_free = atdma_desc_free;
2036 vchan_init(&atchan->vc, &atdma->dma_device);
2037 atc_enable_chan_irq(atdma, i);
2038 }
2039
2040 /* set base routines */
2041 atdma->dma_device.device_alloc_chan_resources = atc_alloc_chan_resources;
2042 atdma->dma_device.device_free_chan_resources = atc_free_chan_resources;
2043 atdma->dma_device.device_tx_status = atc_tx_status;
2044 atdma->dma_device.device_issue_pending = atc_issue_pending;
2045 atdma->dma_device.dev = &pdev->dev;
2046
2047 /* set prep routines based on capability */
2048 if (dma_has_cap(DMA_INTERLEAVE, atdma->dma_device.cap_mask))
2049 atdma->dma_device.device_prep_interleaved_dma = atc_prep_dma_interleaved;
2050
2051 if (dma_has_cap(DMA_MEMCPY, atdma->dma_device.cap_mask))
2052 atdma->dma_device.device_prep_dma_memcpy = atc_prep_dma_memcpy;
2053
2054 if (dma_has_cap(DMA_MEMSET, atdma->dma_device.cap_mask)) {
2055 atdma->dma_device.device_prep_dma_memset = atc_prep_dma_memset;
2056 atdma->dma_device.device_prep_dma_memset_sg = atc_prep_dma_memset_sg;
2057 atdma->dma_device.fill_align = DMAENGINE_ALIGN_4_BYTES;
2058 }
2059
2060 if (dma_has_cap(DMA_SLAVE, atdma->dma_device.cap_mask)) {
2061 atdma->dma_device.device_prep_slave_sg = atc_prep_slave_sg;
2062 /* controller can do slave DMA: can trigger cyclic transfers */
2063 dma_cap_set(DMA_CYCLIC, atdma->dma_device.cap_mask);
2064 atdma->dma_device.device_prep_dma_cyclic = atc_prep_dma_cyclic;
2065 atdma->dma_device.device_config = atc_config;
2066 atdma->dma_device.device_pause = atc_pause;
2067 atdma->dma_device.device_resume = atc_resume;
2068 atdma->dma_device.device_terminate_all = atc_terminate_all;
2069 atdma->dma_device.src_addr_widths = ATC_DMA_BUSWIDTHS;
2070 atdma->dma_device.dst_addr_widths = ATC_DMA_BUSWIDTHS;
2071 atdma->dma_device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
2072 atdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
2073 }
2074
2075 dma_writel(atdma, EN, AT_DMA_ENABLE);
2076
2077 dev_info(&pdev->dev, "Atmel AHB DMA Controller ( %s%s%s), %d channels\n",
2078 dma_has_cap(DMA_MEMCPY, atdma->dma_device.cap_mask) ? "cpy " : "",
2079 dma_has_cap(DMA_MEMSET, atdma->dma_device.cap_mask) ? "set " : "",
2080 dma_has_cap(DMA_SLAVE, atdma->dma_device.cap_mask) ? "slave " : "",
2081 plat_dat->nr_channels);
2082
2083 err = dma_async_device_register(&atdma->dma_device);
2084 if (err) {
2085 dev_err(&pdev->dev, "Unable to register: %d.\n", err);
2086 goto err_dma_async_device_register;
2087 }
2088
2089 /*
2090 * Do not return an error if the dmac node is not present in order to
2091 * not break the existing way of requesting channel with
2092 * dma_request_channel().
2093 */
2094 if (pdev->dev.of_node) {
2095 err = of_dma_controller_register(pdev->dev.of_node,
2096 at_dma_xlate, atdma);
2097 if (err) {
2098 dev_err(&pdev->dev, "could not register of_dma_controller\n");
2099 goto err_of_dma_controller_register;
2100 }
2101 }
2102
2103 return 0;
2104
2105err_of_dma_controller_register:
2106 dma_async_device_unregister(&atdma->dma_device);
2107err_dma_async_device_register:
2108 dma_pool_destroy(atdma->memset_pool);
2109err_memset_pool_create:
2110 dma_pool_destroy(atdma->lli_pool);
2111err_desc_pool_create:
2112 free_irq(platform_get_irq(pdev, 0), atdma);
2113err_irq:
2114 clk_disable_unprepare(atdma->clk);
2115 return err;
2116}
2117
2118static void at_dma_remove(struct platform_device *pdev)
2119{
2120 struct at_dma *atdma = platform_get_drvdata(pdev);
2121 struct dma_chan *chan, *_chan;
2122
2123 at_dma_off(atdma);
2124 if (pdev->dev.of_node)
2125 of_dma_controller_free(pdev->dev.of_node);
2126 dma_async_device_unregister(&atdma->dma_device);
2127
2128 dma_pool_destroy(atdma->memset_pool);
2129 dma_pool_destroy(atdma->lli_pool);
2130 free_irq(platform_get_irq(pdev, 0), atdma);
2131
2132 list_for_each_entry_safe(chan, _chan, &atdma->dma_device.channels,
2133 device_node) {
2134 /* Disable interrupts */
2135 atc_disable_chan_irq(atdma, chan->chan_id);
2136 list_del(&chan->device_node);
2137 }
2138
2139 clk_disable_unprepare(atdma->clk);
2140}
2141
2142static void at_dma_shutdown(struct platform_device *pdev)
2143{
2144 struct at_dma *atdma = platform_get_drvdata(pdev);
2145
2146 at_dma_off(platform_get_drvdata(pdev));
2147 clk_disable_unprepare(atdma->clk);
2148}
2149
2150static int at_dma_prepare(struct device *dev)
2151{
2152 struct at_dma *atdma = dev_get_drvdata(dev);
2153 struct dma_chan *chan, *_chan;
2154
2155 list_for_each_entry_safe(chan, _chan, &atdma->dma_device.channels,
2156 device_node) {
2157 struct at_dma_chan *atchan = to_at_dma_chan(chan);
2158 /* wait for transaction completion (except in cyclic case) */
2159 if (atc_chan_is_enabled(atchan) && !atc_chan_is_cyclic(atchan))
2160 return -EAGAIN;
2161 }
2162 return 0;
2163}
2164
2165static void atc_suspend_cyclic(struct at_dma_chan *atchan)
2166{
2167 struct dma_chan *chan = &atchan->vc.chan;
2168
2169 /* Channel should be paused by user
2170 * do it anyway even if it is not done already */
2171 if (!atc_chan_is_paused(atchan)) {
2172 dev_warn(chan2dev(chan),
2173 "cyclic channel not paused, should be done by channel user\n");
2174 atc_pause(chan);
2175 }
2176
2177 /* now preserve additional data for cyclic operations */
2178 /* next descriptor address in the cyclic list */
2179 atchan->save_dscr = channel_readl(atchan, DSCR);
2180
2181 vdbg_dump_regs(atchan);
2182}
2183
2184static int at_dma_suspend_noirq(struct device *dev)
2185{
2186 struct at_dma *atdma = dev_get_drvdata(dev);
2187 struct dma_chan *chan, *_chan;
2188
2189 /* preserve data */
2190 list_for_each_entry_safe(chan, _chan, &atdma->dma_device.channels,
2191 device_node) {
2192 struct at_dma_chan *atchan = to_at_dma_chan(chan);
2193
2194 if (atc_chan_is_cyclic(atchan))
2195 atc_suspend_cyclic(atchan);
2196 atchan->save_cfg = channel_readl(atchan, CFG);
2197 }
2198 atdma->save_imr = dma_readl(atdma, EBCIMR);
2199
2200 /* disable DMA controller */
2201 at_dma_off(atdma);
2202 clk_disable_unprepare(atdma->clk);
2203 return 0;
2204}
2205
2206static void atc_resume_cyclic(struct at_dma_chan *atchan)
2207{
2208 struct at_dma *atdma = to_at_dma(atchan->vc.chan.device);
2209
2210 /* restore channel status for cyclic descriptors list:
2211 * next descriptor in the cyclic list at the time of suspend */
2212 channel_writel(atchan, SADDR, 0);
2213 channel_writel(atchan, DADDR, 0);
2214 channel_writel(atchan, CTRLA, 0);
2215 channel_writel(atchan, CTRLB, 0);
2216 channel_writel(atchan, DSCR, atchan->save_dscr);
2217 dma_writel(atdma, CHER, atchan->mask);
2218
2219 /* channel pause status should be removed by channel user
2220 * We cannot take the initiative to do it here */
2221
2222 vdbg_dump_regs(atchan);
2223}
2224
2225static int at_dma_resume_noirq(struct device *dev)
2226{
2227 struct at_dma *atdma = dev_get_drvdata(dev);
2228 struct dma_chan *chan, *_chan;
2229
2230 /* bring back DMA controller */
2231 clk_prepare_enable(atdma->clk);
2232 dma_writel(atdma, EN, AT_DMA_ENABLE);
2233
2234 /* clear any pending interrupt */
2235 while (dma_readl(atdma, EBCISR))
2236 cpu_relax();
2237
2238 /* restore saved data */
2239 dma_writel(atdma, EBCIER, atdma->save_imr);
2240 list_for_each_entry_safe(chan, _chan, &atdma->dma_device.channels,
2241 device_node) {
2242 struct at_dma_chan *atchan = to_at_dma_chan(chan);
2243
2244 channel_writel(atchan, CFG, atchan->save_cfg);
2245 if (atc_chan_is_cyclic(atchan))
2246 atc_resume_cyclic(atchan);
2247 }
2248 return 0;
2249}
2250
2251static const struct dev_pm_ops __maybe_unused at_dma_dev_pm_ops = {
2252 .prepare = at_dma_prepare,
2253 .suspend_noirq = at_dma_suspend_noirq,
2254 .resume_noirq = at_dma_resume_noirq,
2255};
2256
2257static struct platform_driver at_dma_driver = {
2258 .remove = at_dma_remove,
2259 .shutdown = at_dma_shutdown,
2260 .id_table = atdma_devtypes,
2261 .driver = {
2262 .name = "at_hdmac",
2263 .pm = pm_ptr(&at_dma_dev_pm_ops),
2264 .of_match_table = of_match_ptr(atmel_dma_dt_ids),
2265 },
2266};
2267
2268static int __init at_dma_init(void)
2269{
2270 return platform_driver_probe(&at_dma_driver, at_dma_probe);
2271}
2272subsys_initcall(at_dma_init);
2273
2274static void __exit at_dma_exit(void)
2275{
2276 platform_driver_unregister(&at_dma_driver);
2277}
2278module_exit(at_dma_exit);
2279
2280MODULE_DESCRIPTION("Atmel AHB DMA Controller driver");
2281MODULE_AUTHOR("Nicolas Ferre <[email protected]>");
2282MODULE_AUTHOR("Tudor Ambarus <[email protected]>");
2283MODULE_LICENSE("GPL");
2284MODULE_ALIAS("platform:at_hdmac");