linux - drivers/dma/pl330.c

3280 lines · 73.1 KiB

1	// SPDX-License-Identifier: GPL-2.0-or-later
2	/*
3	* Copyright (c) 2012 Samsung Electronics Co., Ltd.
4	* http://www.samsung.com
5	*
6	* Copyright (C) 2010 Samsung Electronics Co. Ltd.
7	* Jaswinder Singh <[email protected]>
8	*/
9
10	#include <linux/debugfs.h>
11	#include <linux/kernel.h>
12	#include <linux/io.h>
13	#include <linux/init.h>
14	#include <linux/slab.h>
15	#include <linux/module.h>
16	#include <linux/string.h>
17	#include <linux/delay.h>
18	#include <linux/interrupt.h>
19	#include <linux/dma-mapping.h>
20	#include <linux/dmaengine.h>
21	#include <linux/amba/bus.h>
22	#include <linux/scatterlist.h>
23	#include <linux/of.h>
24	#include <linux/of_dma.h>
25	#include <linux/err.h>
26	#include <linux/pm_runtime.h>
27	#include <linux/bug.h>
28	#include <linux/reset.h>
29
30	#include "dmaengine.h"
31	#define PL330_MAX_CHAN 8
32	#define PL330_MAX_IRQS 32
33	#define PL330_MAX_PERI 32
34	#define PL330_MAX_BURST 16
35
36	#define PL330_QUIRK_BROKEN_NO_FLUSHP BIT(0)
37	#define PL330_QUIRK_PERIPH_BURST BIT(1)
38
39	enum pl330_cachectrl {
40	CCTRL0, /* Noncacheable and nonbufferable */
41	CCTRL1, /* Bufferable only */
42	CCTRL2, /* Cacheable, but do not allocate */
43	CCTRL3, /* Cacheable and bufferable, but do not allocate */
44	INVALID1, /* AWCACHE = 0x1000 */
45	INVALID2,
46	CCTRL6, /* Cacheable write-through, allocate on writes only */
47	CCTRL7, /* Cacheable write-back, allocate on writes only */
48	};
49
50	enum pl330_byteswap {
51	SWAP_NO,
52	SWAP_2,
53	SWAP_4,
54	SWAP_8,
55	SWAP_16,
56	};
57
58	/* Register and Bit field Definitions */
59	#define DS 0x0
60	#define DS_ST_STOP 0x0
61	#define DS_ST_EXEC 0x1
62	#define DS_ST_CMISS 0x2
63	#define DS_ST_UPDTPC 0x3
64	#define DS_ST_WFE 0x4
65	#define DS_ST_ATBRR 0x5
66	#define DS_ST_QBUSY 0x6
67	#define DS_ST_WFP 0x7
68	#define DS_ST_KILL 0x8
69	#define DS_ST_CMPLT 0x9
70	#define DS_ST_FLTCMP 0xe
71	#define DS_ST_FAULT 0xf
72
73	#define DPC 0x4
74	#define INTEN 0x20
75	#define ES 0x24
76	#define INTSTATUS 0x28
77	#define INTCLR 0x2c
78	#define FSM 0x30
79	#define FSC 0x34
80	#define FTM 0x38
81
82	#define _FTC 0x40
83	#define FTC(n) (_FTC + (n)*0x4)
84
85	#define _CS 0x100
86	#define CS(n) (_CS + (n)*0x8)
87	#define CS_CNS (1 << 21)
88
89	#define _CPC 0x104
90	#define CPC(n) (_CPC + (n)*0x8)
91
92	#define _SA 0x400
93	#define SA(n) (_SA + (n)*0x20)
94
95	#define _DA 0x404
96	#define DA(n) (_DA + (n)*0x20)
97
98	#define _CC 0x408
99	#define CC(n) (_CC + (n)*0x20)
100
101	#define CC_SRCINC (1 << 0)
102	#define CC_DSTINC (1 << 14)
103	#define CC_SRCPRI (1 << 8)
104	#define CC_DSTPRI (1 << 22)
105	#define CC_SRCNS (1 << 9)
106	#define CC_DSTNS (1 << 23)
107	#define CC_SRCIA (1 << 10)
108	#define CC_DSTIA (1 << 24)
109	#define CC_SRCBRSTLEN_SHFT 4
110	#define CC_DSTBRSTLEN_SHFT 18
111	#define CC_SRCBRSTSIZE_SHFT 1
112	#define CC_DSTBRSTSIZE_SHFT 15
113	#define CC_SRCCCTRL_SHFT 11
114	#define CC_SRCCCTRL_MASK 0x7
115	#define CC_DSTCCTRL_SHFT 25
116	#define CC_DRCCCTRL_MASK 0x7
117	#define CC_SWAP_SHFT 28
118
119	#define _LC0 0x40c
120	#define LC0(n) (_LC0 + (n)*0x20)
121
122	#define _LC1 0x410
123	#define LC1(n) (_LC1 + (n)*0x20)
124
125	#define DBGSTATUS 0xd00
126	#define DBG_BUSY (1 << 0)
127
128	#define DBGCMD 0xd04
129	#define DBGINST0 0xd08
130	#define DBGINST1 0xd0c
131
132	#define CR0 0xe00
133	#define CR1 0xe04
134	#define CR2 0xe08
135	#define CR3 0xe0c
136	#define CR4 0xe10
137	#define CRD 0xe14
138
139	#define PERIPH_ID 0xfe0
140	#define PERIPH_REV_SHIFT 20
141	#define PERIPH_REV_MASK 0xf
142	#define PERIPH_REV_R0P0 0
143	#define PERIPH_REV_R1P0 1
144	#define PERIPH_REV_R1P1 2
145
146	#define CR0_PERIPH_REQ_SET (1 << 0)
147	#define CR0_BOOT_EN_SET (1 << 1)
148	#define CR0_BOOT_MAN_NS (1 << 2)
149	#define CR0_NUM_CHANS_SHIFT 4
150	#define CR0_NUM_CHANS_MASK 0x7
151	#define CR0_NUM_PERIPH_SHIFT 12
152	#define CR0_NUM_PERIPH_MASK 0x1f
153	#define CR0_NUM_EVENTS_SHIFT 17
154	#define CR0_NUM_EVENTS_MASK 0x1f
155
156	#define CR1_ICACHE_LEN_SHIFT 0
157	#define CR1_ICACHE_LEN_MASK 0x7
158	#define CR1_NUM_ICACHELINES_SHIFT 4
159	#define CR1_NUM_ICACHELINES_MASK 0xf
160
161	#define CRD_DATA_WIDTH_SHIFT 0
162	#define CRD_DATA_WIDTH_MASK 0x7
163	#define CRD_WR_CAP_SHIFT 4
164	#define CRD_WR_CAP_MASK 0x7
165	#define CRD_WR_Q_DEP_SHIFT 8
166	#define CRD_WR_Q_DEP_MASK 0xf
167	#define CRD_RD_CAP_SHIFT 12
168	#define CRD_RD_CAP_MASK 0x7
169	#define CRD_RD_Q_DEP_SHIFT 16
170	#define CRD_RD_Q_DEP_MASK 0xf
171	#define CRD_DATA_BUFF_SHIFT 20
172	#define CRD_DATA_BUFF_MASK 0x3ff
173
174	#define PART 0x330
175	#define DESIGNER 0x41
176	#define REVISION 0x0
177	#define INTEG_CFG 0x0
178	#define PERIPH_ID_VAL ((PART << 0) \| (DESIGNER << 12))
179
180	#define PL330_STATE_STOPPED (1 << 0)
181	#define PL330_STATE_EXECUTING (1 << 1)
182	#define PL330_STATE_WFE (1 << 2)
183	#define PL330_STATE_FAULTING (1 << 3)
184	#define PL330_STATE_COMPLETING (1 << 4)
185	#define PL330_STATE_WFP (1 << 5)
186	#define PL330_STATE_KILLING (1 << 6)
187	#define PL330_STATE_FAULT_COMPLETING (1 << 7)
188	#define PL330_STATE_CACHEMISS (1 << 8)
189	#define PL330_STATE_UPDTPC (1 << 9)
190	#define PL330_STATE_ATBARRIER (1 << 10)
191	#define PL330_STATE_QUEUEBUSY (1 << 11)
192	#define PL330_STATE_INVALID (1 << 15)
193
194	#define PL330_STABLE_STATES (PL330_STATE_STOPPED \| PL330_STATE_EXECUTING \
195	\| PL330_STATE_WFE \| PL330_STATE_FAULTING)
196
197	#define CMD_DMAADDH 0x54
198	#define CMD_DMAEND 0x00
199	#define CMD_DMAFLUSHP 0x35
200	#define CMD_DMAGO 0xa0
201	#define CMD_DMALD 0x04
202	#define CMD_DMALDP 0x25
203	#define CMD_DMALP 0x20
204	#define CMD_DMALPEND 0x28
205	#define CMD_DMAKILL 0x01
206	#define CMD_DMAMOV 0xbc
207	#define CMD_DMANOP 0x18
208	#define CMD_DMARMB 0x12
209	#define CMD_DMASEV 0x34
210	#define CMD_DMAST 0x08
211	#define CMD_DMASTP 0x29
212	#define CMD_DMASTZ 0x0c
213	#define CMD_DMAWFE 0x36
214	#define CMD_DMAWFP 0x30
215	#define CMD_DMAWMB 0x13
216
217	#define SZ_DMAADDH 3
218	#define SZ_DMAEND 1
219	#define SZ_DMAFLUSHP 2
220	#define SZ_DMALD 1
221	#define SZ_DMALDP 2
222	#define SZ_DMALP 2
223	#define SZ_DMALPEND 2
224	#define SZ_DMAKILL 1
225	#define SZ_DMAMOV 6
226	#define SZ_DMANOP 1
227	#define SZ_DMARMB 1
228	#define SZ_DMASEV 2
229	#define SZ_DMAST 1
230	#define SZ_DMASTP 2
231	#define SZ_DMASTZ 1
232	#define SZ_DMAWFE 2
233	#define SZ_DMAWFP 2
234	#define SZ_DMAWMB 1
235	#define SZ_DMAGO 6
236
237	#define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
238	#define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
239
240	#define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
241	#define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
242
243	/*
244	* With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
245	* at 1byte/burst for P<->M and M<->M respectively.
246	* For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
247	* should be enough for P<->M and M<->M respectively.
248	*/
249	#define MCODE_BUFF_PER_REQ 256
250
251	/* Use this _only_ to wait on transient states */
252	#define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
253
254	#ifdef PL330_DEBUG_MCGEN
255	static unsigned cmd_line;
256	#define PL330_DBGCMD_DUMP(off, x...) do { \
257	printk("%x:", cmd_line); \
258	printk(KERN_CONT x); \
259	cmd_line += off; \
260	} while (0)
261	#define PL330_DBGMC_START(addr) (cmd_line = addr)
262	#else
263	#define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
264	#define PL330_DBGMC_START(addr) do {} while (0)
265	#endif
266
267	/* The number of default descriptors */
268
269	#define NR_DEFAULT_DESC 16
270
271	/* Delay for runtime PM autosuspend, ms */
272	#define PL330_AUTOSUSPEND_DELAY 20
273
274	/* Populated by the PL330 core driver for DMA API driver's info */
275	struct pl330_config {
276	u32 periph_id;
277	#define DMAC_MODE_NS (1 << 0)
278	unsigned int mode;
279	unsigned int data_bus_width:10; /* In number of bits */
280	unsigned int data_buf_dep:11;
281	unsigned int num_chan:4;
282	unsigned int num_peri:6;
283	u32 peri_ns;
284	unsigned int num_events:6;
285	u32 irq_ns;
286	};
287
288	/*
289	* Request Configuration.
290	* The PL330 core does not modify this and uses the last
291	* working configuration if the request doesn't provide any.
292	*
293	* The Client may want to provide this info only for the
294	* first request and a request with new settings.
295	*/
296	struct pl330_reqcfg {
297	/* Address Incrementing */
298	unsigned dst_inc:1;
299	unsigned src_inc:1;
300
301	/*
302	* For now, the SRC & DST protection levels
303	* and burst size/length are assumed same.
304	*/
305	bool nonsecure;
306	bool privileged;
307	bool insnaccess;
308	unsigned brst_len:5;
309	unsigned brst_size:3; /* in power of 2 */
310
311	enum pl330_cachectrl dcctl;
312	enum pl330_cachectrl scctl;
313	enum pl330_byteswap swap;
314	struct pl330_config *pcfg;
315	};
316
317	/*
318	* One cycle of DMAC operation.
319	* There may be more than one xfer in a request.
320	*/
321	struct pl330_xfer {
322	u32 src_addr;
323	u32 dst_addr;
324	/* Size to xfer */
325	u32 bytes;
326	};
327
328	/* The xfer callbacks are made with one of these arguments. */
329	enum pl330_op_err {
330	/* The all xfers in the request were success. */
331	PL330_ERR_NONE,
332	/* If req aborted due to global error. */
333	PL330_ERR_ABORT,
334	/* If req failed due to problem with Channel. */
335	PL330_ERR_FAIL,
336	};
337
338	enum dmamov_dst {
339	SAR = 0,
340	CCR,
341	DAR,
342	};
343
344	enum pl330_dst {
345	SRC = 0,
346	DST,
347	};
348
349	enum pl330_cond {
350	SINGLE,
351	BURST,
352	ALWAYS,
353	};
354
355	struct dma_pl330_desc;
356
357	struct _pl330_req {
358	u32 mc_bus;
359	void *mc_cpu;
360	struct dma_pl330_desc *desc;
361	};
362
363	/* ToBeDone for tasklet */
364	struct _pl330_tbd {
365	bool reset_dmac;
366	bool reset_mngr;
367	u8 reset_chan;
368	};
369
370	/* A DMAC Thread */
371	struct pl330_thread {
372	u8 id;
373	int ev;
374	/* If the channel is not yet acquired by any client */
375	bool free;
376	/* Parent DMAC */
377	struct pl330_dmac *dmac;
378	/* Only two at a time */
379	struct _pl330_req req[2];
380	/* Index of the last enqueued request */
381	unsigned lstenq;
382	/* Index of the last submitted request or -1 if the DMA is stopped */
383	int req_running;
384	};
385
386	enum pl330_dmac_state {
387	UNINIT,
388	INIT,
389	DYING,
390	};
391
392	enum desc_status {
393	/* In the DMAC pool */
394	FREE,
395	/*
396	* Allocated to some channel during prep_xxx
397	* Also may be sitting on the work_list.
398	*/
399	PREP,
400	/*
401	* Sitting on the work_list and already submitted
402	* to the PL330 core. Not more than two descriptors
403	* of a channel can be BUSY at any time.
404	*/
405	BUSY,
406	/*
407	* Pause was called while descriptor was BUSY. Due to hardware
408	* limitations, only termination is possible for descriptors
409	* that have been paused.
410	*/
411	PAUSED,
412	/*
413	* Sitting on the channel work_list but xfer done
414	* by PL330 core
415	*/
416	DONE,
417	};
418
419	struct dma_pl330_chan {
420	/* Schedule desc completion */
421	struct tasklet_struct task;
422
423	/* DMA-Engine Channel */
424	struct dma_chan chan;
425
426	/* List of submitted descriptors */
427	struct list_head submitted_list;
428	/* List of issued descriptors */
429	struct list_head work_list;
430	/* List of completed descriptors */
431	struct list_head completed_list;
432
433	/* Pointer to the DMAC that manages this channel,
434	* NULL if the channel is available to be acquired.
435	* As the parent, this DMAC also provides descriptors
436	* to the channel.
437	*/
438	struct pl330_dmac *dmac;
439
440	/* To protect channel manipulation */
441	spinlock_t lock;
442
443	/*
444	* Hardware channel thread of PL330 DMAC. NULL if the channel is
445	* available.
446	*/
447	struct pl330_thread *thread;
448
449	/* For D-to-M and M-to-D channels */
450	int burst_sz; /* the peripheral fifo width */
451	int burst_len; /* the number of burst */
452	phys_addr_t fifo_addr;
453	/* DMA-mapped view of the FIFO; may differ if an IOMMU is present */
454	dma_addr_t fifo_dma;
455	enum dma_data_direction dir;
456	struct dma_slave_config slave_config;
457
458	/* for cyclic capability */
459	bool cyclic;
460
461	/* for runtime pm tracking */
462	bool active;
463	};
464
465	struct pl330_dmac {
466	/* DMA-Engine Device */
467	struct dma_device ddma;
468
469	/* Pool of descriptors available for the DMAC's channels */
470	struct list_head desc_pool;
471	/* To protect desc_pool manipulation */
472	spinlock_t pool_lock;
473
474	/* Size of MicroCode buffers for each channel. */
475	unsigned mcbufsz;
476	/* ioremap'ed address of PL330 registers. */
477	void __iomem *base;
478	/* Populated by the PL330 core driver during pl330_add */
479	struct pl330_config pcfg;
480
481	spinlock_t lock;
482	/* Maximum possible events/irqs */
483	int events[32];
484	/* BUS address of MicroCode buffer */
485	dma_addr_t mcode_bus;
486	/* CPU address of MicroCode buffer */
487	void *mcode_cpu;
488	/* List of all Channel threads */
489	struct pl330_thread *channels;
490	/* Pointer to the MANAGER thread */
491	struct pl330_thread *manager;
492	/* To handle bad news in interrupt */
493	struct tasklet_struct tasks;
494	struct _pl330_tbd dmac_tbd;
495	/* State of DMAC operation */
496	enum pl330_dmac_state state;
497	/* Holds list of reqs with due callbacks */
498	struct list_head req_done;
499
500	/* Peripheral channels connected to this DMAC */
501	unsigned int num_peripherals;
502	struct dma_pl330_chan peripherals; / keep at end */
503	int quirks;
504
505	struct dentry *dbgfs;
506	struct reset_control *rstc;
507	struct reset_control *rstc_ocp;
508	};
509
510	static struct pl330_of_quirks {
511	char *quirk;
512	int id;
513	} of_quirks[] = {
514	{
515	.quirk = "arm,pl330-broken-no-flushp",
516	.id = PL330_QUIRK_BROKEN_NO_FLUSHP,
517	},
518	{
519	.quirk = "arm,pl330-periph-burst",
520	.id = PL330_QUIRK_PERIPH_BURST,
521	}
522	};
523
524	struct dma_pl330_desc {
525	/* To attach to a queue as child */
526	struct list_head node;
527
528	/* Descriptor for the DMA Engine API */
529	struct dma_async_tx_descriptor txd;
530
531	/* Xfer for PL330 core */
532	struct pl330_xfer px;
533
534	struct pl330_reqcfg rqcfg;
535
536	enum desc_status status;
537
538	int bytes_requested;
539	bool last;
540
541	/* The channel which currently holds this desc */
542	struct dma_pl330_chan *pchan;
543
544	enum dma_transfer_direction rqtype;
545	/* Index of peripheral for the xfer. */
546	unsigned peri:5;
547	/* Hook to attach to DMAC's list of reqs with due callback */
548	struct list_head rqd;
549	};
550
551	struct _xfer_spec {
552	u32 ccr;
553	struct dma_pl330_desc *desc;
554	};
555
556	static int pl330_config_write(struct dma_chan *chan,
557	struct dma_slave_config *slave_config,
558	enum dma_transfer_direction direction);
559
560	static inline bool _queue_full(struct pl330_thread *thrd)
561	{
562	return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL;
563	}
564
565	static inline bool is_manager(struct pl330_thread *thrd)
566	{
567	return thrd->dmac->manager == thrd;
568	}
569
570	/* If manager of the thread is in Non-Secure mode */
571	static inline bool _manager_ns(struct pl330_thread *thrd)
572	{
573	return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false;
574	}
575
576	static inline u32 get_revision(u32 periph_id)
577	{
578	return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK;
579	}
580
581	static inline u32 _emit_END(unsigned dry_run, u8 buf[])
582	{
583	if (dry_run)
584	return SZ_DMAEND;
585
586	buf[0] = CMD_DMAEND;
587
588	PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n");
589
590	return SZ_DMAEND;
591	}
592
593	static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri)
594	{
595	if (dry_run)
596	return SZ_DMAFLUSHP;
597
598	buf[0] = CMD_DMAFLUSHP;
599
600	peri &= 0x1f;
601	peri <<= 3;
602	buf[1] = peri;
603
604	PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3);
605
606	return SZ_DMAFLUSHP;
607	}
608
609	static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond)
610	{
611	if (dry_run)
612	return SZ_DMALD;
613
614	buf[0] = CMD_DMALD;
615
616	if (cond == SINGLE)
617	buf[0] \|= (0 << 1) \| (1 << 0);
618	else if (cond == BURST)
619	buf[0] \|= (1 << 1) \| (1 << 0);
620
621	PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n",
622	cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
623
624	return SZ_DMALD;
625	}
626
627	static inline u32 _emit_LDP(unsigned dry_run, u8 buf[],
628	enum pl330_cond cond, u8 peri)
629	{
630	if (dry_run)
631	return SZ_DMALDP;
632
633	buf[0] = CMD_DMALDP;
634
635	if (cond == BURST)
636	buf[0] \|= (1 << 1);
637
638	peri &= 0x1f;
639	peri <<= 3;
640	buf[1] = peri;
641
642	PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n",
643	cond == SINGLE ? 'S' : 'B', peri >> 3);
644
645	return SZ_DMALDP;
646	}
647
648	static inline u32 _emit_LP(unsigned dry_run, u8 buf[],
649	unsigned loop, u8 cnt)
650	{
651	if (dry_run)
652	return SZ_DMALP;
653
654	buf[0] = CMD_DMALP;
655
656	if (loop)
657	buf[0] \|= (1 << 1);
658
659	cnt--; /* DMAC increments by 1 internally */
660	buf[1] = cnt;
661
662	PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt);
663
664	return SZ_DMALP;
665	}
666
667	struct _arg_LPEND {
668	enum pl330_cond cond;
669	bool forever;
670	unsigned loop;
671	u8 bjump;
672	};
673
674	static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[],
675	const struct _arg_LPEND *arg)
676	{
677	enum pl330_cond cond = arg->cond;
678	bool forever = arg->forever;
679	unsigned loop = arg->loop;
680	u8 bjump = arg->bjump;
681
682	if (dry_run)
683	return SZ_DMALPEND;
684
685	buf[0] = CMD_DMALPEND;
686
687	if (loop)
688	buf[0] \|= (1 << 2);
689
690	if (!forever)
691	buf[0] \|= (1 << 4);
692
693	if (cond == SINGLE)
694	buf[0] \|= (0 << 1) \| (1 << 0);
695	else if (cond == BURST)
696	buf[0] \|= (1 << 1) \| (1 << 0);
697
698	buf[1] = bjump;
699
700	PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n",
701	forever ? "FE" : "END",
702	cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'),
703	loop ? '1' : '0',
704	bjump);
705
706	return SZ_DMALPEND;
707	}
708
709	static inline u32 _emit_KILL(unsigned dry_run, u8 buf[])
710	{
711	if (dry_run)
712	return SZ_DMAKILL;
713
714	buf[0] = CMD_DMAKILL;
715
716	return SZ_DMAKILL;
717	}
718
719	static inline u32 _emit_MOV(unsigned dry_run, u8 buf[],
720	enum dmamov_dst dst, u32 val)
721	{
722	if (dry_run)
723	return SZ_DMAMOV;
724
725	buf[0] = CMD_DMAMOV;
726	buf[1] = dst;
727	buf[2] = val;
728	buf[3] = val >> 8;
729	buf[4] = val >> 16;
730	buf[5] = val >> 24;
731
732	PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n",
733	dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
734
735	return SZ_DMAMOV;
736	}
737
738	static inline u32 _emit_RMB(unsigned dry_run, u8 buf[])
739	{
740	if (dry_run)
741	return SZ_DMARMB;
742
743	buf[0] = CMD_DMARMB;
744
745	PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n");
746
747	return SZ_DMARMB;
748	}
749
750	static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev)
751	{
752	if (dry_run)
753	return SZ_DMASEV;
754
755	buf[0] = CMD_DMASEV;
756
757	ev &= 0x1f;
758	ev <<= 3;
759	buf[1] = ev;
760
761	PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3);
762
763	return SZ_DMASEV;
764	}
765
766	static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond)
767	{
768	if (dry_run)
769	return SZ_DMAST;
770
771	buf[0] = CMD_DMAST;
772
773	if (cond == SINGLE)
774	buf[0] \|= (0 << 1) \| (1 << 0);
775	else if (cond == BURST)
776	buf[0] \|= (1 << 1) \| (1 << 0);
777
778	PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n",
779	cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
780
781	return SZ_DMAST;
782	}
783
784	static inline u32 _emit_STP(unsigned dry_run, u8 buf[],
785	enum pl330_cond cond, u8 peri)
786	{
787	if (dry_run)
788	return SZ_DMASTP;
789
790	buf[0] = CMD_DMASTP;
791
792	if (cond == BURST)
793	buf[0] \|= (1 << 1);
794
795	peri &= 0x1f;
796	peri <<= 3;
797	buf[1] = peri;
798
799	PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n",
800	cond == SINGLE ? 'S' : 'B', peri >> 3);
801
802	return SZ_DMASTP;
803	}
804
805	static inline u32 _emit_WFP(unsigned dry_run, u8 buf[],
806	enum pl330_cond cond, u8 peri)
807	{
808	if (dry_run)
809	return SZ_DMAWFP;
810
811	buf[0] = CMD_DMAWFP;
812
813	if (cond == SINGLE)
814	buf[0] \|= (0 << 1) \| (0 << 0);
815	else if (cond == BURST)
816	buf[0] \|= (1 << 1) \| (0 << 0);
817	else
818	buf[0] \|= (0 << 1) \| (1 << 0);
819
820	peri &= 0x1f;
821	peri <<= 3;
822	buf[1] = peri;
823
824	PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n",
825	cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3);
826
827	return SZ_DMAWFP;
828	}
829
830	static inline u32 _emit_WMB(unsigned dry_run, u8 buf[])
831	{
832	if (dry_run)
833	return SZ_DMAWMB;
834
835	buf[0] = CMD_DMAWMB;
836
837	PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n");
838
839	return SZ_DMAWMB;
840	}
841
842	struct _arg_GO {
843	u8 chan;
844	u32 addr;
845	unsigned ns;
846	};
847
848	static inline u32 _emit_GO(unsigned dry_run, u8 buf[],
849	const struct _arg_GO *arg)
850	{
851	u8 chan = arg->chan;
852	u32 addr = arg->addr;
853	unsigned ns = arg->ns;
854
855	if (dry_run)
856	return SZ_DMAGO;
857
858	buf[0] = CMD_DMAGO;
859	buf[0] \|= (ns << 1);
860	buf[1] = chan & 0x7;
861	buf[2] = addr;
862	buf[3] = addr >> 8;
863	buf[4] = addr >> 16;
864	buf[5] = addr >> 24;
865
866	return SZ_DMAGO;
867	}
868
869	#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
870
871	/* Returns Time-Out */
872	static bool _until_dmac_idle(struct pl330_thread *thrd)
873	{
874	void __iomem *regs = thrd->dmac->base;
875	unsigned long loops = msecs_to_loops(5);
876
877	do {
878	/* Until Manager is Idle */
879	if (!(readl(regs + DBGSTATUS) & DBG_BUSY))
880	break;
881
882	cpu_relax();
883	} while (--loops);
884
885	if (!loops)
886	return true;
887
888	return false;
889	}
890
891	static inline void _execute_DBGINSN(struct pl330_thread *thrd,
892	u8 insn[], bool as_manager)
893	{
894	void __iomem *regs = thrd->dmac->base;
895	u32 val;
896
897	/* If timed out due to halted state-machine */
898	if (_until_dmac_idle(thrd)) {
899	dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n");
900	return;
901	}
902
903	val = (insn[0] << 16) \| (insn[1] << 24);
904	if (!as_manager) {
905	val \|= (1 << 0);
906	val \|= (thrd->id << 8); /* Channel Number */
907	}
908	writel(val, regs + DBGINST0);
909
910	val = le32_to_cpu(((__le32 )&insn[2]));
911	writel(val, regs + DBGINST1);
912
913	/* Get going */
914	writel(0, regs + DBGCMD);
915	}
916
917	static inline u32 _state(struct pl330_thread *thrd)
918	{
919	void __iomem *regs = thrd->dmac->base;
920	u32 val;
921
922	if (is_manager(thrd))
923	val = readl(regs + DS) & 0xf;
924	else
925	val = readl(regs + CS(thrd->id)) & 0xf;
926
927	switch (val) {
928	case DS_ST_STOP:
929	return PL330_STATE_STOPPED;
930	case DS_ST_EXEC:
931	return PL330_STATE_EXECUTING;
932	case DS_ST_CMISS:
933	return PL330_STATE_CACHEMISS;
934	case DS_ST_UPDTPC:
935	return PL330_STATE_UPDTPC;
936	case DS_ST_WFE:
937	return PL330_STATE_WFE;
938	case DS_ST_FAULT:
939	return PL330_STATE_FAULTING;
940	case DS_ST_ATBRR:
941	if (is_manager(thrd))
942	return PL330_STATE_INVALID;
943	else
944	return PL330_STATE_ATBARRIER;
945	case DS_ST_QBUSY:
946	if (is_manager(thrd))
947	return PL330_STATE_INVALID;
948	else
949	return PL330_STATE_QUEUEBUSY;
950	case DS_ST_WFP:
951	if (is_manager(thrd))
952	return PL330_STATE_INVALID;
953	else
954	return PL330_STATE_WFP;
955	case DS_ST_KILL:
956	if (is_manager(thrd))
957	return PL330_STATE_INVALID;
958	else
959	return PL330_STATE_KILLING;
960	case DS_ST_CMPLT:
961	if (is_manager(thrd))
962	return PL330_STATE_INVALID;
963	else
964	return PL330_STATE_COMPLETING;
965	case DS_ST_FLTCMP:
966	if (is_manager(thrd))
967	return PL330_STATE_INVALID;
968	else
969	return PL330_STATE_FAULT_COMPLETING;
970	default:
971	return PL330_STATE_INVALID;
972	}
973	}
974
975	static void _stop(struct pl330_thread *thrd)
976	{
977	void __iomem *regs = thrd->dmac->base;
978	u8 insn[6] = {0, 0, 0, 0, 0, 0};
979	u32 inten = readl(regs + INTEN);
980
981	if (_state(thrd) == PL330_STATE_FAULT_COMPLETING)
982	UNTIL(thrd, PL330_STATE_FAULTING \| PL330_STATE_KILLING);
983
984	/* Return if nothing needs to be done */
985	if (_state(thrd) == PL330_STATE_COMPLETING
986	\|\| _state(thrd) == PL330_STATE_KILLING
987	\|\| _state(thrd) == PL330_STATE_STOPPED)
988	return;
989
990	_emit_KILL(0, insn);
991
992	_execute_DBGINSN(thrd, insn, is_manager(thrd));
993
994	/* clear the event */
995	if (inten & (1 << thrd->ev))
996	writel(1 << thrd->ev, regs + INTCLR);
997	/* Stop generating interrupts for SEV */
998	writel(inten & ~(1 << thrd->ev), regs + INTEN);
999	}
1000
1001	/* Start doing req 'idx' of thread 'thrd' */
1002	static bool _trigger(struct pl330_thread *thrd)
1003	{
1004	void __iomem *regs = thrd->dmac->base;
1005	struct _pl330_req *req;
1006	struct dma_pl330_desc *desc;
1007	struct _arg_GO go;
1008	unsigned ns;
1009	u8 insn[6] = {0, 0, 0, 0, 0, 0};
1010	int idx;
1011
1012	/* Return if already ACTIVE */
1013	if (_state(thrd) != PL330_STATE_STOPPED)
1014	return true;
1015
1016	idx = 1 - thrd->lstenq;
1017	if (thrd->req[idx].desc != NULL) {
1018	req = &thrd->req[idx];
1019	} else {
1020	idx = thrd->lstenq;
1021	if (thrd->req[idx].desc != NULL)
1022	req = &thrd->req[idx];
1023	else
1024	req = NULL;
1025	}
1026
1027	/* Return if no request */
1028	if (!req)
1029	return true;
1030
1031	/* Return if req is running */
1032	if (idx == thrd->req_running)
1033	return true;
1034
1035	desc = req->desc;
1036
1037	ns = desc->rqcfg.nonsecure ? 1 : 0;
1038
1039	/* See 'Abort Sources' point-4 at Page 2-25 */
1040	if (_manager_ns(thrd) && !ns)
1041	dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n",
1042	__func__, __LINE__);
1043
1044	go.chan = thrd->id;
1045	go.addr = req->mc_bus;
1046	go.ns = ns;
1047	_emit_GO(0, insn, &go);
1048
1049	/* Set to generate interrupts for SEV */
1050	writel(readl(regs + INTEN) \| (1 << thrd->ev), regs + INTEN);
1051
1052	/* Only manager can execute GO */
1053	_execute_DBGINSN(thrd, insn, true);
1054
1055	thrd->req_running = idx;
1056
1057	return true;
1058	}
1059
1060	static bool pl330_start_thread(struct pl330_thread *thrd)
1061	{
1062	switch (_state(thrd)) {
1063	case PL330_STATE_FAULT_COMPLETING:
1064	UNTIL(thrd, PL330_STATE_FAULTING \| PL330_STATE_KILLING);
1065
1066	if (_state(thrd) == PL330_STATE_KILLING)
1067	UNTIL(thrd, PL330_STATE_STOPPED)
1068	fallthrough;
1069
1070	case PL330_STATE_FAULTING:
1071	_stop(thrd);
1072	fallthrough;
1073
1074	case PL330_STATE_KILLING:
1075	case PL330_STATE_COMPLETING:
1076	UNTIL(thrd, PL330_STATE_STOPPED)
1077	fallthrough;
1078
1079	case PL330_STATE_STOPPED:
1080	return _trigger(thrd);
1081
1082	case PL330_STATE_WFP:
1083	case PL330_STATE_QUEUEBUSY:
1084	case PL330_STATE_ATBARRIER:
1085	case PL330_STATE_UPDTPC:
1086	case PL330_STATE_CACHEMISS:
1087	case PL330_STATE_EXECUTING:
1088	return true;
1089
1090	case PL330_STATE_WFE: /* For RESUME, nothing yet */
1091	default:
1092	return false;
1093	}
1094	}
1095
1096	static inline int _ldst_memtomem(unsigned dry_run, u8 buf[],
1097	const struct _xfer_spec *pxs, int cyc)
1098	{
1099	int off = 0;
1100	struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg;
1101
1102	/* check lock-up free version */
1103	if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) {
1104	while (cyc--) {
1105	off += _emit_LD(dry_run, &buf[off], ALWAYS);
1106	off += _emit_ST(dry_run, &buf[off], ALWAYS);
1107	}
1108	} else {
1109	while (cyc--) {
1110	off += _emit_LD(dry_run, &buf[off], ALWAYS);
1111	off += _emit_RMB(dry_run, &buf[off]);
1112	off += _emit_ST(dry_run, &buf[off], ALWAYS);
1113	off += _emit_WMB(dry_run, &buf[off]);
1114	}
1115	}
1116
1117	return off;
1118	}
1119
1120	static u32 _emit_load(unsigned int dry_run, u8 buf[],
1121	enum pl330_cond cond, enum dma_transfer_direction direction,
1122	u8 peri)
1123	{
1124	int off = 0;
1125
1126	switch (direction) {
1127	case DMA_MEM_TO_MEM:
1128	case DMA_MEM_TO_DEV:
1129	off += _emit_LD(dry_run, &buf[off], cond);
1130	break;
1131
1132	case DMA_DEV_TO_MEM:
1133	if (cond == ALWAYS) {
1134	off += _emit_LDP(dry_run, &buf[off], SINGLE,
1135	peri);
1136	off += _emit_LDP(dry_run, &buf[off], BURST,
1137	peri);
1138	} else {
1139	off += _emit_LDP(dry_run, &buf[off], cond,
1140	peri);
1141	}
1142	break;
1143
1144	default:
1145	/* this code should be unreachable */
1146	WARN_ON(1);
1147	break;
1148	}
1149
1150	return off;
1151	}
1152
1153	static inline u32 _emit_store(unsigned int dry_run, u8 buf[],
1154	enum pl330_cond cond, enum dma_transfer_direction direction,
1155	u8 peri)
1156	{
1157	int off = 0;
1158
1159	switch (direction) {
1160	case DMA_MEM_TO_MEM:
1161	case DMA_DEV_TO_MEM:
1162	off += _emit_ST(dry_run, &buf[off], cond);
1163	break;
1164
1165	case DMA_MEM_TO_DEV:
1166	if (cond == ALWAYS) {
1167	off += _emit_STP(dry_run, &buf[off], SINGLE,
1168	peri);
1169	off += _emit_STP(dry_run, &buf[off], BURST,
1170	peri);
1171	} else {
1172	off += _emit_STP(dry_run, &buf[off], cond,
1173	peri);
1174	}
1175	break;
1176
1177	default:
1178	/* this code should be unreachable */
1179	WARN_ON(1);
1180	break;
1181	}
1182
1183	return off;
1184	}
1185
1186	static inline int _ldst_peripheral(struct pl330_dmac *pl330,
1187	unsigned dry_run, u8 buf[],
1188	const struct _xfer_spec *pxs, int cyc,
1189	enum pl330_cond cond)
1190	{
1191	int off = 0;
1192
1193	/*
1194	* do FLUSHP at beginning to clear any stale dma requests before the
1195	* first WFP.
1196	*/
1197	if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP))
1198	off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri);
1199	while (cyc--) {
1200	off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri);
1201	off += _emit_load(dry_run, &buf[off], cond, pxs->desc->rqtype,
1202	pxs->desc->peri);
1203	off += _emit_store(dry_run, &buf[off], cond, pxs->desc->rqtype,
1204	pxs->desc->peri);
1205	}
1206
1207	return off;
1208	}
1209
1210	static int _bursts(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
1211	const struct _xfer_spec *pxs, int cyc)
1212	{
1213	int off = 0;
1214	enum pl330_cond cond = BRST_LEN(pxs->ccr) > 1 ? BURST : SINGLE;
1215
1216	if (pl330->quirks & PL330_QUIRK_PERIPH_BURST)
1217	cond = BURST;
1218
1219	switch (pxs->desc->rqtype) {
1220	case DMA_MEM_TO_DEV:
1221	case DMA_DEV_TO_MEM:
1222	off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs, cyc,
1223	cond);
1224	break;
1225
1226	case DMA_MEM_TO_MEM:
1227	off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc);
1228	break;
1229
1230	default:
1231	/* this code should be unreachable */
1232	WARN_ON(1);
1233	break;
1234	}
1235
1236	return off;
1237	}
1238
1239	/*
1240	* only the unaligned burst transfers have the dregs.
1241	* so, still transfer dregs with a reduced size burst
1242	* for mem-to-mem, mem-to-dev or dev-to-mem.
1243	*/
1244	static int _dregs(struct pl330_dmac *pl330, unsigned int dry_run, u8 buf[],
1245	const struct _xfer_spec *pxs, int transfer_length)
1246	{
1247	int off = 0;
1248	int dregs_ccr;
1249
1250	if (transfer_length == 0)
1251	return off;
1252
1253	/*
1254	* dregs_len = (total bytes - BURST_TO_BYTE(bursts, ccr)) /
1255	* BRST_SIZE(ccr)
1256	* the dregs len must be smaller than burst len,
1257	* so, for higher efficiency, we can modify CCR
1258	* to use a reduced size burst len for the dregs.
1259	*/
1260	dregs_ccr = pxs->ccr;
1261	dregs_ccr &= ~((0xf << CC_SRCBRSTLEN_SHFT) \|
1262	(0xf << CC_DSTBRSTLEN_SHFT));
1263	dregs_ccr \|= (((transfer_length - 1) & 0xf) <<
1264	CC_SRCBRSTLEN_SHFT);
1265	dregs_ccr \|= (((transfer_length - 1) & 0xf) <<
1266	CC_DSTBRSTLEN_SHFT);
1267
1268	switch (pxs->desc->rqtype) {
1269	case DMA_MEM_TO_DEV:
1270	case DMA_DEV_TO_MEM:
1271	off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr);
1272	off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs, 1,
1273	BURST);
1274	break;
1275
1276	case DMA_MEM_TO_MEM:
1277	off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr);
1278	off += _ldst_memtomem(dry_run, &buf[off], pxs, 1);
1279	break;
1280
1281	default:
1282	/* this code should be unreachable */
1283	WARN_ON(1);
1284	break;
1285	}
1286
1287	return off;
1288	}
1289
1290	/* Returns bytes consumed and updates bursts */
1291	static inline int _loop(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
1292	unsigned long bursts, const struct _xfer_spec pxs)
1293	{
1294	int cyc, cycmax, szlp, szlpend, szbrst, off;
1295	unsigned lcnt0, lcnt1, ljmp0, ljmp1;
1296	struct _arg_LPEND lpend;
1297
1298	if (*bursts == 1)
1299	return _bursts(pl330, dry_run, buf, pxs, 1);
1300
1301	/* Max iterations possible in DMALP is 256 */
1302	if (bursts >= 256256) {
1303	lcnt1 = 256;
1304	lcnt0 = 256;
1305	cyc = *bursts / lcnt1 / lcnt0;
1306	} else if (*bursts > 256) {
1307	lcnt1 = 256;
1308	lcnt0 = *bursts / lcnt1;
1309	cyc = 1;
1310	} else {
1311	lcnt1 = *bursts;
1312	lcnt0 = 0;
1313	cyc = 1;
1314	}
1315
1316	szlp = _emit_LP(1, buf, 0, 0);
1317	szbrst = _bursts(pl330, 1, buf, pxs, 1);
1318
1319	lpend.cond = ALWAYS;
1320	lpend.forever = false;
1321	lpend.loop = 0;
1322	lpend.bjump = 0;
1323	szlpend = _emit_LPEND(1, buf, &lpend);
1324
1325	if (lcnt0) {
1326	szlp *= 2;
1327	szlpend *= 2;
1328	}
1329
1330	/*
1331	* Max bursts that we can unroll due to limit on the
1332	* size of backward jump that can be encoded in DMALPEND
1333	* which is 8-bits and hence 255
1334	*/
1335	cycmax = (255 - (szlp + szlpend)) / szbrst;
1336
1337	cyc = (cycmax < cyc) ? cycmax : cyc;
1338
1339	off = 0;
1340
1341	if (lcnt0) {
1342	off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
1343	ljmp0 = off;
1344	}
1345
1346	off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
1347	ljmp1 = off;
1348
1349	off += _bursts(pl330, dry_run, &buf[off], pxs, cyc);
1350
1351	lpend.cond = ALWAYS;
1352	lpend.forever = false;
1353	lpend.loop = 1;
1354	lpend.bjump = off - ljmp1;
1355	off += _emit_LPEND(dry_run, &buf[off], &lpend);
1356
1357	if (lcnt0) {
1358	lpend.cond = ALWAYS;
1359	lpend.forever = false;
1360	lpend.loop = 0;
1361	lpend.bjump = off - ljmp0;
1362	off += _emit_LPEND(dry_run, &buf[off], &lpend);
1363	}
1364
1365	bursts = lcnt1 cyc;
1366	if (lcnt0)
1367	bursts = lcnt0;
1368
1369	return off;
1370	}
1371
1372	static inline int _setup_loops(struct pl330_dmac *pl330,
1373	unsigned dry_run, u8 buf[],
1374	const struct _xfer_spec *pxs)
1375	{
1376	struct pl330_xfer *x = &pxs->desc->px;
1377	u32 ccr = pxs->ccr;
1378	unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr);
1379	int num_dregs = (x->bytes - BURST_TO_BYTE(bursts, ccr)) /
1380	BRST_SIZE(ccr);
1381	int off = 0;
1382
1383	while (bursts) {
1384	c = bursts;
1385	off += _loop(pl330, dry_run, &buf[off], &c, pxs);
1386	bursts -= c;
1387	}
1388	off += _dregs(pl330, dry_run, &buf[off], pxs, num_dregs);
1389
1390	return off;
1391	}
1392
1393	static inline int _setup_xfer(struct pl330_dmac *pl330,
1394	unsigned dry_run, u8 buf[],
1395	const struct _xfer_spec *pxs)
1396	{
1397	struct pl330_xfer *x = &pxs->desc->px;
1398	int off = 0;
1399
1400	/* DMAMOV SAR, x->src_addr */
1401	off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
1402	/* DMAMOV DAR, x->dst_addr */
1403	off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
1404
1405	/* Setup Loop(s) */
1406	off += _setup_loops(pl330, dry_run, &buf[off], pxs);
1407
1408	return off;
1409	}
1410
1411	/*
1412	* A req is a sequence of one or more xfer units.
1413	* Returns the number of bytes taken to setup the MC for the req.
1414	*/
1415	static int _setup_req(struct pl330_dmac *pl330, unsigned dry_run,
1416	struct pl330_thread *thrd, unsigned index,
1417	struct _xfer_spec *pxs)
1418	{
1419	struct _pl330_req *req = &thrd->req[index];
1420	u8 *buf = req->mc_cpu;
1421	int off = 0;
1422
1423	PL330_DBGMC_START(req->mc_bus);
1424
1425	/* DMAMOV CCR, ccr */
1426	off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
1427
1428	off += _setup_xfer(pl330, dry_run, &buf[off], pxs);
1429
1430	/* DMASEV peripheral/event */
1431	off += _emit_SEV(dry_run, &buf[off], thrd->ev);
1432	/* DMAEND */
1433	off += _emit_END(dry_run, &buf[off]);
1434
1435	return off;
1436	}
1437
1438	static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
1439	{
1440	u32 ccr = 0;
1441
1442	if (rqc->src_inc)
1443	ccr \|= CC_SRCINC;
1444
1445	if (rqc->dst_inc)
1446	ccr \|= CC_DSTINC;
1447
1448	/* We set same protection levels for Src and DST for now */
1449	if (rqc->privileged)
1450	ccr \|= CC_SRCPRI \| CC_DSTPRI;
1451	if (rqc->nonsecure)
1452	ccr \|= CC_SRCNS \| CC_DSTNS;
1453	if (rqc->insnaccess)
1454	ccr \|= CC_SRCIA \| CC_DSTIA;
1455
1456	ccr \|= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT);
1457	ccr \|= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT);
1458
1459	ccr \|= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
1460	ccr \|= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
1461
1462	ccr \|= (rqc->scctl << CC_SRCCCTRL_SHFT);
1463	ccr \|= (rqc->dcctl << CC_DSTCCTRL_SHFT);
1464
1465	ccr \|= (rqc->swap << CC_SWAP_SHFT);
1466
1467	return ccr;
1468	}
1469
1470	/*
1471	* Submit a list of xfers after which the client wants notification.
1472	* Client is not notified after each xfer unit, just once after all
1473	* xfer units are done or some error occurs.
1474	*/
1475	static int pl330_submit_req(struct pl330_thread *thrd,
1476	struct dma_pl330_desc *desc)
1477	{
1478	struct pl330_dmac *pl330 = thrd->dmac;
1479	struct _xfer_spec xs;
1480	unsigned long flags;
1481	unsigned idx;
1482	u32 ccr;
1483	int ret = 0;
1484
1485	switch (desc->rqtype) {
1486	case DMA_MEM_TO_DEV:
1487	break;
1488
1489	case DMA_DEV_TO_MEM:
1490	break;
1491
1492	case DMA_MEM_TO_MEM:
1493	break;
1494
1495	default:
1496	return -ENOTSUPP;
1497	}
1498
1499	if (pl330->state == DYING
1500	\|\| pl330->dmac_tbd.reset_chan & (1 << thrd->id)) {
1501	dev_info(thrd->dmac->ddma.dev, "%s:%d\n",
1502	__func__, __LINE__);
1503	return -EAGAIN;
1504	}
1505
1506	/* If request for non-existing peripheral */
1507	if (desc->rqtype != DMA_MEM_TO_MEM &&
1508	desc->peri >= pl330->pcfg.num_peri) {
1509	dev_info(thrd->dmac->ddma.dev,
1510	"%s:%d Invalid peripheral(%u)!\n",
1511	__func__, __LINE__, desc->peri);
1512	return -EINVAL;
1513	}
1514
1515	spin_lock_irqsave(&pl330->lock, flags);
1516
1517	if (_queue_full(thrd)) {
1518	ret = -EAGAIN;
1519	goto xfer_exit;
1520	}
1521
1522	/* Prefer Secure Channel */
1523	if (!_manager_ns(thrd))
1524	desc->rqcfg.nonsecure = 0;
1525	else
1526	desc->rqcfg.nonsecure = 1;
1527
1528	ccr = _prepare_ccr(&desc->rqcfg);
1529
1530	idx = thrd->req[0].desc == NULL ? 0 : 1;
1531
1532	xs.ccr = ccr;
1533	xs.desc = desc;
1534
1535	/* First dry run to check if req is acceptable */
1536	ret = _setup_req(pl330, 1, thrd, idx, &xs);
1537
1538	if (ret > pl330->mcbufsz / 2) {
1539	dev_info(pl330->ddma.dev, "%s:%d Try increasing mcbufsz (%i/%i)\n",
1540	__func__, __LINE__, ret, pl330->mcbufsz / 2);
1541	ret = -ENOMEM;
1542	goto xfer_exit;
1543	}
1544
1545	/* Hook the request */
1546	thrd->lstenq = idx;
1547	thrd->req[idx].desc = desc;
1548	_setup_req(pl330, 0, thrd, idx, &xs);
1549
1550	ret = 0;
1551
1552	xfer_exit:
1553	spin_unlock_irqrestore(&pl330->lock, flags);
1554
1555	return ret;
1556	}
1557
1558	static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err)
1559	{
1560	struct dma_pl330_chan *pch;
1561	unsigned long flags;
1562
1563	if (!desc)
1564	return;
1565
1566	pch = desc->pchan;
1567
1568	/* If desc aborted */
1569	if (!pch)
1570	return;
1571
1572	spin_lock_irqsave(&pch->lock, flags);
1573
1574	desc->status = DONE;
1575
1576	spin_unlock_irqrestore(&pch->lock, flags);
1577
1578	tasklet_schedule(&pch->task);
1579	}
1580
1581	static void pl330_dotask(struct tasklet_struct *t)
1582	{
1583	struct pl330_dmac *pl330 = from_tasklet(pl330, t, tasks);
1584	unsigned long flags;
1585	int i;
1586
1587	spin_lock_irqsave(&pl330->lock, flags);
1588
1589	/* The DMAC itself gone nuts */
1590	if (pl330->dmac_tbd.reset_dmac) {
1591	pl330->state = DYING;
1592	/* Reset the manager too */
1593	pl330->dmac_tbd.reset_mngr = true;
1594	/* Clear the reset flag */
1595	pl330->dmac_tbd.reset_dmac = false;
1596	}
1597
1598	if (pl330->dmac_tbd.reset_mngr) {
1599	_stop(pl330->manager);
1600	/* Reset all channels */
1601	pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1;
1602	/* Clear the reset flag */
1603	pl330->dmac_tbd.reset_mngr = false;
1604	}
1605
1606	for (i = 0; i < pl330->pcfg.num_chan; i++) {
1607
1608	if (pl330->dmac_tbd.reset_chan & (1 << i)) {
1609	struct pl330_thread *thrd = &pl330->channels[i];
1610	void __iomem *regs = pl330->base;
1611	enum pl330_op_err err;
1612
1613	_stop(thrd);
1614
1615	if (readl(regs + FSC) & (1 << thrd->id))
1616	err = PL330_ERR_FAIL;
1617	else
1618	err = PL330_ERR_ABORT;
1619
1620	spin_unlock_irqrestore(&pl330->lock, flags);
1621	dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err);
1622	dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err);
1623	spin_lock_irqsave(&pl330->lock, flags);
1624
1625	thrd->req[0].desc = NULL;
1626	thrd->req[1].desc = NULL;
1627	thrd->req_running = -1;
1628
1629	/* Clear the reset flag */
1630	pl330->dmac_tbd.reset_chan &= ~(1 << i);
1631	}
1632	}
1633
1634	spin_unlock_irqrestore(&pl330->lock, flags);
1635
1636	return;
1637	}
1638
1639	/* Returns 1 if state was updated, 0 otherwise */
1640	static int pl330_update(struct pl330_dmac *pl330)
1641	{
1642	struct dma_pl330_desc *descdone;
1643	unsigned long flags;
1644	void __iomem *regs;
1645	u32 val;
1646	int id, ev, ret = 0;
1647
1648	regs = pl330->base;
1649
1650	spin_lock_irqsave(&pl330->lock, flags);
1651
1652	val = readl(regs + FSM) & 0x1;
1653	if (val)
1654	pl330->dmac_tbd.reset_mngr = true;
1655	else
1656	pl330->dmac_tbd.reset_mngr = false;
1657
1658	val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1);
1659	pl330->dmac_tbd.reset_chan \|= val;
1660	if (val) {
1661	int i = 0;
1662	while (i < pl330->pcfg.num_chan) {
1663	if (val & (1 << i)) {
1664	dev_info(pl330->ddma.dev,
1665	"Reset Channel-%d\t CS-%x FTC-%x\n",
1666	i, readl(regs + CS(i)),
1667	readl(regs + FTC(i)));
1668	_stop(&pl330->channels[i]);
1669	}
1670	i++;
1671	}
1672	}
1673
1674	/* Check which event happened i.e, thread notified */
1675	val = readl(regs + ES);
1676	if (pl330->pcfg.num_events < 32
1677	&& val & ~((1 << pl330->pcfg.num_events) - 1)) {
1678	pl330->dmac_tbd.reset_dmac = true;
1679	dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__,
1680	__LINE__);
1681	ret = 1;
1682	goto updt_exit;
1683	}
1684
1685	for (ev = 0; ev < pl330->pcfg.num_events; ev++) {
1686	if (val & (1 << ev)) { /* Event occurred */
1687	struct pl330_thread *thrd;
1688	u32 inten = readl(regs + INTEN);
1689	int active;
1690
1691	/* Clear the event */
1692	if (inten & (1 << ev))
1693	writel(1 << ev, regs + INTCLR);
1694
1695	ret = 1;
1696
1697	id = pl330->events[ev];
1698
1699	thrd = &pl330->channels[id];
1700
1701	active = thrd->req_running;
1702	if (active == -1) /* Aborted */
1703	continue;
1704
1705	/* Detach the req */
1706	descdone = thrd->req[active].desc;
1707	thrd->req[active].desc = NULL;
1708
1709	thrd->req_running = -1;
1710
1711	/* Get going again ASAP */
1712	pl330_start_thread(thrd);
1713
1714	/* For now, just make a list of callbacks to be done */
1715	list_add_tail(&descdone->rqd, &pl330->req_done);
1716	}
1717	}
1718
1719	/* Now that we are in no hurry, do the callbacks */
1720	while (!list_empty(&pl330->req_done)) {
1721	descdone = list_first_entry(&pl330->req_done,
1722	struct dma_pl330_desc, rqd);
1723	list_del(&descdone->rqd);
1724	spin_unlock_irqrestore(&pl330->lock, flags);
1725	dma_pl330_rqcb(descdone, PL330_ERR_NONE);
1726	spin_lock_irqsave(&pl330->lock, flags);
1727	}
1728
1729	updt_exit:
1730	spin_unlock_irqrestore(&pl330->lock, flags);
1731
1732	if (pl330->dmac_tbd.reset_dmac
1733	\|\| pl330->dmac_tbd.reset_mngr
1734	\|\| pl330->dmac_tbd.reset_chan) {
1735	ret = 1;
1736	tasklet_schedule(&pl330->tasks);
1737	}
1738
1739	return ret;
1740	}
1741
1742	/* Reserve an event */
1743	static inline int _alloc_event(struct pl330_thread *thrd)
1744	{
1745	struct pl330_dmac *pl330 = thrd->dmac;
1746	int ev;
1747
1748	for (ev = 0; ev < pl330->pcfg.num_events; ev++)
1749	if (pl330->events[ev] == -1) {
1750	pl330->events[ev] = thrd->id;
1751	return ev;
1752	}
1753
1754	return -1;
1755	}
1756
1757	static bool _chan_ns(const struct pl330_dmac *pl330, int i)
1758	{
1759	return pl330->pcfg.irq_ns & (1 << i);
1760	}
1761
1762	/* Upon success, returns IdentityToken for the
1763	* allocated channel, NULL otherwise.
1764	*/
1765	static struct pl330_thread pl330_request_channel(struct pl330_dmac pl330)
1766	{
1767	struct pl330_thread *thrd = NULL;
1768	int chans, i;
1769
1770	if (pl330->state == DYING)
1771	return NULL;
1772
1773	chans = pl330->pcfg.num_chan;
1774
1775	for (i = 0; i < chans; i++) {
1776	thrd = &pl330->channels[i];
1777	if ((thrd->free) && (!_manager_ns(thrd) \|\|
1778	_chan_ns(pl330, i))) {
1779	thrd->ev = _alloc_event(thrd);
1780	if (thrd->ev >= 0) {
1781	thrd->free = false;
1782	thrd->lstenq = 1;
1783	thrd->req[0].desc = NULL;
1784	thrd->req[1].desc = NULL;
1785	thrd->req_running = -1;
1786	break;
1787	}
1788	}
1789	thrd = NULL;
1790	}
1791
1792	return thrd;
1793	}
1794
1795	/* Release an event */
1796	static inline void _free_event(struct pl330_thread *thrd, int ev)
1797	{
1798	struct pl330_dmac *pl330 = thrd->dmac;
1799
1800	/* If the event is valid and was held by the thread */
1801	if (ev >= 0 && ev < pl330->pcfg.num_events
1802	&& pl330->events[ev] == thrd->id)
1803	pl330->events[ev] = -1;
1804	}
1805
1806	static void pl330_release_channel(struct pl330_thread *thrd)
1807	{
1808	if (!thrd \|\| thrd->free)
1809	return;
1810
1811	_stop(thrd);
1812
1813	dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT);
1814	dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT);
1815
1816	_free_event(thrd, thrd->ev);
1817	thrd->free = true;
1818	}
1819
1820	/* Initialize the structure for PL330 configuration, that can be used
1821	* by the client driver the make best use of the DMAC
1822	*/
1823	static void read_dmac_config(struct pl330_dmac *pl330)
1824	{
1825	void __iomem *regs = pl330->base;
1826	u32 val;
1827
1828	val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT;
1829	val &= CRD_DATA_WIDTH_MASK;
1830	pl330->pcfg.data_bus_width = 8 * (1 << val);
1831
1832	val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT;
1833	val &= CRD_DATA_BUFF_MASK;
1834	pl330->pcfg.data_buf_dep = val + 1;
1835
1836	val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT;
1837	val &= CR0_NUM_CHANS_MASK;
1838	val += 1;
1839	pl330->pcfg.num_chan = val;
1840
1841	val = readl(regs + CR0);
1842	if (val & CR0_PERIPH_REQ_SET) {
1843	val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK;
1844	val += 1;
1845	pl330->pcfg.num_peri = val;
1846	pl330->pcfg.peri_ns = readl(regs + CR4);
1847	} else {
1848	pl330->pcfg.num_peri = 0;
1849	}
1850
1851	val = readl(regs + CR0);
1852	if (val & CR0_BOOT_MAN_NS)
1853	pl330->pcfg.mode \|= DMAC_MODE_NS;
1854	else
1855	pl330->pcfg.mode &= ~DMAC_MODE_NS;
1856
1857	val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT;
1858	val &= CR0_NUM_EVENTS_MASK;
1859	val += 1;
1860	pl330->pcfg.num_events = val;
1861
1862	pl330->pcfg.irq_ns = readl(regs + CR3);
1863	}
1864
1865	static inline void _reset_thread(struct pl330_thread *thrd)
1866	{
1867	struct pl330_dmac *pl330 = thrd->dmac;
1868
1869	thrd->req[0].mc_cpu = pl330->mcode_cpu
1870	+ (thrd->id * pl330->mcbufsz);
1871	thrd->req[0].mc_bus = pl330->mcode_bus
1872	+ (thrd->id * pl330->mcbufsz);
1873	thrd->req[0].desc = NULL;
1874
1875	thrd->req[1].mc_cpu = thrd->req[0].mc_cpu
1876	+ pl330->mcbufsz / 2;
1877	thrd->req[1].mc_bus = thrd->req[0].mc_bus
1878	+ pl330->mcbufsz / 2;
1879	thrd->req[1].desc = NULL;
1880
1881	thrd->req_running = -1;
1882	}
1883
1884	static int dmac_alloc_threads(struct pl330_dmac *pl330)
1885	{
1886	int chans = pl330->pcfg.num_chan;
1887	struct pl330_thread *thrd;
1888	int i;
1889
1890	/* Allocate 1 Manager and 'chans' Channel threads */
1891	pl330->channels = kzalloc_objs(*thrd, 1 + chans);
1892	if (!pl330->channels)
1893	return -ENOMEM;
1894
1895	/* Init Channel threads */
1896	for (i = 0; i < chans; i++) {
1897	thrd = &pl330->channels[i];
1898	thrd->id = i;
1899	thrd->dmac = pl330;
1900	_reset_thread(thrd);
1901	thrd->free = true;
1902	}
1903
1904	/* MANAGER is indexed at the end */
1905	thrd = &pl330->channels[chans];
1906	thrd->id = chans;
1907	thrd->dmac = pl330;
1908	thrd->free = false;
1909	pl330->manager = thrd;
1910
1911	return 0;
1912	}
1913
1914	static int dmac_alloc_resources(struct pl330_dmac *pl330)
1915	{
1916	int chans = pl330->pcfg.num_chan;
1917	int ret;
1918
1919	/*
1920	* Alloc MicroCode buffer for 'chans' Channel threads.
1921	* A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
1922	*/
1923	pl330->mcode_cpu = dma_alloc_attrs(pl330->ddma.dev,
1924	chans * pl330->mcbufsz,
1925	&pl330->mcode_bus, GFP_KERNEL,
1926	DMA_ATTR_PRIVILEGED);
1927	if (!pl330->mcode_cpu) {
1928	dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n",
1929	__func__, __LINE__);
1930	return -ENOMEM;
1931	}
1932
1933	ret = dmac_alloc_threads(pl330);
1934	if (ret) {
1935	dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n",
1936	__func__, __LINE__);
1937	dma_free_attrs(pl330->ddma.dev,
1938	chans * pl330->mcbufsz,
1939	pl330->mcode_cpu, pl330->mcode_bus,
1940	DMA_ATTR_PRIVILEGED);
1941	return ret;
1942	}
1943
1944	return 0;
1945	}
1946
1947	static int pl330_add(struct pl330_dmac *pl330)
1948	{
1949	int i, ret;
1950
1951	/* Check if we can handle this DMAC */
1952	if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) {
1953	dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n",
1954	pl330->pcfg.periph_id);
1955	return -EINVAL;
1956	}
1957
1958	/* Read the configuration of the DMAC */
1959	read_dmac_config(pl330);
1960
1961	if (pl330->pcfg.num_events == 0) {
1962	dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n",
1963	__func__, __LINE__);
1964	return -EINVAL;
1965	}
1966
1967	spin_lock_init(&pl330->lock);
1968
1969	INIT_LIST_HEAD(&pl330->req_done);
1970
1971	/* Use default MC buffer size if not provided */
1972	if (!pl330->mcbufsz)
1973	pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2;
1974
1975	/* Mark all events as free */
1976	for (i = 0; i < pl330->pcfg.num_events; i++)
1977	pl330->events[i] = -1;
1978
1979	/* Allocate resources needed by the DMAC */
1980	ret = dmac_alloc_resources(pl330);
1981	if (ret) {
1982	dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n");
1983	return ret;
1984	}
1985
1986	tasklet_setup(&pl330->tasks, pl330_dotask);
1987
1988	pl330->state = INIT;
1989
1990	return 0;
1991	}
1992
1993	static int dmac_free_threads(struct pl330_dmac *pl330)
1994	{
1995	struct pl330_thread *thrd;
1996	int i;
1997
1998	/* Release Channel threads */
1999	for (i = 0; i < pl330->pcfg.num_chan; i++) {
2000	thrd = &pl330->channels[i];
2001	pl330_release_channel(thrd);
2002	}
2003
2004	/* Free memory */
2005	kfree(pl330->channels);
2006
2007	return 0;
2008	}
2009
2010	static void pl330_del(struct pl330_dmac *pl330)
2011	{
2012	pl330->state = UNINIT;
2013
2014	tasklet_kill(&pl330->tasks);
2015
2016	/* Free DMAC resources */
2017	dmac_free_threads(pl330);
2018
2019	dma_free_attrs(pl330->ddma.dev,
2020	pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu,
2021	pl330->mcode_bus, DMA_ATTR_PRIVILEGED);
2022	}
2023
2024	/* forward declaration */
2025	static struct amba_driver pl330_driver;
2026
2027	static inline struct dma_pl330_chan *
2028	to_pchan(struct dma_chan *ch)
2029	{
2030	if (!ch)
2031	return NULL;
2032
2033	return container_of(ch, struct dma_pl330_chan, chan);
2034	}
2035
2036	static inline struct dma_pl330_desc *
2037	to_desc(struct dma_async_tx_descriptor *tx)
2038	{
2039	return container_of(tx, struct dma_pl330_desc, txd);
2040	}
2041
2042	static inline void fill_queue(struct dma_pl330_chan *pch)
2043	{
2044	struct dma_pl330_desc *desc;
2045	int ret;
2046
2047	list_for_each_entry(desc, &pch->work_list, node) {
2048
2049	/* If already submitted */
2050	if (desc->status == BUSY \|\| desc->status == PAUSED)
2051	continue;
2052
2053	ret = pl330_submit_req(pch->thread, desc);
2054	if (!ret) {
2055	desc->status = BUSY;
2056	} else if (ret == -EAGAIN) {
2057	/* QFull or DMAC Dying */
2058	break;
2059	} else {
2060	/* Unacceptable request */
2061	desc->status = DONE;
2062	dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n",
2063	__func__, __LINE__, desc->txd.cookie);
2064	tasklet_schedule(&pch->task);
2065	}
2066	}
2067	}
2068
2069	static void pl330_tasklet(struct tasklet_struct *t)
2070	{
2071	struct dma_pl330_chan *pch = from_tasklet(pch, t, task);
2072	struct dma_pl330_desc desc, _dt;
2073	unsigned long flags;
2074	bool power_down = false;
2075
2076	spin_lock_irqsave(&pch->lock, flags);
2077
2078	/* Pick up ripe tomatoes */
2079	list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
2080	if (desc->status == DONE) {
2081	if (!pch->cyclic)
2082	dma_cookie_complete(&desc->txd);
2083	list_move_tail(&desc->node, &pch->completed_list);
2084	}
2085
2086	/* Try to submit a req imm. next to the last completed cookie */
2087	fill_queue(pch);
2088
2089	if (list_empty(&pch->work_list)) {
2090	spin_lock(&pch->thread->dmac->lock);
2091	_stop(pch->thread);
2092	spin_unlock(&pch->thread->dmac->lock);
2093	power_down = true;
2094	pch->active = false;
2095	} else {
2096	/* Make sure the PL330 Channel thread is active */
2097	spin_lock(&pch->thread->dmac->lock);
2098	pl330_start_thread(pch->thread);
2099	spin_unlock(&pch->thread->dmac->lock);
2100	}
2101
2102	while (!list_empty(&pch->completed_list)) {
2103	struct dmaengine_desc_callback cb;
2104
2105	desc = list_first_entry(&pch->completed_list,
2106	struct dma_pl330_desc, node);
2107
2108	dmaengine_desc_get_callback(&desc->txd, &cb);
2109
2110	if (pch->cyclic) {
2111	desc->status = PREP;
2112	list_move_tail(&desc->node, &pch->work_list);
2113	if (power_down) {
2114	pch->active = true;
2115	spin_lock(&pch->thread->dmac->lock);
2116	pl330_start_thread(pch->thread);
2117	spin_unlock(&pch->thread->dmac->lock);
2118	power_down = false;
2119	}
2120	} else {
2121	desc->status = FREE;
2122	list_move_tail(&desc->node, &pch->dmac->desc_pool);
2123	}
2124
2125	dma_descriptor_unmap(&desc->txd);
2126
2127	if (dmaengine_desc_callback_valid(&cb)) {
2128	spin_unlock_irqrestore(&pch->lock, flags);
2129	dmaengine_desc_callback_invoke(&cb, NULL);
2130	spin_lock_irqsave(&pch->lock, flags);
2131	}
2132	}
2133	spin_unlock_irqrestore(&pch->lock, flags);
2134
2135	/* If work list empty, power down */
2136	if (power_down)
2137	pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2138	}
2139
2140	static struct dma_chan of_dma_pl330_xlate(struct of_phandle_args dma_spec,
2141	struct of_dma *ofdma)
2142	{
2143	int count = dma_spec->args_count;
2144	struct pl330_dmac *pl330 = ofdma->of_dma_data;
2145	unsigned int chan_id;
2146
2147	if (!pl330)
2148	return NULL;
2149
2150	if (count != 1)
2151	return NULL;
2152
2153	chan_id = dma_spec->args[0];
2154	if (chan_id >= pl330->num_peripherals)
2155	return NULL;
2156
2157	return dma_get_slave_channel(&pl330->peripherals[chan_id].chan);
2158	}
2159
2160	static int pl330_alloc_chan_resources(struct dma_chan *chan)
2161	{
2162	struct dma_pl330_chan *pch = to_pchan(chan);
2163	struct pl330_dmac *pl330 = pch->dmac;
2164	unsigned long flags;
2165
2166	spin_lock_irqsave(&pl330->lock, flags);
2167
2168	dma_cookie_init(chan);
2169	pch->cyclic = false;
2170
2171	pch->thread = pl330_request_channel(pl330);
2172	if (!pch->thread) {
2173	spin_unlock_irqrestore(&pl330->lock, flags);
2174	return -ENOMEM;
2175	}
2176
2177	tasklet_setup(&pch->task, pl330_tasklet);
2178
2179	spin_unlock_irqrestore(&pl330->lock, flags);
2180
2181	return 1;
2182	}
2183
2184	/*
2185	* We need the data direction between the DMAC (the dma-mapping "device") and
2186	* the FIFO (the dmaengine "dev"), from the FIFO's point of view. Confusing!
2187	*/
2188	static enum dma_data_direction
2189	pl330_dma_slave_map_dir(enum dma_transfer_direction dir)
2190	{
2191	switch (dir) {
2192	case DMA_MEM_TO_DEV:
2193	return DMA_FROM_DEVICE;
2194	case DMA_DEV_TO_MEM:
2195	return DMA_TO_DEVICE;
2196	case DMA_DEV_TO_DEV:
2197	return DMA_BIDIRECTIONAL;
2198	default:
2199	return DMA_NONE;
2200	}
2201	}
2202
2203	static void pl330_unprep_slave_fifo(struct dma_pl330_chan *pch)
2204	{
2205	if (pch->dir != DMA_NONE)
2206	dma_unmap_resource(pch->chan.device->dev, pch->fifo_dma,
2207	1 << pch->burst_sz, pch->dir, 0);
2208	pch->dir = DMA_NONE;
2209	}
2210
2211
2212	static bool pl330_prep_slave_fifo(struct dma_pl330_chan *pch,
2213	enum dma_transfer_direction dir)
2214	{
2215	struct device *dev = pch->chan.device->dev;
2216	enum dma_data_direction dma_dir = pl330_dma_slave_map_dir(dir);
2217
2218	/* Already mapped for this config? */
2219	if (pch->dir == dma_dir)
2220	return true;
2221
2222	pl330_unprep_slave_fifo(pch);
2223	pch->fifo_dma = dma_map_resource(dev, pch->fifo_addr,
2224	1 << pch->burst_sz, dma_dir, 0);
2225	if (dma_mapping_error(dev, pch->fifo_dma))
2226	return false;
2227
2228	pch->dir = dma_dir;
2229	return true;
2230	}
2231
2232	static int fixup_burst_len(int max_burst_len, int quirks)
2233	{
2234	if (max_burst_len > PL330_MAX_BURST)
2235	return PL330_MAX_BURST;
2236	else if (max_burst_len < 1)
2237	return 1;
2238	else
2239	return max_burst_len;
2240	}
2241
2242	static int pl330_config_write(struct dma_chan *chan,
2243	struct dma_slave_config *slave_config,
2244	enum dma_transfer_direction direction)
2245	{
2246	struct dma_pl330_chan *pch = to_pchan(chan);
2247
2248	pl330_unprep_slave_fifo(pch);
2249	if (direction == DMA_MEM_TO_DEV) {
2250	if (slave_config->dst_addr)
2251	pch->fifo_addr = slave_config->dst_addr;
2252	if (slave_config->dst_addr_width)
2253	pch->burst_sz = __ffs(slave_config->dst_addr_width);
2254	pch->burst_len = fixup_burst_len(slave_config->dst_maxburst,
2255	pch->dmac->quirks);
2256	} else if (direction == DMA_DEV_TO_MEM) {
2257	if (slave_config->src_addr)
2258	pch->fifo_addr = slave_config->src_addr;
2259	if (slave_config->src_addr_width)
2260	pch->burst_sz = __ffs(slave_config->src_addr_width);
2261	pch->burst_len = fixup_burst_len(slave_config->src_maxburst,
2262	pch->dmac->quirks);
2263	}
2264
2265	return 0;
2266	}
2267
2268	static int pl330_config(struct dma_chan *chan,
2269	struct dma_slave_config *slave_config)
2270	{
2271	struct dma_pl330_chan *pch = to_pchan(chan);
2272
2273	memcpy(&pch->slave_config, slave_config, sizeof(*slave_config));
2274
2275	return 0;
2276	}
2277
2278	static int pl330_terminate_all(struct dma_chan *chan)
2279	{
2280	struct dma_pl330_chan *pch = to_pchan(chan);
2281	struct dma_pl330_desc *desc;
2282	unsigned long flags;
2283	struct pl330_dmac *pl330 = pch->dmac;
2284	bool power_down = false;
2285
2286	pm_runtime_get_sync(pl330->ddma.dev);
2287	spin_lock_irqsave(&pch->lock, flags);
2288
2289	spin_lock(&pl330->lock);
2290	_stop(pch->thread);
2291	pch->thread->req[0].desc = NULL;
2292	pch->thread->req[1].desc = NULL;
2293	pch->thread->req_running = -1;
2294	spin_unlock(&pl330->lock);
2295
2296	power_down = pch->active;
2297	pch->active = false;
2298
2299	/* Mark all desc done */
2300	list_for_each_entry(desc, &pch->submitted_list, node) {
2301	desc->status = FREE;
2302	dma_cookie_complete(&desc->txd);
2303	}
2304
2305	list_for_each_entry(desc, &pch->work_list , node) {
2306	desc->status = FREE;
2307	dma_cookie_complete(&desc->txd);
2308	}
2309
2310	list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool);
2311	list_splice_tail_init(&pch->work_list, &pl330->desc_pool);
2312	list_splice_tail_init(&pch->completed_list, &pl330->desc_pool);
2313	spin_unlock_irqrestore(&pch->lock, flags);
2314	if (power_down)
2315	pm_runtime_put_autosuspend(pl330->ddma.dev);
2316	pm_runtime_put_autosuspend(pl330->ddma.dev);
2317
2318	return 0;
2319	}
2320
2321	/*
2322	* We don't support DMA_RESUME command because of hardware
2323	* limitations, so after pausing the channel we cannot restore
2324	* it to active state. We have to terminate channel and setup
2325	* DMA transfer again. This pause feature was implemented to
2326	* allow safely read residue before channel termination.
2327	*/
2328	static int pl330_pause(struct dma_chan *chan)
2329	{
2330	struct dma_pl330_chan *pch = to_pchan(chan);
2331	struct pl330_dmac *pl330 = pch->dmac;
2332	struct dma_pl330_desc *desc;
2333	unsigned long flags;
2334
2335	pm_runtime_get_sync(pl330->ddma.dev);
2336	spin_lock_irqsave(&pch->lock, flags);
2337
2338	spin_lock(&pl330->lock);
2339	_stop(pch->thread);
2340	spin_unlock(&pl330->lock);
2341
2342	list_for_each_entry(desc, &pch->work_list, node) {
2343	if (desc->status == BUSY)
2344	desc->status = PAUSED;
2345	}
2346	spin_unlock_irqrestore(&pch->lock, flags);
2347	pm_runtime_put_autosuspend(pl330->ddma.dev);
2348
2349	return 0;
2350	}
2351
2352	static void pl330_free_chan_resources(struct dma_chan *chan)
2353	{
2354	struct dma_pl330_chan *pch = to_pchan(chan);
2355	struct pl330_dmac *pl330 = pch->dmac;
2356	unsigned long flags;
2357
2358	tasklet_kill(&pch->task);
2359
2360	pm_runtime_get_sync(pch->dmac->ddma.dev);
2361	spin_lock_irqsave(&pl330->lock, flags);
2362
2363	pl330_release_channel(pch->thread);
2364	pch->thread = NULL;
2365
2366	if (pch->cyclic)
2367	list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
2368
2369	spin_unlock_irqrestore(&pl330->lock, flags);
2370	pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2371	pl330_unprep_slave_fifo(pch);
2372	}
2373
2374	static int pl330_get_current_xferred_count(struct dma_pl330_chan *pch,
2375	struct dma_pl330_desc *desc)
2376	{
2377	struct pl330_thread *thrd = pch->thread;
2378	struct pl330_dmac *pl330 = pch->dmac;
2379	void __iomem *regs = thrd->dmac->base;
2380	u32 val, addr;
2381
2382	pm_runtime_get_sync(pl330->ddma.dev);
2383	val = addr = 0;
2384	if (desc->rqcfg.src_inc) {
2385	val = readl(regs + SA(thrd->id));
2386	addr = desc->px.src_addr;
2387	} else {
2388	val = readl(regs + DA(thrd->id));
2389	addr = desc->px.dst_addr;
2390	}
2391	pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2392	pm_runtime_put_autosuspend(pl330->ddma.dev);
2393
2394	/* If DMAMOV hasn't finished yet, SAR/DAR can be zero */
2395	if (!val)
2396	return 0;
2397
2398	return val - addr;
2399	}
2400
2401	static enum dma_status
2402	pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
2403	struct dma_tx_state *txstate)
2404	{
2405	enum dma_status ret;
2406	unsigned long flags;
2407	struct dma_pl330_desc desc, running = NULL, *last_enq = NULL;
2408	struct dma_pl330_chan *pch = to_pchan(chan);
2409	unsigned int transferred, residual = 0;
2410
2411	ret = dma_cookie_status(chan, cookie, txstate);
2412
2413	if (!txstate)
2414	return ret;
2415
2416	if (ret == DMA_COMPLETE)
2417	goto out;
2418
2419	spin_lock_irqsave(&pch->lock, flags);
2420	spin_lock(&pch->thread->dmac->lock);
2421
2422	if (pch->thread->req_running != -1)
2423	running = pch->thread->req[pch->thread->req_running].desc;
2424
2425	last_enq = pch->thread->req[pch->thread->lstenq].desc;
2426
2427	/* Check in pending list */
2428	list_for_each_entry(desc, &pch->work_list, node) {
2429	if (desc->status == DONE)
2430	transferred = desc->bytes_requested;
2431	else if (running && desc == running)
2432	transferred =
2433	pl330_get_current_xferred_count(pch, desc);
2434	else if (desc->status == BUSY \|\| desc->status == PAUSED)
2435	/*
2436	* Busy but not running means either just enqueued,
2437	* or finished and not yet marked done
2438	*/
2439	if (desc == last_enq)
2440	transferred = 0;
2441	else
2442	transferred = desc->bytes_requested;
2443	else
2444	transferred = 0;
2445	residual += desc->bytes_requested - transferred;
2446	if (desc->txd.cookie == cookie) {
2447	switch (desc->status) {
2448	case DONE:
2449	ret = DMA_COMPLETE;
2450	break;
2451	case PAUSED:
2452	ret = DMA_PAUSED;
2453	break;
2454	case PREP:
2455	case BUSY:
2456	ret = DMA_IN_PROGRESS;
2457	break;
2458	default:
2459	WARN_ON(1);
2460	}
2461	break;
2462	}
2463	if (desc->last)
2464	residual = 0;
2465	}
2466	spin_unlock(&pch->thread->dmac->lock);
2467	spin_unlock_irqrestore(&pch->lock, flags);
2468
2469	out:
2470	dma_set_residue(txstate, residual);
2471
2472	return ret;
2473	}
2474
2475	static void pl330_issue_pending(struct dma_chan *chan)
2476	{
2477	struct dma_pl330_chan *pch = to_pchan(chan);
2478	unsigned long flags;
2479
2480	spin_lock_irqsave(&pch->lock, flags);
2481	if (list_empty(&pch->work_list)) {
2482	/*
2483	* Warn on nothing pending. Empty submitted_list may
2484	* break our pm_runtime usage counter as it is
2485	* updated on work_list emptiness status.
2486	*/
2487	WARN_ON(list_empty(&pch->submitted_list));
2488	pch->active = true;
2489	pm_runtime_get_sync(pch->dmac->ddma.dev);
2490	}
2491	list_splice_tail_init(&pch->submitted_list, &pch->work_list);
2492	spin_unlock_irqrestore(&pch->lock, flags);
2493
2494	pl330_tasklet(&pch->task);
2495	}
2496
2497	/*
2498	* We returned the last one of the circular list of descriptor(s)
2499	* from prep_xxx, so the argument to submit corresponds to the last
2500	* descriptor of the list.
2501	*/
2502	static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
2503	{
2504	struct dma_pl330_desc desc, last = to_desc(tx);
2505	struct dma_pl330_chan *pch = to_pchan(tx->chan);
2506	dma_cookie_t cookie;
2507	unsigned long flags;
2508
2509	spin_lock_irqsave(&pch->lock, flags);
2510
2511	/* Assign cookies to all nodes */
2512	while (!list_empty(&last->node)) {
2513	desc = list_entry(last->node.next, struct dma_pl330_desc, node);
2514	if (pch->cyclic) {
2515	desc->txd.callback = last->txd.callback;
2516	desc->txd.callback_param = last->txd.callback_param;
2517	}
2518	desc->last = false;
2519
2520	dma_cookie_assign(&desc->txd);
2521
2522	list_move_tail(&desc->node, &pch->submitted_list);
2523	}
2524
2525	last->last = true;
2526	cookie = dma_cookie_assign(&last->txd);
2527	list_add_tail(&last->node, &pch->submitted_list);
2528	spin_unlock_irqrestore(&pch->lock, flags);
2529
2530	return cookie;
2531	}
2532
2533	static inline void _init_desc(struct dma_pl330_desc *desc)
2534	{
2535	desc->rqcfg.swap = SWAP_NO;
2536	desc->rqcfg.scctl = CCTRL0;
2537	desc->rqcfg.dcctl = CCTRL0;
2538	desc->txd.tx_submit = pl330_tx_submit;
2539
2540	INIT_LIST_HEAD(&desc->node);
2541	}
2542
2543	/* Returns the number of descriptors added to the DMAC pool */
2544	static int add_desc(struct list_head pool, spinlock_t lock,
2545	gfp_t flg, int count)
2546	{
2547	struct dma_pl330_desc *desc;
2548	unsigned long flags;
2549	int i;
2550
2551	desc = kzalloc_objs(*desc, count, flg);
2552	if (!desc)
2553	return 0;
2554
2555	spin_lock_irqsave(lock, flags);
2556
2557	for (i = 0; i < count; i++) {
2558	_init_desc(&desc[i]);
2559	list_add_tail(&desc[i].node, pool);
2560	}
2561
2562	spin_unlock_irqrestore(lock, flags);
2563
2564	return count;
2565	}
2566
2567	static struct dma_pl330_desc pluck_desc(struct list_head pool,
2568	spinlock_t *lock)
2569	{
2570	struct dma_pl330_desc *desc = NULL;
2571	unsigned long flags;
2572
2573	spin_lock_irqsave(lock, flags);
2574
2575	if (!list_empty(pool)) {
2576	desc = list_entry(pool->next,
2577	struct dma_pl330_desc, node);
2578
2579	list_del_init(&desc->node);
2580
2581	desc->status = PREP;
2582	desc->txd.callback = NULL;
2583	desc->txd.callback_result = NULL;
2584	}
2585
2586	spin_unlock_irqrestore(lock, flags);
2587
2588	return desc;
2589	}
2590
2591	static struct dma_pl330_desc pl330_get_desc(struct dma_pl330_chan pch)
2592	{
2593	struct pl330_dmac *pl330 = pch->dmac;
2594	u8 *peri_id = pch->chan.private;
2595	struct dma_pl330_desc *desc;
2596
2597	/* Pluck one desc from the pool of DMAC */
2598	desc = pluck_desc(&pl330->desc_pool, &pl330->pool_lock);
2599
2600	/* If the DMAC pool is empty, alloc new */
2601	if (!desc) {
2602	static DEFINE_SPINLOCK(lock);
2603	LIST_HEAD(pool);
2604
2605	if (!add_desc(&pool, &lock, GFP_ATOMIC, 1))
2606	return NULL;
2607
2608	desc = pluck_desc(&pool, &lock);
2609	WARN_ON(!desc \|\| !list_empty(&pool));
2610	}
2611
2612	/* Initialize the descriptor */
2613	desc->pchan = pch;
2614	desc->txd.cookie = 0;
2615	async_tx_ack(&desc->txd);
2616
2617	desc->peri = peri_id ? pch->chan.chan_id : 0;
2618	desc->rqcfg.pcfg = &pch->dmac->pcfg;
2619
2620	dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
2621
2622	return desc;
2623	}
2624
2625	static inline void fill_px(struct pl330_xfer *px,
2626	dma_addr_t dst, dma_addr_t src, size_t len)
2627	{
2628	px->bytes = len;
2629	px->dst_addr = dst;
2630	px->src_addr = src;
2631	}
2632
2633	static struct dma_pl330_desc *
2634	__pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst,
2635	dma_addr_t src, size_t len)
2636	{
2637	struct dma_pl330_desc *desc = pl330_get_desc(pch);
2638
2639	if (!desc) {
2640	dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2641	__func__, __LINE__);
2642	return NULL;
2643	}
2644
2645	/*
2646	* Ideally we should lookout for reqs bigger than
2647	* those that can be programmed with 256 bytes of
2648	* MC buffer, but considering a req size is seldom
2649	* going to be word-unaligned and more than 200MB,
2650	* we take it easy.
2651	* Also, should the limit is reached we'd rather
2652	* have the platform increase MC buffer size than
2653	* complicating this API driver.
2654	*/
2655	fill_px(&desc->px, dst, src, len);
2656
2657	return desc;
2658	}
2659
2660	/* Call after fixing burst size */
2661	static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
2662	{
2663	struct dma_pl330_chan *pch = desc->pchan;
2664	struct pl330_dmac *pl330 = pch->dmac;
2665	int burst_len;
2666
2667	burst_len = pl330->pcfg.data_bus_width / 8;
2668	burst_len *= pl330->pcfg.data_buf_dep / pl330->pcfg.num_chan;
2669	burst_len >>= desc->rqcfg.brst_size;
2670
2671	/* src/dst_burst_len can't be more than 16 */
2672	if (burst_len > PL330_MAX_BURST)
2673	burst_len = PL330_MAX_BURST;
2674
2675	return burst_len;
2676	}
2677
2678	static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
2679	struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
2680	size_t period_len, enum dma_transfer_direction direction,
2681	unsigned long flags)
2682	{
2683	struct dma_pl330_desc desc = NULL, first = NULL;
2684	struct dma_pl330_chan *pch = to_pchan(chan);
2685	struct pl330_dmac *pl330 = pch->dmac;
2686	unsigned int i;
2687	dma_addr_t dst;
2688	dma_addr_t src;
2689
2690	if (len % period_len != 0)
2691	return NULL;
2692
2693	if (!is_slave_direction(direction)) {
2694	dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n",
2695	__func__, __LINE__);
2696	return NULL;
2697	}
2698
2699	pl330_config_write(chan, &pch->slave_config, direction);
2700
2701	if (!pl330_prep_slave_fifo(pch, direction))
2702	return NULL;
2703
2704	for (i = 0; i < len / period_len; i++) {
2705	desc = pl330_get_desc(pch);
2706	if (!desc) {
2707	unsigned long iflags;
2708
2709	dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2710	__func__, __LINE__);
2711
2712	if (!first)
2713	return NULL;
2714
2715	spin_lock_irqsave(&pl330->pool_lock, iflags);
2716
2717	while (!list_empty(&first->node)) {
2718	desc = list_entry(first->node.next,
2719	struct dma_pl330_desc, node);
2720	list_move_tail(&desc->node, &pl330->desc_pool);
2721	}
2722
2723	list_move_tail(&first->node, &pl330->desc_pool);
2724
2725	spin_unlock_irqrestore(&pl330->pool_lock, iflags);
2726
2727	return NULL;
2728	}
2729
2730	switch (direction) {
2731	case DMA_MEM_TO_DEV:
2732	desc->rqcfg.src_inc = 1;
2733	desc->rqcfg.dst_inc = 0;
2734	src = dma_addr;
2735	dst = pch->fifo_dma;
2736	break;
2737	case DMA_DEV_TO_MEM:
2738	desc->rqcfg.src_inc = 0;
2739	desc->rqcfg.dst_inc = 1;
2740	src = pch->fifo_dma;
2741	dst = dma_addr;
2742	break;
2743	default:
2744	break;
2745	}
2746
2747	desc->rqtype = direction;
2748	desc->rqcfg.brst_size = pch->burst_sz;
2749	desc->rqcfg.brst_len = pch->burst_len;
2750	desc->bytes_requested = period_len;
2751	fill_px(&desc->px, dst, src, period_len);
2752
2753	if (!first)
2754	first = desc;
2755	else
2756	list_add_tail(&desc->node, &first->node);
2757
2758	dma_addr += period_len;
2759	}
2760
2761	if (!desc)
2762	return NULL;
2763
2764	pch->cyclic = true;
2765
2766	return &desc->txd;
2767	}
2768
2769	static struct dma_async_tx_descriptor *
2770	pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
2771	dma_addr_t src, size_t len, unsigned long flags)
2772	{
2773	struct dma_pl330_desc *desc;
2774	struct dma_pl330_chan *pch = to_pchan(chan);
2775	struct pl330_dmac *pl330;
2776	int burst;
2777
2778	if (unlikely(!pch \|\| !len))
2779	return NULL;
2780
2781	pl330 = pch->dmac;
2782
2783	desc = __pl330_prep_dma_memcpy(pch, dst, src, len);
2784	if (!desc)
2785	return NULL;
2786
2787	desc->rqcfg.src_inc = 1;
2788	desc->rqcfg.dst_inc = 1;
2789	desc->rqtype = DMA_MEM_TO_MEM;
2790
2791	/* Select max possible burst size */
2792	burst = pl330->pcfg.data_bus_width / 8;
2793
2794	/*
2795	* Make sure we use a burst size that aligns with all the memcpy
2796	* parameters because our DMA programming algorithm doesn't cope with
2797	* transfers which straddle an entry in the DMA device's MFIFO.
2798	*/
2799	while ((src \| dst \| len) & (burst - 1))
2800	burst /= 2;
2801
2802	desc->rqcfg.brst_size = 0;
2803	while (burst != (1 << desc->rqcfg.brst_size))
2804	desc->rqcfg.brst_size++;
2805
2806	desc->rqcfg.brst_len = get_burst_len(desc, len);
2807	/*
2808	* If burst size is smaller than bus width then make sure we only
2809	* transfer one at a time to avoid a burst stradling an MFIFO entry.
2810	*/
2811	if (burst * 8 < pl330->pcfg.data_bus_width)
2812	desc->rqcfg.brst_len = 1;
2813
2814	desc->bytes_requested = len;
2815
2816	return &desc->txd;
2817	}
2818
2819	static void __pl330_giveback_desc(struct pl330_dmac *pl330,
2820	struct dma_pl330_desc *first)
2821	{
2822	unsigned long flags;
2823	struct dma_pl330_desc *desc;
2824
2825	if (!first)
2826	return;
2827
2828	spin_lock_irqsave(&pl330->pool_lock, flags);
2829
2830	while (!list_empty(&first->node)) {
2831	desc = list_entry(first->node.next,
2832	struct dma_pl330_desc, node);
2833	list_move_tail(&desc->node, &pl330->desc_pool);
2834	}
2835
2836	list_move_tail(&first->node, &pl330->desc_pool);
2837
2838	spin_unlock_irqrestore(&pl330->pool_lock, flags);
2839	}
2840
2841	static struct dma_async_tx_descriptor *
2842	pl330_prep_slave_sg(struct dma_chan chan, struct scatterlist sgl,
2843	unsigned int sg_len, enum dma_transfer_direction direction,
2844	unsigned long flg, void *context)
2845	{
2846	struct dma_pl330_desc first, desc = NULL;
2847	struct dma_pl330_chan *pch = to_pchan(chan);
2848	struct scatterlist *sg;
2849	int i;
2850
2851	if (unlikely(!pch \|\| !sgl \|\| !sg_len))
2852	return NULL;
2853
2854	pl330_config_write(chan, &pch->slave_config, direction);
2855
2856	if (!pl330_prep_slave_fifo(pch, direction))
2857	return NULL;
2858
2859	first = NULL;
2860
2861	for_each_sg(sgl, sg, sg_len, i) {
2862
2863	desc = pl330_get_desc(pch);
2864	if (!desc) {
2865	struct pl330_dmac *pl330 = pch->dmac;
2866
2867	dev_err(pch->dmac->ddma.dev,
2868	"%s:%d Unable to fetch desc\n",
2869	__func__, __LINE__);
2870	__pl330_giveback_desc(pl330, first);
2871
2872	return NULL;
2873	}
2874
2875	if (!first)
2876	first = desc;
2877	else
2878	list_add_tail(&desc->node, &first->node);
2879
2880	if (direction == DMA_MEM_TO_DEV) {
2881	desc->rqcfg.src_inc = 1;
2882	desc->rqcfg.dst_inc = 0;
2883	fill_px(&desc->px, pch->fifo_dma, sg_dma_address(sg),
2884	sg_dma_len(sg));
2885	} else {
2886	desc->rqcfg.src_inc = 0;
2887	desc->rqcfg.dst_inc = 1;
2888	fill_px(&desc->px, sg_dma_address(sg), pch->fifo_dma,
2889	sg_dma_len(sg));
2890	}
2891
2892	desc->rqcfg.brst_size = pch->burst_sz;
2893	desc->rqcfg.brst_len = pch->burst_len;
2894	desc->rqtype = direction;
2895	desc->bytes_requested = sg_dma_len(sg);
2896	}
2897
2898	/* Return the last desc in the chain */
2899	return &desc->txd;
2900	}
2901
2902	static irqreturn_t pl330_irq_handler(int irq, void *data)
2903	{
2904	if (pl330_update(data))
2905	return IRQ_HANDLED;
2906	else
2907	return IRQ_NONE;
2908	}
2909
2910	#define PL330_DMA_BUSWIDTHS \
2911	BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) \| \
2912	BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) \| \
2913	BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) \| \
2914	BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) \| \
2915	BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
2916
2917	#ifdef CONFIG_DEBUG_FS
2918	static int pl330_debugfs_show(struct seq_file s, void data)
2919	{
2920	struct pl330_dmac *pl330 = s->private;
2921	int chans, pchs, ch, pr;
2922
2923	chans = pl330->pcfg.num_chan;
2924	pchs = pl330->num_peripherals;
2925
2926	seq_puts(s, "PL330 physical channels:\n");
2927	seq_puts(s, "THREAD:\t\tCHANNEL:\n");
2928	seq_puts(s, "--------\t-----\n");
2929	for (ch = 0; ch < chans; ch++) {
2930	struct pl330_thread *thrd = &pl330->channels[ch];
2931	int found = -1;
2932
2933	for (pr = 0; pr < pchs; pr++) {
2934	struct dma_pl330_chan *pch = &pl330->peripherals[pr];
2935
2936	if (!pch->thread \|\| thrd->id != pch->thread->id)
2937	continue;
2938
2939	found = pr;
2940	}
2941
2942	seq_printf(s, "%d\t\t", thrd->id);
2943	if (found == -1)
2944	seq_puts(s, "--\n");
2945	else
2946	seq_printf(s, "%d\n", found);
2947	}
2948
2949	return 0;
2950	}
2951
2952	DEFINE_SHOW_ATTRIBUTE(pl330_debugfs);
2953
2954	static inline void init_pl330_debugfs(struct pl330_dmac *pl330)
2955	{
2956	pl330->dbgfs = debugfs_create_file(dev_name(pl330->ddma.dev),
2957	S_IFREG \| 0444, NULL, pl330,
2958	&pl330_debugfs_fops);
2959	}
2960
2961	static inline void deinit_pl330_debugfs(struct pl330_dmac *pl330)
2962	{
2963	debugfs_remove(pl330->dbgfs);
2964	pl330->dbgfs = NULL;
2965	}
2966	#else
2967	static inline void init_pl330_debugfs(struct pl330_dmac *pl330)
2968	{
2969	}
2970
2971	static inline void deinit_pl330_debugfs(struct pl330_dmac *pl330)
2972	{
2973	}
2974	#endif
2975
2976	/*
2977	* Runtime PM callbacks are provided by amba/bus.c driver.
2978	*
2979	* It is assumed here that IRQ safe runtime PM is chosen in probe and amba
2980	* bus driver will only disable/enable the clock in runtime PM callbacks.
2981	*/
2982	static int __maybe_unused pl330_suspend(struct device *dev)
2983	{
2984	struct amba_device *pcdev = to_amba_device(dev);
2985
2986	pm_runtime_force_suspend(dev);
2987	clk_unprepare(pcdev->pclk);
2988
2989	return 0;
2990	}
2991
2992	static int __maybe_unused pl330_resume(struct device *dev)
2993	{
2994	struct amba_device *pcdev = to_amba_device(dev);
2995	int ret;
2996
2997	ret = clk_prepare(pcdev->pclk);
2998	if (ret)
2999	return ret;
3000
3001	pm_runtime_force_resume(dev);
3002
3003	return ret;
3004	}
3005
3006	static const struct dev_pm_ops pl330_pm = {
3007	SET_LATE_SYSTEM_SLEEP_PM_OPS(pl330_suspend, pl330_resume)
3008	};
3009
3010	static int
3011	pl330_probe(struct amba_device adev, const struct amba_id id)
3012	{
3013	struct pl330_config *pcfg;
3014	struct pl330_dmac *pl330;
3015	struct dma_pl330_chan pch, _p;
3016	struct dma_device *pd;
3017	struct resource *res;
3018	int i, ret, irq;
3019	int num_chan;
3020	struct device_node *np = adev->dev.of_node;
3021
3022	ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32));
3023	if (ret)
3024	return ret;
3025
3026	/* Allocate a new DMAC and its Channels */
3027	pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL);
3028	if (!pl330)
3029	return -ENOMEM;
3030
3031	pd = &pl330->ddma;
3032	pd->dev = &adev->dev;
3033
3034	pl330->mcbufsz = 0;
3035
3036	/* get quirk */
3037	for (i = 0; i < ARRAY_SIZE(of_quirks); i++)
3038	if (of_property_read_bool(np, of_quirks[i].quirk))
3039	pl330->quirks \|= of_quirks[i].id;
3040
3041	res = &adev->res;
3042	pl330->base = devm_ioremap_resource(&adev->dev, res);
3043	if (IS_ERR(pl330->base))
3044	return PTR_ERR(pl330->base);
3045
3046	amba_set_drvdata(adev, pl330);
3047
3048	pl330->rstc = devm_reset_control_get_optional(&adev->dev, "dma");
3049	if (IS_ERR(pl330->rstc)) {
3050	return dev_err_probe(&adev->dev, PTR_ERR(pl330->rstc), "Failed to get reset!\n");
3051	} else {
3052	ret = reset_control_deassert(pl330->rstc);
3053	if (ret) {
3054	dev_err(&adev->dev, "Couldn't deassert the device from reset!\n");
3055	return ret;
3056	}
3057	}
3058
3059	pl330->rstc_ocp = devm_reset_control_get_optional(&adev->dev, "dma-ocp");
3060	if (IS_ERR(pl330->rstc_ocp)) {
3061	return dev_err_probe(&adev->dev, PTR_ERR(pl330->rstc_ocp),
3062	"Failed to get OCP reset!\n");
3063	} else {
3064	ret = reset_control_deassert(pl330->rstc_ocp);
3065	if (ret) {
3066	dev_err(&adev->dev, "Couldn't deassert the device from OCP reset!\n");
3067	return ret;
3068	}
3069	}
3070
3071	for (i = 0; i < AMBA_NR_IRQS; i++) {
3072	irq = adev->irq[i];
3073	if (irq) {
3074	ret = devm_request_irq(&adev->dev, irq,
3075	pl330_irq_handler, 0,
3076	dev_name(&adev->dev), pl330);
3077	if (ret)
3078	return ret;
3079	} else {
3080	break;
3081	}
3082	}
3083
3084	pcfg = &pl330->pcfg;
3085
3086	pcfg->periph_id = adev->periphid;
3087	ret = pl330_add(pl330);
3088	if (ret)
3089	return ret;
3090
3091	INIT_LIST_HEAD(&pl330->desc_pool);
3092	spin_lock_init(&pl330->pool_lock);
3093
3094	/* Create a descriptor pool of default size */
3095	if (!add_desc(&pl330->desc_pool, &pl330->pool_lock,
3096	GFP_KERNEL, NR_DEFAULT_DESC))
3097	dev_warn(&adev->dev, "unable to allocate desc\n");
3098
3099	INIT_LIST_HEAD(&pd->channels);
3100
3101	/* Initialize channel parameters */
3102	num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan);
3103
3104	pl330->num_peripherals = num_chan;
3105
3106	pl330->peripherals = kzalloc_objs(*pch, num_chan);
3107	if (!pl330->peripherals) {
3108	ret = -ENOMEM;
3109	goto probe_err2;
3110	}
3111
3112	for (i = 0; i < num_chan; i++) {
3113	pch = &pl330->peripherals[i];
3114
3115	pch->chan.private = adev->dev.of_node;
3116	INIT_LIST_HEAD(&pch->submitted_list);
3117	INIT_LIST_HEAD(&pch->work_list);
3118	INIT_LIST_HEAD(&pch->completed_list);
3119	spin_lock_init(&pch->lock);
3120	pch->thread = NULL;
3121	pch->chan.device = pd;
3122	pch->dmac = pl330;
3123	pch->dir = DMA_NONE;
3124
3125	/* Add the channel to the DMAC list */
3126	list_add_tail(&pch->chan.device_node, &pd->channels);
3127	}
3128
3129	dma_cap_set(DMA_MEMCPY, pd->cap_mask);
3130	if (pcfg->num_peri) {
3131	dma_cap_set(DMA_SLAVE, pd->cap_mask);
3132	dma_cap_set(DMA_CYCLIC, pd->cap_mask);
3133	dma_cap_set(DMA_PRIVATE, pd->cap_mask);
3134	}
3135
3136	pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
3137	pd->device_free_chan_resources = pl330_free_chan_resources;
3138	pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
3139	pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
3140	pd->device_tx_status = pl330_tx_status;
3141	pd->device_prep_slave_sg = pl330_prep_slave_sg;
3142	pd->device_config = pl330_config;
3143	pd->device_pause = pl330_pause;
3144	pd->device_terminate_all = pl330_terminate_all;
3145	pd->device_issue_pending = pl330_issue_pending;
3146	pd->src_addr_widths = PL330_DMA_BUSWIDTHS;
3147	pd->dst_addr_widths = PL330_DMA_BUSWIDTHS;
3148	pd->directions = BIT(DMA_DEV_TO_MEM) \| BIT(DMA_MEM_TO_DEV);
3149	pd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
3150	pd->max_burst = PL330_MAX_BURST;
3151
3152	ret = dma_async_device_register(pd);
3153	if (ret) {
3154	dev_err(&adev->dev, "unable to register DMAC\n");
3155	goto probe_err3;
3156	}
3157
3158	if (adev->dev.of_node) {
3159	ret = of_dma_controller_register(adev->dev.of_node,
3160	of_dma_pl330_xlate, pl330);
3161	if (ret) {
3162	dev_err(&adev->dev,
3163	"unable to register DMA to the generic DT DMA helpers\n");
3164	}
3165	}
3166
3167	/*
3168	* This is the limit for transfers with a buswidth of 1, larger
3169	* buswidths will have larger limits.
3170	*/
3171	dma_set_max_seg_size(&adev->dev, 1900800);
3172
3173	init_pl330_debugfs(pl330);
3174	dev_info(&adev->dev,
3175	"Loaded driver for PL330 DMAC-%x\n", adev->periphid);
3176	dev_info(&adev->dev,
3177	"\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
3178	pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan,
3179	pcfg->num_peri, pcfg->num_events);
3180
3181	pm_runtime_irq_safe(&adev->dev);
3182	pm_runtime_use_autosuspend(&adev->dev);
3183	pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY);
3184	pm_runtime_put_autosuspend(&adev->dev);
3185
3186	return 0;
3187	probe_err3:
3188	/* Idle the DMAC */
3189	list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
3190	chan.device_node) {
3191
3192	/* Remove the channel */
3193	list_del(&pch->chan.device_node);
3194
3195	/* Flush the channel */
3196	if (pch->thread) {
3197	pl330_terminate_all(&pch->chan);
3198	pl330_free_chan_resources(&pch->chan);
3199	}
3200	}
3201	probe_err2:
3202	pl330_del(pl330);
3203
3204	if (pl330->rstc_ocp)
3205	reset_control_assert(pl330->rstc_ocp);
3206
3207	if (pl330->rstc)
3208	reset_control_assert(pl330->rstc);
3209	return ret;
3210	}
3211
3212	static void pl330_remove(struct amba_device *adev)
3213	{
3214	struct pl330_dmac *pl330 = amba_get_drvdata(adev);
3215	struct dma_pl330_chan pch, _p;
3216	int i, irq;
3217
3218	deinit_pl330_debugfs(pl330);
3219
3220	pm_runtime_get_noresume(pl330->ddma.dev);
3221
3222	if (adev->dev.of_node)
3223	of_dma_controller_free(adev->dev.of_node);
3224
3225	for (i = 0; i < AMBA_NR_IRQS; i++) {
3226	irq = adev->irq[i];
3227	if (irq)
3228	devm_free_irq(&adev->dev, irq, pl330);
3229	}
3230
3231	dma_async_device_unregister(&pl330->ddma);
3232
3233	/* Idle the DMAC */
3234	list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
3235	chan.device_node) {
3236
3237	/* Remove the channel */
3238	list_del(&pch->chan.device_node);
3239
3240	/* Flush the channel */
3241	if (pch->thread) {
3242	pl330_terminate_all(&pch->chan);
3243	pl330_free_chan_resources(&pch->chan);
3244	}
3245	}
3246
3247	pl330_del(pl330);
3248
3249	if (pl330->rstc_ocp)
3250	reset_control_assert(pl330->rstc_ocp);
3251
3252	if (pl330->rstc)
3253	reset_control_assert(pl330->rstc);
3254	}
3255
3256	static const struct amba_id pl330_ids[] = {
3257	{
3258	.id = 0x00041330,
3259	.mask = 0x000fffff,
3260	},
3261	{ 0, 0 },
3262	};
3263
3264	MODULE_DEVICE_TABLE(amba, pl330_ids);
3265
3266	static struct amba_driver pl330_driver = {
3267	.drv = {
3268	.name = "dma-pl330",
3269	.pm = &pl330_pm,
3270	},
3271	.id_table = pl330_ids,
3272	.probe = pl330_probe,
3273	.remove = pl330_remove,
3274	};
3275
3276	module_amba_driver(pl330_driver);
3277
3278	MODULE_AUTHOR("Jaswinder Singh <[email protected]>");
3279	MODULE_DESCRIPTION("API Driver for PL330 DMAC");
3280	MODULE_LICENSE("GPL");