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1#
2# EDAC Kconfig
3# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
4# Licensed and distributed under the GPL
5
6config EDAC_ATOMIC_SCRUB
7 bool
8
9config EDAC_SUPPORT
10 bool
11
12menuconfig EDAC
13 tristate "EDAC (Error Detection And Correction) reporting"
14 depends on HAS_IOMEM && EDAC_SUPPORT && RAS
15 help
16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
18 in the CPU or supporting chipset or other subsystems:
19 memory errors, cache errors, PCI errors, thermal throttling, etc..
20 If unsure, select 'Y'.
21
22 The mailing list for the EDAC project is [email protected].
23
24if EDAC
25
26config EDAC_DEBUG
27 bool "Debugging"
28 select DEBUG_FS
29 help
30 This turns on debugging information for the entire EDAC subsystem.
31 You do so by inserting edac_module with "edac_debug_level=x." Valid
32 levels are 0-4 (from low to high) and by default it is set to 2.
33 Usually you should select 'N' here.
34
35config EDAC_DECODE_MCE
36 tristate "Decode MCEs in human-readable form (only on AMD for now)"
37 depends on CPU_SUP_AMD && X86_MCE_AMD
38 default y
39 help
40 Enable this option if you want to decode Machine Check Exceptions
41 occurring on your machine in human-readable form.
42
43 You should definitely say Y here in case you want to decode MCEs
44 which occur really early upon boot, before the module infrastructure
45 has been initialized.
46
47config EDAC_GHES
48 tristate "Output ACPI APEI/GHES BIOS detected errors via EDAC"
49 depends on ACPI_APEI_GHES
50 select UEFI_CPER
51 help
52 Not all machines support hardware-driven error report. Some of those
53 provide a BIOS-driven error report mechanism via ACPI, using the
54 APEI/GHES driver. By enabling this option, the error reports provided
55 by GHES are sent to userspace via the EDAC API.
56
57 When this option is enabled, it will disable the hardware-driven
58 mechanisms, if a GHES BIOS is detected, entering into the
59 "Firmware First" mode.
60
61 It should be noticed that keeping both GHES and a hardware-driven
62 error mechanism won't work well, as BIOS will race with OS, while
63 reading the error registers. So, if you want to not use "Firmware
64 first" GHES error mechanism, you should disable GHES either at
65 compilation time or by passing "ghes.disable=1" Kernel parameter
66 at boot time.
67
68 In doubt, say 'Y'.
69
70config EDAC_SCRUB
71 bool "EDAC scrub feature"
72 help
73 The EDAC scrub feature is optional and is designed to control the
74 memory scrubbers in the system. The common sysfs scrub interface
75 abstracts the control of various arbitrary scrubbing functionalities
76 into a unified set of functions.
77 Say 'y/n' to enable/disable EDAC scrub feature.
78
79config EDAC_ECS
80 bool "EDAC ECS (Error Check Scrub) feature"
81 help
82 The EDAC ECS feature is optional and is designed to control on-die
83 error check scrub (e.g., DDR5 ECS) in the system. The common sysfs
84 ECS interface abstracts the control of various ECS functionalities
85 into a unified set of functions.
86 Say 'y/n' to enable/disable EDAC ECS feature.
87
88config EDAC_MEM_REPAIR
89 bool "EDAC memory repair feature"
90 help
91 The EDAC memory repair feature is optional and is designed to control
92 the memory devices with repair features, such as Post Package Repair
93 (PPR), memory sparing etc. The common sysfs memory repair interface
94 abstracts the control of various memory repair functionalities into
95 a unified set of functions.
96 Say 'y/n' to enable/disable EDAC memory repair feature.
97
98config EDAC_AMD64
99 tristate "AMD64 (Opteron, Athlon64)"
100 depends on AMD_NB && EDAC_DECODE_MCE
101 depends on AMD_NODE
102 imply AMD_ATL
103 help
104 Support for error detection and correction of DRAM ECC errors on
105 the AMD64 families (>= K8) of memory controllers.
106
107 When EDAC_DEBUG is enabled, hardware error injection facilities
108 through sysfs are available:
109
110 AMD CPUs up to and excluding family 0x17 provide for Memory
111 Error Injection into the ECC detection circuits. The amd64_edac
112 module allows the operator/user to inject Uncorrectable and
113 Correctable errors into DRAM.
114
115 When enabled, in each of the respective memory controller directories
116 (/sys/devices/system/edac/mc/mcX), there are 3 input files:
117
118 - inject_section (0..3, 16-byte section of 64-byte cacheline),
119 - inject_word (0..8, 16-bit word of 16-byte section),
120 - inject_ecc_vector (hex ecc vector: select bits of inject word)
121
122 In addition, there are two control files, inject_read and inject_write,
123 which trigger the DRAM ECC Read and Write respectively.
124
125config EDAC_AL_MC
126 tristate "Amazon's Annapurna Lab Memory Controller"
127 depends on (ARCH_ALPINE || COMPILE_TEST)
128 help
129 Support for error detection and correction for Amazon's Annapurna
130 Labs Alpine chips which allow 1 bit correction and 2 bits detection.
131
132config EDAC_AMD76X
133 tristate "AMD 76x (760, 762, 768)"
134 depends on PCI && X86_32
135 help
136 Support for error detection and correction on the AMD 76x
137 series of chipsets used with the Athlon processor.
138
139config EDAC_E7XXX
140 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
141 depends on PCI && X86_32
142 help
143 Support for error detection and correction on the Intel
144 E7205, E7500, E7501 and E7505 server chipsets.
145
146config EDAC_E752X
147 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
148 depends on PCI && X86
149 help
150 Support for error detection and correction on the Intel
151 E7520, E7525, E7320 server chipsets.
152
153config EDAC_I82875P
154 tristate "Intel 82875p (D82875P, E7210)"
155 depends on PCI && X86_32
156 help
157 Support for error detection and correction on the Intel
158 DP82785P and E7210 server chipsets.
159
160config EDAC_I82975X
161 tristate "Intel 82975x (D82975x)"
162 depends on PCI && X86
163 help
164 Support for error detection and correction on the Intel
165 DP82975x server chipsets.
166
167config EDAC_I3000
168 tristate "Intel 3000/3010"
169 depends on PCI && X86
170 help
171 Support for error detection and correction on the Intel
172 3000 and 3010 server chipsets.
173
174config EDAC_I3200
175 tristate "Intel 3200"
176 depends on PCI && X86
177 help
178 Support for error detection and correction on the Intel
179 3200 and 3210 server chipsets.
180
181config EDAC_IE31200
182 tristate "Intel e312xx"
183 depends on PCI && X86 && X86_MCE_INTEL
184 help
185 Support for error detection and correction on the Intel
186 E3-1200 based DRAM controllers.
187
188config EDAC_X38
189 tristate "Intel X38"
190 depends on PCI && X86
191 help
192 Support for error detection and correction on the Intel
193 X38 server chipsets.
194
195config EDAC_I5400
196 tristate "Intel 5400 (Seaburg) chipsets"
197 depends on PCI && X86
198 help
199 Support for error detection and correction the Intel
200 i5400 MCH chipset (Seaburg).
201
202config EDAC_I7CORE
203 tristate "Intel i7 Core (Nehalem) processors"
204 depends on PCI && X86 && X86_MCE_INTEL
205 help
206 Support for error detection and correction the Intel
207 i7 Core (Nehalem) Integrated Memory Controller that exists on
208 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
209 and Xeon 55xx processors.
210
211config EDAC_I82860
212 tristate "Intel 82860"
213 depends on PCI && X86_32
214 help
215 Support for error detection and correction on the Intel
216 82860 chipset.
217
218config EDAC_I5000
219 tristate "Intel Greencreek/Blackford chipset"
220 depends on X86 && PCI
221 depends on BROKEN
222 help
223 Support for error detection and correction the Intel
224 Greekcreek/Blackford chipsets.
225
226config EDAC_I5100
227 tristate "Intel San Clemente MCH"
228 depends on X86 && PCI
229 help
230 Support for error detection and correction the Intel
231 San Clemente MCH.
232
233config EDAC_I7300
234 tristate "Intel Clarksboro MCH"
235 depends on X86 && PCI
236 help
237 Support for error detection and correction the Intel
238 Clarksboro MCH (Intel 7300 chipset).
239
240config EDAC_SBRIDGE
241 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
242 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
243 help
244 Support for error detection and correction the Intel
245 Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
246
247config EDAC_SKX
248 tristate "Intel Skylake server Integrated MC"
249 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
250 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y
251 select DMI
252 select ACPI_ADXL
253 help
254 Support for error detection and correction the Intel
255 Skylake server Integrated Memory Controllers. If your
256 system has non-volatile DIMMs you should also manually
257 select CONFIG_ACPI_NFIT.
258
259config EDAC_I10NM
260 tristate "Intel 10nm server Integrated MC"
261 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
262 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y
263 select DMI
264 select ACPI_ADXL
265 help
266 Support for error detection and correction the Intel
267 10nm server Integrated Memory Controllers. If your
268 system has non-volatile DIMMs you should also manually
269 select CONFIG_ACPI_NFIT.
270
271config EDAC_IMH
272 tristate "Intel Integrated Memory/IO Hub MC"
273 depends on X86_64 && X86_MCE_INTEL && ACPI
274 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_IMH can't be y
275 select DMI
276 select ACPI_ADXL
277 help
278 Support for error detection and correction the Intel
279 Integrated Memory/IO Hub Memory Controller. This MC IP is
280 first used on the Diamond Rapids servers but may appear on
281 others in the future.
282
283config EDAC_INTEL_BFF_RESET
284 tristate "Intel bitfix filter reset driver"
285 depends on X86_64 && X86_MCE_INTEL
286 help
287 Support for Intel systems that implement bitfix filters to
288 suppress repeated logging and signaling of the same corrected
289 error. Those filters can become clogged with transient errors
290 over time. Clearing the filter may make space for additional
291 hard errors.
292
293 To compile this driver as a module, choose M here: the module
294 will be called intel_bff.
295
296config EDAC_PND2
297 tristate "Intel Pondicherry2"
298 depends on PCI && X86_64 && X86_MCE_INTEL
299 select P2SB if X86
300 help
301 Support for error detection and correction on the Intel
302 Pondicherry2 Integrated Memory Controller. This SoC IP is
303 first used on the Apollo Lake platform and Denverton
304 micro-server but may appear on others in the future.
305
306config EDAC_IGEN6
307 tristate "Intel client SoC Integrated MC"
308 depends on PCI && PCI_MMCONFIG && ARCH_HAVE_NMI_SAFE_CMPXCHG
309 depends on X86_64 && X86_MCE_INTEL
310 help
311 Support for error detection and correction on the Intel
312 client SoC Integrated Memory Controller using In-Band ECC IP.
313 This In-Band ECC is first used on the Elkhart Lake SoC but
314 may appear on others in the future.
315
316config EDAC_MPC85XX
317 bool "Freescale MPC83xx / MPC85xx"
318 depends on FSL_SOC && EDAC=y
319 help
320 Support for error detection and correction on the Freescale
321 MPC8349, MPC8560, MPC8540, MPC8548, T4240
322
323config EDAC_LAYERSCAPE
324 tristate "Freescale Layerscape DDR"
325 depends on ARCH_LAYERSCAPE || SOC_LS1021A
326 help
327 Support for error detection and correction on Freescale memory
328 controllers on Layerscape SoCs.
329
330config EDAC_PASEMI
331 tristate "PA Semi PWRficient"
332 depends on PPC_PASEMI && PCI
333 help
334 Support for error detection and correction on PA Semi
335 PWRficient.
336
337config EDAC_CPC925
338 tristate "IBM CPC925 Memory Controller (PPC970FX)"
339 depends on PPC64
340 help
341 Support for error detection and correction on the
342 IBM CPC925 Bridge and Memory Controller, which is
343 a companion chip to the PowerPC 970 family of
344 processors.
345
346config EDAC_HIGHBANK_MC
347 tristate "Highbank Memory Controller"
348 depends on ARCH_HIGHBANK
349 help
350 Support for error detection and correction on the
351 Calxeda Highbank memory controller.
352
353config EDAC_HIGHBANK_L2
354 tristate "Highbank L2 Cache"
355 depends on ARCH_HIGHBANK
356 help
357 Support for error detection and correction on the
358 Calxeda Highbank memory controller.
359
360config EDAC_OCTEON_PC
361 tristate "Cavium Octeon Primary Caches"
362 depends on CPU_CAVIUM_OCTEON
363 help
364 Support for error detection and correction on the primary caches of
365 the cnMIPS cores of Cavium Octeon family SOCs.
366
367config EDAC_OCTEON_L2C
368 tristate "Cavium Octeon Secondary Caches (L2C)"
369 depends on CAVIUM_OCTEON_SOC
370 help
371 Support for error detection and correction on the
372 Cavium Octeon family of SOCs.
373
374config EDAC_OCTEON_LMC
375 tristate "Cavium Octeon DRAM Memory Controller (LMC)"
376 depends on CAVIUM_OCTEON_SOC
377 help
378 Support for error detection and correction on the
379 Cavium Octeon family of SOCs.
380
381config EDAC_OCTEON_PCI
382 tristate "Cavium Octeon PCI Controller"
383 depends on PCI && CAVIUM_OCTEON_SOC
384 help
385 Support for error detection and correction on the
386 Cavium Octeon family of SOCs.
387
388config EDAC_THUNDERX
389 tristate "Cavium ThunderX EDAC"
390 depends on ARM64
391 depends on PCI
392 help
393 Support for error detection and correction on the
394 Cavium ThunderX memory controllers (LMC), Cache
395 Coherent Processor Interconnect (CCPI) and L2 cache
396 blocks (TAD, CBC, MCI).
397
398config EDAC_ALTERA
399 bool "Altera SOCFPGA ECC"
400 depends on EDAC=y && ARCH_INTEL_SOCFPGA
401 help
402 Support for error detection and correction on the
403 Altera SOCs. This is the global enable for the
404 various Altera peripherals.
405
406config EDAC_ALTERA_SDRAM
407 bool "Altera SDRAM ECC"
408 depends on EDAC_ALTERA=y
409 help
410 Support for error detection and correction on the
411 Altera SDRAM Memory for Altera SoCs. Note that the
412 preloader must initialize the SDRAM before loading
413 the kernel.
414
415config EDAC_ALTERA_L2C
416 bool "Altera L2 Cache ECC"
417 depends on EDAC_ALTERA=y && CACHE_L2X0
418 help
419 Support for error detection and correction on the
420 Altera L2 cache Memory for Altera SoCs. This option
421 requires L2 cache.
422
423config EDAC_ALTERA_OCRAM
424 bool "Altera On-Chip RAM ECC"
425 depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR
426 help
427 Support for error detection and correction on the
428 Altera On-Chip RAM Memory for Altera SoCs.
429
430config EDAC_ALTERA_ETHERNET
431 bool "Altera Ethernet FIFO ECC"
432 depends on EDAC_ALTERA=y
433 help
434 Support for error detection and correction on the
435 Altera Ethernet FIFO Memory for Altera SoCs.
436
437config EDAC_ALTERA_NAND
438 bool "Altera NAND FIFO ECC"
439 depends on EDAC_ALTERA=y && MTD_NAND_DENALI
440 help
441 Support for error detection and correction on the
442 Altera NAND FIFO Memory for Altera SoCs.
443
444config EDAC_ALTERA_DMA
445 bool "Altera DMA FIFO ECC"
446 depends on EDAC_ALTERA=y && PL330_DMA=y
447 help
448 Support for error detection and correction on the
449 Altera DMA FIFO Memory for Altera SoCs.
450
451config EDAC_ALTERA_USB
452 bool "Altera USB FIFO ECC"
453 depends on EDAC_ALTERA=y && USB_DWC2
454 help
455 Support for error detection and correction on the
456 Altera USB FIFO Memory for Altera SoCs.
457
458config EDAC_ALTERA_QSPI
459 bool "Altera QSPI FIFO ECC"
460 depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI
461 help
462 Support for error detection and correction on the
463 Altera QSPI FIFO Memory for Altera SoCs.
464
465config EDAC_ALTERA_SDMMC
466 bool "Altera SDMMC FIFO ECC"
467 depends on EDAC_ALTERA=y && MMC_DW
468 help
469 Support for error detection and correction on the
470 Altera SDMMC FIFO Memory for Altera SoCs.
471
472config EDAC_SIFIVE
473 bool "Sifive platform EDAC driver"
474 depends on EDAC=y && SIFIVE_CCACHE
475 help
476 Support for error detection and correction on the SiFive SoCs.
477
478config EDAC_ARMADA_XP
479 bool "Marvell Armada XP DDR and L2 Cache ECC"
480 depends on MACH_MVEBU_V7
481 help
482 Support for error correction and detection on the Marvell Aramada XP
483 DDR RAM and L2 cache controllers.
484
485config EDAC_SYNOPSYS
486 tristate "Synopsys DDR Memory Controller"
487 depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_INTEL_SOCFPGA || ARCH_MXC
488 help
489 Support for error detection and correction on the Synopsys DDR
490 memory controller.
491
492config EDAC_XGENE
493 tristate "APM X-Gene SoC"
494 depends on (ARM64 || COMPILE_TEST)
495 help
496 Support for error detection and correction on the
497 APM X-Gene family of SOCs.
498
499config EDAC_TI
500 tristate "Texas Instruments DDR3 ECC Controller"
501 depends on ARCH_KEYSTONE || SOC_DRA7XX
502 help
503 Support for error detection and correction on the TI SoCs.
504
505config EDAC_QCOM
506 tristate "QCOM EDAC Controller"
507 depends on ARCH_QCOM && QCOM_LLCC
508 help
509 Support for error detection and correction on the
510 Qualcomm Technologies, Inc. SoCs.
511
512 This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs).
513 As of now, it supports error reporting for Last Level Cache Controller (LLCC)
514 of Tag RAM and Data RAM.
515
516 For debugging issues having to do with stability and overall system
517 health, you should probably say 'Y' here.
518
519config EDAC_ASPEED
520 tristate "Aspeed AST BMC SoC"
521 depends on ARCH_ASPEED
522 help
523 Support for error detection and correction on the Aspeed AST BMC SoC.
524
525 First, ECC must be configured in the bootloader. Then, this driver
526 will expose error counters via the EDAC kernel framework.
527
528config EDAC_BLUEFIELD
529 tristate "Mellanox BlueField Memory ECC"
530 depends on ARM64 && ((MELLANOX_PLATFORM && ACPI) || COMPILE_TEST)
531 help
532 Support for error detection and correction on the
533 Mellanox BlueField SoCs.
534
535config EDAC_DMC520
536 tristate "ARM DMC-520 ECC"
537 depends on ARM64
538 help
539 Support for error detection and correction on the
540 SoCs with ARM DMC-520 DRAM controller.
541
542config EDAC_ZYNQMP
543 tristate "Xilinx ZynqMP OCM Controller"
544 depends on ARCH_ZYNQMP || COMPILE_TEST
545 help
546 This driver supports error detection and correction for the
547 Xilinx ZynqMP OCM (On Chip Memory) controller. It can also be
548 built as a module. In that case it will be called zynqmp_edac.
549
550config EDAC_NPCM
551 tristate "Nuvoton NPCM DDR Memory Controller"
552 depends on (ARCH_NPCM || COMPILE_TEST)
553 help
554 Support for error detection and correction on the Nuvoton NPCM DDR
555 memory controller.
556
557 The memory controller supports single bit error correction, double bit
558 error detection (in-line ECC in which a section 1/8th of the memory
559 device used to store data is used for ECC storage).
560
561config EDAC_VERSAL
562 tristate "Xilinx Versal DDR Memory Controller"
563 depends on ARCH_ZYNQMP || COMPILE_TEST
564 help
565 Support for error detection and correction on the Xilinx Versal DDR
566 memory controller.
567
568 Report both single bit errors (CE) and double bit errors (UE).
569 Support injecting both correctable and uncorrectable errors
570 for debugging purposes.
571
572config EDAC_LOONGSON
573 tristate "Loongson Memory Controller"
574 depends on LOONGARCH && ACPI
575 help
576 Support for error detection and correction on the Loongson
577 family memory controller. This driver reports single bit
578 errors (CE) only. Loongson-3A5000/3C5000/3D5000/3A6000/3C6000
579 are compatible.
580
581config EDAC_CORTEX_A72
582 tristate "ARM Cortex A72"
583 depends on ARM64
584 help
585 Support for L1/L2 cache error detection for ARM Cortex A72 processor.
586 The detected and reported errors are from reading CPU/L2 memory error
587 syndrome registers.
588
589config EDAC_VERSALNET
590 tristate "AMD VersalNET DDR Controller"
591 depends on CDX_CONTROLLER && ARCH_ZYNQMP
592 help
593 Support for single bit error correction, double bit error detection
594 and other system errors from various IP subsystems like RPU, NOCs,
595 HNICX, PL on the AMD Versal NET DDR memory controller.
596
597config EDAC_DUMMY
598 tristate "Dummy EDAC driver"
599 default n
600 help
601 A dummy EDAC driver is useful for testing purposes in a VM when one
602 doesn't have all the hardware needed to test aspects of the EDAC
603 subsystem code.
604
605 You definitely wanna say N here.
606endif # EDAC