| 1 |
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| 2 | |
| 3 | * Chip register definitions for PCILynx chipset. Based on pcilynx.h
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| 4 | * from the Linux 1394 drivers, but modified a bit so the names here
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| 5 | * match the specification exactly (even though they have weird names,
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| 6 | * like xxx_OVER_FLOW, or arbitrary abbreviations like SNTRJ for "sent
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| 7 | * reject" etc.)
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| 8 |
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| 9 |
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| 10 | #define PCILYNX_MAX_REGISTER 0xfff
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| 11 | #define PCILYNX_MAX_MEMORY 0xffff
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| 12 |
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| 13 | #define PCI_LATENCY_CACHELINE 0x0c
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| 14 |
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| 15 | #define MISC_CONTROL 0x40
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| 16 | #define MISC_CONTROL_SWRESET (1<<0)
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| 17 |
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| 18 | #define SERIAL_EEPROM_CONTROL 0x44
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| 19 |
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| 20 | #define PCI_INT_STATUS 0x48
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| 21 | #define PCI_INT_ENABLE 0x4c
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| 22 |
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| 23 | #define PCI_INT_INT_PEND (1<<31)
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| 24 | #define PCI_INT_FRC_INT (1<<30)
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| 25 | #define PCI_INT_SLV_ADR_PERR (1<<28)
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| 26 | #define PCI_INT_SLV_DAT_PERR (1<<27)
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| 27 | #define PCI_INT_MST_DAT_PERR (1<<26)
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| 28 | #define PCI_INT_MST_DEV_TO (1<<25)
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| 29 | #define PCI_INT_INT_SLV_TO (1<<23)
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| 30 | #define PCI_INT_AUX_TO (1<<18)
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| 31 | #define PCI_INT_AUX_INT (1<<17)
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| 32 | #define PCI_INT_P1394_INT (1<<16)
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| 33 | #define PCI_INT_DMA4_PCL (1<<9)
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| 34 | #define PCI_INT_DMA4_HLT (1<<8)
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| 35 | #define PCI_INT_DMA3_PCL (1<<7)
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| 36 | #define PCI_INT_DMA3_HLT (1<<6)
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| 37 | #define PCI_INT_DMA2_PCL (1<<5)
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| 38 | #define PCI_INT_DMA2_HLT (1<<4)
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| 39 | #define PCI_INT_DMA1_PCL (1<<3)
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| 40 | #define PCI_INT_DMA1_HLT (1<<2)
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| 41 | #define PCI_INT_DMA0_PCL (1<<1)
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| 42 | #define PCI_INT_DMA0_HLT (1<<0)
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| 43 |
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| 44 | #define PCI_INT_DMA_ALL 0x3ff
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| 45 |
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| 46 | #define PCI_INT_DMA_HLT(chan) (1 << (chan * 2))
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| 47 | #define PCI_INT_DMA_PCL(chan) (1 << (chan * 2 + 1))
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| 48 |
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| 49 | #define LBUS_ADDR 0xb4
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| 50 | #define LBUS_ADDR_SEL_RAM (0x0<<16)
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| 51 | #define LBUS_ADDR_SEL_ROM (0x1<<16)
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| 52 | #define LBUS_ADDR_SEL_AUX (0x2<<16)
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| 53 | #define LBUS_ADDR_SEL_ZV (0x3<<16)
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| 54 |
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| 55 | #define GPIO_CTRL_A 0xb8
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| 56 | #define GPIO_CTRL_B 0xbc
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| 57 | #define GPIO_DATA_BASE 0xc0
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| 58 |
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| 59 | #define DMA_BREG(base, chan) (base + chan * 0x20)
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| 60 | #define DMA_SREG(base, chan) (base + chan * 0x10)
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| 61 |
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| 62 | #define PCL_NEXT_INVALID (1<<0)
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| 63 |
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| 64 |
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| 65 | #define PCL_CMD_RCV (0x1<<24)
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| 66 | #define PCL_CMD_RCV_AND_UPDATE (0xa<<24)
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| 67 | #define PCL_CMD_XMT (0x2<<24)
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| 68 | #define PCL_CMD_UNFXMT (0xc<<24)
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| 69 | #define PCL_CMD_PCI_TO_LBUS (0x8<<24)
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| 70 | #define PCL_CMD_LBUS_TO_PCI (0x9<<24)
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| 71 |
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| 72 |
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| 73 | #define PCL_CMD_NOP (0x0<<24)
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| 74 | #define PCL_CMD_LOAD (0x3<<24)
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| 75 | #define PCL_CMD_STOREQ (0x4<<24)
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| 76 | #define PCL_CMD_STORED (0xb<<24)
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| 77 | #define PCL_CMD_STORE0 (0x5<<24)
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| 78 | #define PCL_CMD_STORE1 (0x6<<24)
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| 79 | #define PCL_CMD_COMPARE (0xe<<24)
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| 80 | #define PCL_CMD_SWAP_COMPARE (0xf<<24)
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| 81 | #define PCL_CMD_ADD (0xd<<24)
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| 82 | #define PCL_CMD_BRANCH (0x7<<24)
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| 83 |
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| 84 |
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| 85 | #define PCL_COND_DMARDY_SET (0x1<<20)
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| 86 | #define PCL_COND_DMARDY_CLEAR (0x2<<20)
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| 87 |
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| 88 | #define PCL_GEN_INTR (1<<19)
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| 89 | #define PCL_LAST_BUFF (1<<18)
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| 90 | #define PCL_LAST_CMD (PCL_LAST_BUFF)
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| 91 | #define PCL_WAITSTAT (1<<17)
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| 92 | #define PCL_BIGENDIAN (1<<16)
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| 93 | #define PCL_ISOMODE (1<<12)
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| 94 |
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| 95 | #define DMA0_PREV_PCL 0x100
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| 96 | #define DMA1_PREV_PCL 0x120
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| 97 | #define DMA2_PREV_PCL 0x140
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| 98 | #define DMA3_PREV_PCL 0x160
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| 99 | #define DMA4_PREV_PCL 0x180
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| 100 | #define DMA_PREV_PCL(chan) (DMA_BREG(DMA0_PREV_PCL, chan))
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| 101 |
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| 102 | #define DMA0_CURRENT_PCL 0x104
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| 103 | #define DMA1_CURRENT_PCL 0x124
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| 104 | #define DMA2_CURRENT_PCL 0x144
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| 105 | #define DMA3_CURRENT_PCL 0x164
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| 106 | #define DMA4_CURRENT_PCL 0x184
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| 107 | #define DMA_CURRENT_PCL(chan) (DMA_BREG(DMA0_CURRENT_PCL, chan))
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| 108 |
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| 109 | #define DMA0_CHAN_STAT 0x10c
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| 110 | #define DMA1_CHAN_STAT 0x12c
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| 111 | #define DMA2_CHAN_STAT 0x14c
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| 112 | #define DMA3_CHAN_STAT 0x16c
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| 113 | #define DMA4_CHAN_STAT 0x18c
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| 114 | #define DMA_CHAN_STAT(chan) (DMA_BREG(DMA0_CHAN_STAT, chan))
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| 115 |
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| 116 | #define DMA_CHAN_STAT_SELFID (1<<31)
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| 117 | #define DMA_CHAN_STAT_ISOPKT (1<<30)
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| 118 | #define DMA_CHAN_STAT_PCIERR (1<<29)
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| 119 | #define DMA_CHAN_STAT_PKTERR (1<<28)
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| 120 | #define DMA_CHAN_STAT_PKTCMPL (1<<27)
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| 121 | #define DMA_CHAN_STAT_SPECIALACK (1<<14)
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| 122 |
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| 123 | #define DMA0_CHAN_CTRL 0x110
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| 124 | #define DMA1_CHAN_CTRL 0x130
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| 125 | #define DMA2_CHAN_CTRL 0x150
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| 126 | #define DMA3_CHAN_CTRL 0x170
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| 127 | #define DMA4_CHAN_CTRL 0x190
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| 128 | #define DMA_CHAN_CTRL(chan) (DMA_BREG(DMA0_CHAN_CTRL, chan))
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| 129 |
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| 130 | #define DMA_CHAN_CTRL_ENABLE (1<<31)
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| 131 | #define DMA_CHAN_CTRL_BUSY (1<<30)
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| 132 | #define DMA_CHAN_CTRL_LINK (1<<29)
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| 133 |
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| 134 | #define DMA0_READY 0x114
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| 135 | #define DMA1_READY 0x134
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| 136 | #define DMA2_READY 0x154
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| 137 | #define DMA3_READY 0x174
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| 138 | #define DMA4_READY 0x194
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| 139 | #define DMA_READY(chan) (DMA_BREG(DMA0_READY, chan))
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| 140 |
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| 141 | #define DMA_GLOBAL_REGISTER 0x908
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| 142 |
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| 143 | #define FIFO_SIZES 0xa00
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| 144 |
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| 145 | #define FIFO_CONTROL 0xa10
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| 146 | #define FIFO_CONTROL_GRF_FLUSH (1<<4)
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| 147 | #define FIFO_CONTROL_ITF_FLUSH (1<<3)
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| 148 | #define FIFO_CONTROL_ATF_FLUSH (1<<2)
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| 149 |
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| 150 | #define FIFO_XMIT_THRESHOLD 0xa14
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| 151 |
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| 152 | #define DMA0_WORD0_CMP_VALUE 0xb00
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| 153 | #define DMA1_WORD0_CMP_VALUE 0xb10
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| 154 | #define DMA2_WORD0_CMP_VALUE 0xb20
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| 155 | #define DMA3_WORD0_CMP_VALUE 0xb30
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| 156 | #define DMA4_WORD0_CMP_VALUE 0xb40
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| 157 | #define DMA_WORD0_CMP_VALUE(chan) (DMA_SREG(DMA0_WORD0_CMP_VALUE, chan))
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| 158 |
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| 159 | #define DMA0_WORD0_CMP_ENABLE 0xb04
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| 160 | #define DMA1_WORD0_CMP_ENABLE 0xb14
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| 161 | #define DMA2_WORD0_CMP_ENABLE 0xb24
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| 162 | #define DMA3_WORD0_CMP_ENABLE 0xb34
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| 163 | #define DMA4_WORD0_CMP_ENABLE 0xb44
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| 164 | #define DMA_WORD0_CMP_ENABLE(chan) (DMA_SREG(DMA0_WORD0_CMP_ENABLE, chan))
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| 165 |
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| 166 | #define DMA0_WORD1_CMP_VALUE 0xb08
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| 167 | #define DMA1_WORD1_CMP_VALUE 0xb18
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| 168 | #define DMA2_WORD1_CMP_VALUE 0xb28
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| 169 | #define DMA3_WORD1_CMP_VALUE 0xb38
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| 170 | #define DMA4_WORD1_CMP_VALUE 0xb48
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| 171 | #define DMA_WORD1_CMP_VALUE(chan) (DMA_SREG(DMA0_WORD1_CMP_VALUE, chan))
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| 172 |
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| 173 | #define DMA0_WORD1_CMP_ENABLE 0xb0c
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| 174 | #define DMA1_WORD1_CMP_ENABLE 0xb1c
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| 175 | #define DMA2_WORD1_CMP_ENABLE 0xb2c
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| 176 | #define DMA3_WORD1_CMP_ENABLE 0xb3c
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| 177 | #define DMA4_WORD1_CMP_ENABLE 0xb4c
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| 178 | #define DMA_WORD1_CMP_ENABLE(chan) (DMA_SREG(DMA0_WORD1_CMP_ENABLE, chan))
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| 179 |
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| 180 | #define DMA_WORD1_CMP_MATCH_OTHERBUS (1<<15)
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| 181 | #define DMA_WORD1_CMP_MATCH_BROADCAST (1<<14)
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| 182 | #define DMA_WORD1_CMP_MATCH_BUS_BCAST (1<<13)
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| 183 | #define DMA_WORD1_CMP_MATCH_LOCAL_NODE (1<<12)
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| 184 | #define DMA_WORD1_CMP_MATCH_EXACT (1<<11)
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| 185 | #define DMA_WORD1_CMP_ENABLE_SELF_ID (1<<10)
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| 186 | #define DMA_WORD1_CMP_ENABLE_MASTER (1<<8)
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| 187 |
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| 188 | #define LINK_ID 0xf00
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| 189 | #define LINK_ID_BUS(id) (id<<22)
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| 190 | #define LINK_ID_NODE(id) (id<<16)
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| 191 |
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| 192 | #define LINK_CONTROL 0xf04
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| 193 | #define LINK_CONTROL_BUSY (1<<29)
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| 194 | #define LINK_CONTROL_TX_ISO_EN (1<<26)
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| 195 | #define LINK_CONTROL_RX_ISO_EN (1<<25)
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| 196 | #define LINK_CONTROL_TX_ASYNC_EN (1<<24)
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| 197 | #define LINK_CONTROL_RX_ASYNC_EN (1<<23)
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| 198 | #define LINK_CONTROL_RESET_TX (1<<21)
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| 199 | #define LINK_CONTROL_RESET_RX (1<<20)
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| 200 | #define LINK_CONTROL_CYCMASTER (1<<11)
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| 201 | #define LINK_CONTROL_CYCSOURCE (1<<10)
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| 202 | #define LINK_CONTROL_CYCTIMEREN (1<<9)
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| 203 | #define LINK_CONTROL_RCV_CMP_VALID (1<<7)
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| 204 | #define LINK_CONTROL_SNOOP_ENABLE (1<<6)
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| 205 |
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| 206 | #define CYCLE_TIMER 0xf08
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| 207 |
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| 208 | #define LINK_PHY 0xf0c
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| 209 | #define LINK_PHY_READ (1<<31)
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| 210 | #define LINK_PHY_WRITE (1<<30)
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| 211 | #define LINK_PHY_ADDR(addr) (addr<<24)
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| 212 | #define LINK_PHY_WDATA(data) (data<<16)
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| 213 | #define LINK_PHY_RADDR(addr) (addr<<8)
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| 214 |
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| 215 | #define LINK_INT_STATUS 0xf14
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| 216 | #define LINK_INT_ENABLE 0xf18
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| 217 | /* status and enable have identical bit numbers */
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| 218 | #define LINK_INT_LINK_INT (1<<31)
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| 219 | #define LINK_INT_PHY_TIME_OUT (1<<30)
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| 220 | #define LINK_INT_PHY_REG_RCVD (1<<29)
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| 221 | #define LINK_INT_PHY_BUSRESET (1<<28)
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| 222 | #define LINK_INT_TX_RDY (1<<26)
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| 223 | #define LINK_INT_RX_DATA_RDY (1<<25)
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| 224 | #define LINK_INT_IT_STUCK (1<<20)
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| 225 | #define LINK_INT_AT_STUCK (1<<19)
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| 226 | #define LINK_INT_SNTRJ (1<<17)
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| 227 | #define LINK_INT_HDR_ERR (1<<16)
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| 228 | #define LINK_INT_TC_ERR (1<<15)
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| 229 | #define LINK_INT_CYC_SEC (1<<11)
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| 230 | #define LINK_INT_CYC_STRT (1<<10)
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| 231 | #define LINK_INT_CYC_DONE (1<<9)
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| 232 | #define LINK_INT_CYC_PEND (1<<8)
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| 233 | #define LINK_INT_CYC_LOST (1<<7)
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| 234 | #define LINK_INT_CYC_ARB_FAILED (1<<6)
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| 235 | #define LINK_INT_GRF_OVER_FLOW (1<<5)
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| 236 | #define LINK_INT_ITF_UNDER_FLOW (1<<4)
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| 237 | #define LINK_INT_ATF_UNDER_FLOW (1<<3)
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| 238 | #define LINK_INT_IARB_FAILED (1<<0)
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