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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Driver Header File for FPGA Device Feature List (DFL) Support
4 *
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
6 *
7 * Authors:
8 * Kang Luwei <[email protected]>
9 * Zhang Yi <[email protected]>
10 * Wu Hao <[email protected]>
11 * Xiao Guangrong <[email protected]>
12 */
13
14#ifndef __FPGA_DFL_H
15#define __FPGA_DFL_H
16
17#include <linux/bitfield.h>
18#include <linux/cdev.h>
19#include <linux/delay.h>
20#include <linux/dfl.h>
21#include <linux/eventfd.h>
22#include <linux/fs.h>
23#include <linux/interrupt.h>
24#include <linux/iopoll.h>
25#include <linux/io-64-nonatomic-lo-hi.h>
26#include <linux/mod_devicetable.h>
27#include <linux/platform_device.h>
28#include <linux/slab.h>
29#include <linux/uuid.h>
30#include <linux/fpga/fpga-region.h>
31
32/* maximum supported number of ports */
33#define MAX_DFL_FPGA_PORT_NUM 4
34/* plus one for fme device */
35#define MAX_DFL_FEATURE_DEV_NUM (MAX_DFL_FPGA_PORT_NUM + 1)
36
37/* Reserved 0xfe for Header Group Register and 0xff for AFU */
38#define FEATURE_ID_FIU_HEADER 0xfe
39#define FEATURE_ID_AFU 0xff
40
41#define FME_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER
42#define FME_FEATURE_ID_THERMAL_MGMT 0x1
43#define FME_FEATURE_ID_POWER_MGMT 0x2
44#define FME_FEATURE_ID_GLOBAL_IPERF 0x3
45#define FME_FEATURE_ID_GLOBAL_ERR 0x4
46#define FME_FEATURE_ID_PR_MGMT 0x5
47#define FME_FEATURE_ID_HSSI 0x6
48#define FME_FEATURE_ID_GLOBAL_DPERF 0x7
49
50#define PORT_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER
51#define PORT_FEATURE_ID_AFU FEATURE_ID_AFU
52#define PORT_FEATURE_ID_ERROR 0x10
53#define PORT_FEATURE_ID_UMSG 0x11
54#define PORT_FEATURE_ID_UINT 0x12
55#define PORT_FEATURE_ID_STP 0x13
56
57/*
58 * Device Feature Header Register Set
59 *
60 * For FIUs, they all have DFH + GUID + NEXT_AFU as common header registers.
61 * For AFUs, they have DFH + GUID as common header registers.
62 * For private features, they only have DFH register as common header.
63 */
64#define DFH 0x0
65#define GUID_L 0x8
66#define GUID_H 0x10
67#define NEXT_AFU 0x18
68
69#define DFH_SIZE 0x8
70
71/* Device Feature Header Register Bitfield */
72#define DFH_ID GENMASK_ULL(11, 0) /* Feature ID */
73#define DFH_ID_FIU_FME 0
74#define DFH_ID_FIU_PORT 1
75#define DFH_REVISION GENMASK_ULL(15, 12) /* Feature revision */
76#define DFH_NEXT_HDR_OFST GENMASK_ULL(39, 16) /* Offset to next DFH */
77#define DFH_EOL BIT_ULL(40) /* End of list */
78#define DFH_VERSION GENMASK_ULL(59, 52) /* DFH version */
79#define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */
80#define DFH_TYPE_AFU 1
81#define DFH_TYPE_PRIVATE 3
82#define DFH_TYPE_FIU 4
83
84/*
85 * DFHv1 Register Offset definitions
86 * In DHFv1, DFH + GUID + CSR_START + CSR_SIZE_GROUP + PARAM_HDR + PARAM_DATA
87 * as common header registers
88 */
89#define DFHv1_CSR_ADDR 0x18 /* CSR Register start address */
90#define DFHv1_CSR_SIZE_GRP 0x20 /* Size of Reg Block and Group/tag */
91#define DFHv1_PARAM_HDR 0x28 /* Optional First Param header */
92
93/*
94 * CSR Rel Bit, 1'b0 = relative (offset from feature DFH start),
95 * 1'b1 = absolute (ARM or other non-PCIe use)
96 */
97#define DFHv1_CSR_ADDR_REL BIT_ULL(0)
98
99/* CSR Header Register Bit Definitions */
100#define DFHv1_CSR_ADDR_MASK GENMASK_ULL(63, 1) /* 63:1 of CSR address */
101
102/* CSR SIZE Goup Register Bit Definitions */
103#define DFHv1_CSR_SIZE_GRP_INSTANCE_ID GENMASK_ULL(15, 0) /* Enumeration instantiated IP */
104#define DFHv1_CSR_SIZE_GRP_GROUPING_ID GENMASK_ULL(30, 16) /* Group Features/interfaces */
105#define DFHv1_CSR_SIZE_GRP_HAS_PARAMS BIT_ULL(31) /* Presence of Parameters */
106#define DFHv1_CSR_SIZE_GRP_SIZE GENMASK_ULL(63, 32) /* Size of CSR Block in bytes */
107
108/* PARAM Header Register Bit Definitions */
109#define DFHv1_PARAM_HDR_ID GENMASK_ULL(15, 0) /* Id of this Param */
110#define DFHv1_PARAM_HDR_VER GENMASK_ULL(31, 16) /* Version Param */
111#define DFHv1_PARAM_HDR_NEXT_OFFSET GENMASK_ULL(63, 35) /* Offset of next Param */
112#define DFHv1_PARAM_HDR_NEXT_EOP BIT_ULL(32)
113#define DFHv1_PARAM_DATA 0x08 /* Offset of Param data from Param header */
114
115#define DFHv1_PARAM_ID_MSI_X 0x1
116#define DFHv1_PARAM_MSI_X_NUMV GENMASK_ULL(63, 32)
117#define DFHv1_PARAM_MSI_X_STARTV GENMASK_ULL(31, 0)
118
119/* Next AFU Register Bitfield */
120#define NEXT_AFU_NEXT_DFH_OFST GENMASK_ULL(23, 0) /* Offset to next AFU */
121
122/* FME Header Register Set */
123#define FME_HDR_DFH DFH
124#define FME_HDR_GUID_L GUID_L
125#define FME_HDR_GUID_H GUID_H
126#define FME_HDR_NEXT_AFU NEXT_AFU
127#define FME_HDR_CAP 0x30
128#define FME_HDR_PORT_OFST(n) (0x38 + ((n) * 0x8))
129#define FME_PORT_OFST_BAR_SKIP 7
130#define FME_HDR_BITSTREAM_ID 0x60
131#define FME_HDR_BITSTREAM_MD 0x68
132
133/* FME Fab Capability Register Bitfield */
134#define FME_CAP_FABRIC_VERID GENMASK_ULL(7, 0) /* Fabric version ID */
135#define FME_CAP_SOCKET_ID BIT_ULL(8) /* Socket ID */
136#define FME_CAP_PCIE0_LINK_AVL BIT_ULL(12) /* PCIE0 Link */
137#define FME_CAP_PCIE1_LINK_AVL BIT_ULL(13) /* PCIE1 Link */
138#define FME_CAP_COHR_LINK_AVL BIT_ULL(14) /* Coherent Link */
139#define FME_CAP_IOMMU_AVL BIT_ULL(16) /* IOMMU available */
140#define FME_CAP_NUM_PORTS GENMASK_ULL(19, 17) /* Number of ports */
141#define FME_CAP_ADDR_WIDTH GENMASK_ULL(29, 24) /* Address bus width */
142#define FME_CAP_CACHE_SIZE GENMASK_ULL(43, 32) /* cache size in KB */
143#define FME_CAP_CACHE_ASSOC GENMASK_ULL(47, 44) /* Associativity */
144
145/* FME Port Offset Register Bitfield */
146/* Offset to port device feature header */
147#define FME_PORT_OFST_DFH_OFST GENMASK_ULL(23, 0)
148/* PCI Bar ID for this port */
149#define FME_PORT_OFST_BAR_ID GENMASK_ULL(34, 32)
150/* AFU MMIO access permission. 1 - VF, 0 - PF. */
151#define FME_PORT_OFST_ACC_CTRL BIT_ULL(55)
152#define FME_PORT_OFST_ACC_PF 0
153#define FME_PORT_OFST_ACC_VF 1
154#define FME_PORT_OFST_IMP BIT_ULL(60)
155
156/* FME Error Capability Register */
157#define FME_ERROR_CAP 0x70
158
159/* FME Error Capability Register Bitfield */
160#define FME_ERROR_CAP_SUPP_INT BIT_ULL(0) /* Interrupt Support */
161#define FME_ERROR_CAP_INT_VECT GENMASK_ULL(12, 1) /* Interrupt vector */
162
163/* PORT Header Register Set */
164#define PORT_HDR_DFH DFH
165#define PORT_HDR_GUID_L GUID_L
166#define PORT_HDR_GUID_H GUID_H
167#define PORT_HDR_NEXT_AFU NEXT_AFU
168#define PORT_HDR_CAP 0x30
169#define PORT_HDR_CTRL 0x38
170#define PORT_HDR_STS 0x40
171#define PORT_HDR_USRCLK_CMD0 0x50
172#define PORT_HDR_USRCLK_CMD1 0x58
173#define PORT_HDR_USRCLK_STS0 0x60
174#define PORT_HDR_USRCLK_STS1 0x68
175
176/* Port Capability Register Bitfield */
177#define PORT_CAP_PORT_NUM GENMASK_ULL(1, 0) /* ID of this port */
178#define PORT_CAP_MMIO_SIZE GENMASK_ULL(23, 8) /* MMIO size in KB */
179#define PORT_CAP_SUPP_INT_NUM GENMASK_ULL(35, 32) /* Interrupts num */
180
181/* Port Control Register Bitfield */
182#define PORT_CTRL_SFTRST BIT_ULL(0) /* Port soft reset */
183/* Latency tolerance reporting. '1' >= 40us, '0' < 40us.*/
184#define PORT_CTRL_LATENCY BIT_ULL(2)
185#define PORT_CTRL_SFTRST_ACK BIT_ULL(4) /* HW ack for reset */
186
187/* Port Status Register Bitfield */
188#define PORT_STS_AP2_EVT BIT_ULL(13) /* AP2 event detected */
189#define PORT_STS_AP1_EVT BIT_ULL(12) /* AP1 event detected */
190#define PORT_STS_PWR_STATE GENMASK_ULL(11, 8) /* AFU power states */
191#define PORT_STS_PWR_STATE_NORM 0
192#define PORT_STS_PWR_STATE_AP1 1 /* 50% throttling */
193#define PORT_STS_PWR_STATE_AP2 2 /* 90% throttling */
194#define PORT_STS_PWR_STATE_AP6 6 /* 100% throttling */
195
196/* Port Error Capability Register */
197#define PORT_ERROR_CAP 0x38
198
199/* Port Error Capability Register Bitfield */
200#define PORT_ERROR_CAP_SUPP_INT BIT_ULL(0) /* Interrupt Support */
201#define PORT_ERROR_CAP_INT_VECT GENMASK_ULL(12, 1) /* Interrupt vector */
202
203/* Port Uint Capability Register */
204#define PORT_UINT_CAP 0x8
205
206/* Port Uint Capability Register Bitfield */
207#define PORT_UINT_CAP_INT_NUM GENMASK_ULL(11, 0) /* Interrupts num */
208#define PORT_UINT_CAP_FST_VECT GENMASK_ULL(23, 12) /* First Vector */
209
210struct dfl_feature_dev_data;
211
212/**
213 * struct dfl_fpga_port_ops - port ops
214 *
215 * @name: name of this port ops, to match with port platform device.
216 * @owner: pointer to the module which owns this port ops.
217 * @node: node to link port ops to global list.
218 * @get_id: get port id from hardware.
219 * @enable_set: enable/disable the port.
220 */
221struct dfl_fpga_port_ops {
222 const char *name;
223 struct module *owner;
224 struct list_head node;
225 int (*get_id)(struct dfl_feature_dev_data *fdata);
226 int (*enable_set)(struct dfl_feature_dev_data *fdata, bool enable);
227};
228
229void dfl_fpga_port_ops_add(struct dfl_fpga_port_ops *ops);
230void dfl_fpga_port_ops_del(struct dfl_fpga_port_ops *ops);
231struct dfl_fpga_port_ops *dfl_fpga_port_ops_get(struct dfl_feature_dev_data *fdata);
232void dfl_fpga_port_ops_put(struct dfl_fpga_port_ops *ops);
233int dfl_fpga_check_port_id(struct dfl_feature_dev_data *fdata, void *pport_id);
234
235/**
236 * struct dfl_feature_id - dfl private feature id
237 *
238 * @id: unique dfl private feature id.
239 */
240struct dfl_feature_id {
241 u16 id;
242};
243
244/**
245 * struct dfl_feature_driver - dfl private feature driver
246 *
247 * @id_table: id_table for dfl private features supported by this driver.
248 * @ops: ops of this dfl private feature driver.
249 */
250struct dfl_feature_driver {
251 const struct dfl_feature_id *id_table;
252 const struct dfl_feature_ops *ops;
253};
254
255/**
256 * struct dfl_feature_irq_ctx - dfl private feature interrupt context
257 *
258 * @irq: Linux IRQ number of this interrupt.
259 * @trigger: eventfd context to signal when interrupt happens.
260 * @name: irq name needed when requesting irq.
261 */
262struct dfl_feature_irq_ctx {
263 int irq;
264 struct eventfd_ctx *trigger;
265 char *name;
266};
267
268/**
269 * struct dfl_feature - sub feature of the feature devices
270 *
271 * @dev: ptr to pdev of the feature device which has the sub feature.
272 * @id: sub feature id.
273 * @revision: revision of this sub feature.
274 * @resource_index: each sub feature has one mmio resource for its registers.
275 * this index is used to find its mmio resource from the
276 * feature dev (platform device)'s resources.
277 * @ioaddr: mapped mmio resource address.
278 * @irq_ctx: interrupt context list.
279 * @nr_irqs: number of interrupt contexts.
280 * @ops: ops of this sub feature.
281 * @ddev: ptr to the dfl device of this sub feature.
282 * @priv: priv data of this feature.
283 * @dfh_version: version of the DFH
284 * @param_size: size of dfh parameters
285 * @params: point to memory copy of dfh parameters
286 */
287struct dfl_feature {
288 struct platform_device *dev;
289 u16 id;
290 u8 revision;
291 int resource_index;
292 void __iomem *ioaddr;
293 struct dfl_feature_irq_ctx *irq_ctx;
294 unsigned int nr_irqs;
295 const struct dfl_feature_ops *ops;
296 struct dfl_device *ddev;
297 void *priv;
298 u8 dfh_version;
299 unsigned int param_size;
300 void *params;
301};
302
303#define FEATURE_DEV_ID_UNUSED (-1)
304
305/**
306 * struct dfl_feature_dev_data - dfl enumeration data for dfl feature dev.
307 *
308 * @node: node to link the data structure to container device's port_dev_list.
309 * @lock: mutex to protect feature dev data.
310 * @dev: ptr to the feature's platform device linked with this structure.
311 * @type: type of DFL FIU for the feature dev. See enum dfl_id_type.
312 * @pdev_id: platform device id for the feature dev.
313 * @pdev_name: platform device name for the feature dev.
314 * @dfl_cdev: ptr to container device.
315 * @id: id used for the feature device.
316 * @disable_count: count for port disable.
317 * @excl_open: set on feature device exclusive open.
318 * @open_count: count for feature device open.
319 * @num: number for sub features.
320 * @private: ptr to feature dev private data.
321 * @features: sub features for the feature dev.
322 * @resource_num: number of resources for the feature dev.
323 * @resources: resources for the feature dev.
324 */
325struct dfl_feature_dev_data {
326 struct list_head node;
327 struct mutex lock;
328 struct platform_device *dev;
329 enum dfl_id_type type;
330 int pdev_id;
331 const char *pdev_name;
332 struct dfl_fpga_cdev *dfl_cdev;
333 int id;
334 unsigned int disable_count;
335 bool excl_open;
336 int open_count;
337 void *private;
338 int num;
339 struct dfl_feature *features;
340 int resource_num;
341 struct resource *resources;
342};
343
344/**
345 * struct dfl_feature_platform_data - platform data for feature devices
346 *
347 * @cdev: cdev of feature dev.
348 * @fdata: dfl enumeration data for the dfl feature device.
349 */
350struct dfl_feature_platform_data {
351 struct cdev cdev;
352 struct dfl_feature_dev_data *fdata;
353};
354
355static inline
356int dfl_feature_dev_use_begin(struct dfl_feature_dev_data *fdata,
357 bool excl)
358{
359 if (fdata->excl_open)
360 return -EBUSY;
361
362 if (excl) {
363 if (fdata->open_count)
364 return -EBUSY;
365
366 fdata->excl_open = true;
367 }
368 fdata->open_count++;
369
370 return 0;
371}
372
373static inline
374void dfl_feature_dev_use_end(struct dfl_feature_dev_data *fdata)
375{
376 fdata->excl_open = false;
377
378 if (WARN_ON(fdata->open_count <= 0))
379 return;
380
381 fdata->open_count--;
382}
383
384static inline
385int dfl_feature_dev_use_count(struct dfl_feature_dev_data *fdata)
386{
387 return fdata->open_count;
388}
389
390static inline
391void dfl_fpga_fdata_set_private(struct dfl_feature_dev_data *fdata,
392 void *private)
393{
394 fdata->private = private;
395}
396
397static inline
398void *dfl_fpga_fdata_get_private(struct dfl_feature_dev_data *fdata)
399{
400 return fdata->private;
401}
402
403struct dfl_feature_ops {
404 int (*init)(struct platform_device *pdev, struct dfl_feature *feature);
405 void (*uinit)(struct platform_device *pdev,
406 struct dfl_feature *feature);
407 long (*ioctl)(struct platform_device *pdev, struct dfl_feature *feature,
408 unsigned int cmd, unsigned long arg);
409};
410
411#define DFL_FPGA_FEATURE_DEV_FME "dfl-fme"
412#define DFL_FPGA_FEATURE_DEV_PORT "dfl-port"
413
414void dfl_fpga_dev_feature_uinit(struct platform_device *pdev);
415int dfl_fpga_dev_feature_init(struct platform_device *pdev,
416 struct dfl_feature_driver *feature_drvs);
417
418int dfl_fpga_dev_ops_register(struct platform_device *pdev,
419 const struct file_operations *fops,
420 struct module *owner);
421void dfl_fpga_dev_ops_unregister(struct platform_device *pdev);
422
423static inline struct dfl_feature_dev_data *
424dfl_fpga_inode_to_feature_dev_data(struct inode *inode)
425{
426 struct dfl_feature_platform_data *pdata;
427
428 pdata = container_of(inode->i_cdev, struct dfl_feature_platform_data,
429 cdev);
430 return pdata->fdata;
431}
432
433#define dfl_fpga_dev_for_each_feature(fdata, feature) \
434 for ((feature) = (fdata)->features; \
435 (feature) < (fdata)->features + (fdata)->num; (feature)++)
436
437static inline struct dfl_feature *
438dfl_get_feature_by_id(struct dfl_feature_dev_data *fdata, u16 id)
439{
440 struct dfl_feature *feature;
441
442 dfl_fpga_dev_for_each_feature(fdata, feature)
443 if (feature->id == id)
444 return feature;
445
446 return NULL;
447}
448
449static inline void __iomem *
450dfl_get_feature_ioaddr_by_id(struct dfl_feature_dev_data *fdata, u16 id)
451{
452 struct dfl_feature *feature = dfl_get_feature_by_id(fdata, id);
453
454 if (feature && feature->ioaddr)
455 return feature->ioaddr;
456
457 WARN_ON(1);
458 return NULL;
459}
460
461static inline struct dfl_feature_dev_data *
462to_dfl_feature_dev_data(struct device *dev)
463{
464 struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
465
466 return pdata->fdata;
467}
468
469static inline
470struct device *dfl_fpga_fdata_to_parent(struct dfl_feature_dev_data *fdata)
471{
472 return fdata->dev->dev.parent->parent;
473}
474
475static inline bool dfl_feature_is_fme(void __iomem *base)
476{
477 u64 v = readq(base + DFH);
478
479 return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) &&
480 (FIELD_GET(DFH_ID, v) == DFH_ID_FIU_FME);
481}
482
483static inline bool dfl_feature_is_port(void __iomem *base)
484{
485 u64 v = readq(base + DFH);
486
487 return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) &&
488 (FIELD_GET(DFH_ID, v) == DFH_ID_FIU_PORT);
489}
490
491static inline u8 dfl_feature_revision(void __iomem *base)
492{
493 return (u8)FIELD_GET(DFH_REVISION, readq(base + DFH));
494}
495
496/**
497 * struct dfl_fpga_enum_info - DFL FPGA enumeration information
498 *
499 * @dev: parent device.
500 * @dfls: list of device feature lists.
501 * @nr_irqs: number of irqs for all feature devices.
502 * @irq_table: Linux IRQ numbers for all irqs, indexed by hw irq numbers.
503 */
504struct dfl_fpga_enum_info {
505 struct device *dev;
506 struct list_head dfls;
507 unsigned int nr_irqs;
508 int *irq_table;
509};
510
511/**
512 * struct dfl_fpga_enum_dfl - DFL FPGA enumeration device feature list info
513 *
514 * @start: base address of this device feature list.
515 * @len: size of this device feature list.
516 * @node: node in list of device feature lists.
517 */
518struct dfl_fpga_enum_dfl {
519 resource_size_t start;
520 resource_size_t len;
521 struct list_head node;
522};
523
524struct dfl_fpga_enum_info *dfl_fpga_enum_info_alloc(struct device *dev);
525int dfl_fpga_enum_info_add_dfl(struct dfl_fpga_enum_info *info,
526 resource_size_t start, resource_size_t len);
527int dfl_fpga_enum_info_add_irq(struct dfl_fpga_enum_info *info,
528 unsigned int nr_irqs, int *irq_table);
529void dfl_fpga_enum_info_free(struct dfl_fpga_enum_info *info);
530
531/**
532 * struct dfl_fpga_cdev - container device of DFL based FPGA
533 *
534 * @parent: parent device of this container device.
535 * @region: base fpga region.
536 * @fme_dev: FME feature device under this container device.
537 * @lock: mutex lock to protect the port device list.
538 * @port_dev_list: list of all port feature devices under this container device.
539 * @released_port_num: released port number under this container device.
540 */
541struct dfl_fpga_cdev {
542 struct device *parent;
543 struct fpga_region *region;
544 struct device *fme_dev;
545 struct mutex lock;
546 struct list_head port_dev_list;
547 int released_port_num;
548};
549
550struct dfl_fpga_cdev *
551dfl_fpga_feature_devs_enumerate(struct dfl_fpga_enum_info *info);
552void dfl_fpga_feature_devs_remove(struct dfl_fpga_cdev *cdev);
553
554struct dfl_feature_dev_data *
555__dfl_fpga_cdev_find_port_data(struct dfl_fpga_cdev *cdev, void *data,
556 int (*match)(struct dfl_feature_dev_data *, void *));
557
558static inline struct dfl_feature_dev_data *
559dfl_fpga_cdev_find_port_data(struct dfl_fpga_cdev *cdev, void *data,
560 int (*match)(struct dfl_feature_dev_data *, void *))
561{
562 struct dfl_feature_dev_data *fdata;
563
564 mutex_lock(&cdev->lock);
565 fdata = __dfl_fpga_cdev_find_port_data(cdev, data, match);
566 mutex_unlock(&cdev->lock);
567
568 return fdata;
569}
570
571int dfl_fpga_cdev_release_port(struct dfl_fpga_cdev *cdev, int port_id);
572int dfl_fpga_cdev_assign_port(struct dfl_fpga_cdev *cdev, int port_id);
573void dfl_fpga_cdev_config_ports_pf(struct dfl_fpga_cdev *cdev);
574int dfl_fpga_cdev_config_ports_vf(struct dfl_fpga_cdev *cdev, int num_vf);
575int dfl_fpga_set_irq_triggers(struct dfl_feature *feature, unsigned int start,
576 unsigned int count, int32_t *fds);
577long dfl_feature_ioctl_get_num_irqs(struct platform_device *pdev,
578 struct dfl_feature *feature,
579 unsigned long arg);
580long dfl_feature_ioctl_set_irq(struct platform_device *pdev,
581 struct dfl_feature *feature,
582 unsigned long arg);
583
584#endif /* __FPGA_DFL_H */