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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Atheros AR71XX/AR724X/AR913X GPIO API support
4 *
5 * Copyright (C) 2015 Alban Bedel <[email protected]>
6 * Copyright (C) 2010-2011 Jaiganesh Narayanan <[email protected]>
7 * Copyright (C) 2008-2011 Gabor Juhos <[email protected]>
8 * Copyright (C) 2008 Imre Kaloz <[email protected]>
9 */
10
11#include <linux/device.h>
12#include <linux/gpio/driver.h>
13#include <linux/gpio/generic.h>
14#include <linux/gpio/machine.h> /* For WLAN GPIOs */
15#include <linux/interrupt.h>
16#include <linux/irq.h>
17#include <linux/module.h>
18#include <linux/platform_device.h>
19
20#define AR71XX_GPIO_REG_OE 0x00
21#define AR71XX_GPIO_REG_IN 0x04
22#define AR71XX_GPIO_REG_SET 0x0c
23#define AR71XX_GPIO_REG_CLEAR 0x10
24
25#define AR71XX_GPIO_REG_INT_ENABLE 0x14
26#define AR71XX_GPIO_REG_INT_TYPE 0x18
27#define AR71XX_GPIO_REG_INT_POLARITY 0x1c
28#define AR71XX_GPIO_REG_INT_PENDING 0x20
29#define AR71XX_GPIO_REG_INT_MASK 0x24
30
31struct ath79_gpio_ctrl {
32 struct gpio_generic_chip chip;
33 void __iomem *base;
34 unsigned long both_edges;
35};
36
37static struct ath79_gpio_ctrl *irq_data_to_ath79_gpio(struct irq_data *data)
38{
39 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
40 struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
41
42 return container_of(gen_gc, struct ath79_gpio_ctrl, chip);
43}
44
45static u32 ath79_gpio_read(struct ath79_gpio_ctrl *ctrl, unsigned reg)
46{
47 return readl(ctrl->base + reg);
48}
49
50static void ath79_gpio_write(struct ath79_gpio_ctrl *ctrl,
51 unsigned reg, u32 val)
52{
53 writel(val, ctrl->base + reg);
54}
55
56static bool ath79_gpio_update_bits(
57 struct ath79_gpio_ctrl *ctrl, unsigned reg, u32 mask, u32 bits)
58{
59 u32 old_val, new_val;
60
61 old_val = ath79_gpio_read(ctrl, reg);
62 new_val = (old_val & ~mask) | (bits & mask);
63
64 if (new_val != old_val)
65 ath79_gpio_write(ctrl, reg, new_val);
66
67 return new_val != old_val;
68}
69
70static void ath79_gpio_irq_unmask(struct irq_data *data)
71{
72 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
73 u32 mask = BIT(irqd_to_hwirq(data));
74
75 gpiochip_enable_irq(&ctrl->chip.gc, irqd_to_hwirq(data));
76
77 guard(gpio_generic_lock_irqsave)(&ctrl->chip);
78
79 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);
80}
81
82static void ath79_gpio_irq_mask(struct irq_data *data)
83{
84 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
85 u32 mask = BIT(irqd_to_hwirq(data));
86
87 scoped_guard(gpio_generic_lock_irqsave, &ctrl->chip)
88 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);
89
90 gpiochip_disable_irq(&ctrl->chip.gc, irqd_to_hwirq(data));
91}
92
93static void ath79_gpio_irq_enable(struct irq_data *data)
94{
95 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
96 u32 mask = BIT(irqd_to_hwirq(data));
97
98 guard(gpio_generic_lock_irqsave)(&ctrl->chip);
99 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);
100 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);
101}
102
103static void ath79_gpio_irq_disable(struct irq_data *data)
104{
105 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
106 u32 mask = BIT(irqd_to_hwirq(data));
107
108 guard(gpio_generic_lock_irqsave)(&ctrl->chip);
109 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);
110 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);
111}
112
113static int ath79_gpio_irq_set_type(struct irq_data *data,
114 unsigned int flow_type)
115{
116 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
117 u32 mask = BIT(irqd_to_hwirq(data));
118 u32 type = 0, polarity = 0;
119 bool disabled;
120
121 switch (flow_type) {
122 case IRQ_TYPE_EDGE_RISING:
123 polarity |= mask;
124 fallthrough;
125 case IRQ_TYPE_EDGE_FALLING:
126 case IRQ_TYPE_EDGE_BOTH:
127 break;
128
129 case IRQ_TYPE_LEVEL_HIGH:
130 polarity |= mask;
131 fallthrough;
132 case IRQ_TYPE_LEVEL_LOW:
133 type |= mask;
134 break;
135
136 default:
137 return -EINVAL;
138 }
139
140 guard(gpio_generic_lock_irqsave)(&ctrl->chip);
141
142 if (flow_type == IRQ_TYPE_EDGE_BOTH) {
143 ctrl->both_edges |= mask;
144 polarity = ~ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);
145 } else {
146 ctrl->both_edges &= ~mask;
147 }
148
149 /* As the IRQ configuration can't be loaded atomically we
150 * have to disable the interrupt while the configuration state
151 * is invalid.
152 */
153 disabled = ath79_gpio_update_bits(
154 ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);
155
156 ath79_gpio_update_bits(
157 ctrl, AR71XX_GPIO_REG_INT_TYPE, mask, type);
158 ath79_gpio_update_bits(
159 ctrl, AR71XX_GPIO_REG_INT_POLARITY, mask, polarity);
160
161 if (disabled)
162 ath79_gpio_update_bits(
163 ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);
164
165 return 0;
166}
167
168static const struct irq_chip ath79_gpio_irqchip = {
169 .name = "gpio-ath79",
170 .irq_enable = ath79_gpio_irq_enable,
171 .irq_disable = ath79_gpio_irq_disable,
172 .irq_mask = ath79_gpio_irq_mask,
173 .irq_unmask = ath79_gpio_irq_unmask,
174 .irq_set_type = ath79_gpio_irq_set_type,
175 .flags = IRQCHIP_IMMUTABLE,
176 GPIOCHIP_IRQ_RESOURCE_HELPERS,
177};
178
179static void ath79_gpio_irq_handler(struct irq_desc *desc)
180{
181 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
182 struct irq_chip *irqchip = irq_desc_get_chip(desc);
183 struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
184 struct ath79_gpio_ctrl *ctrl =
185 container_of(gen_gc, struct ath79_gpio_ctrl, chip);
186 unsigned long pending;
187 u32 both_edges, state;
188 int irq;
189
190 chained_irq_enter(irqchip, desc);
191
192 scoped_guard(gpio_generic_lock_irqsave, &ctrl->chip) {
193 pending = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_INT_PENDING);
194
195 /* Update the polarity of the both edges irqs */
196 both_edges = ctrl->both_edges & pending;
197 if (both_edges) {
198 state = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);
199 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_POLARITY,
200 both_edges, ~state);
201 }
202 }
203
204 for_each_set_bit(irq, &pending, gc->ngpio)
205 generic_handle_domain_irq(gc->irq.domain, irq);
206
207 chained_irq_exit(irqchip, desc);
208}
209
210static const struct of_device_id ath79_gpio_of_match[] = {
211 { .compatible = "qca,ar7100-gpio" },
212 { .compatible = "qca,ar9340-gpio" },
213 {},
214};
215MODULE_DEVICE_TABLE(of, ath79_gpio_of_match);
216
217#if IS_ENABLED(CONFIG_ATH9K_AHB)
218/*
219 * This registers all of the ath79k GPIOs as descriptors to be picked
220 * directly from the ATH79K wifi driver if the two are jitted together
221 * in the same SoC.
222 */
223#define ATH79K_WIFI_DESCS 32
224static int ath79_gpio_register_wifi_descriptors(struct device *dev,
225 const char *label)
226{
227 struct gpiod_lookup_table *lookup;
228 int i;
229
230 /* Create a gpiod lookup using gpiochip-local offsets + 1 for NULL */
231 lookup = devm_kzalloc(dev,
232 struct_size(lookup, table, ATH79K_WIFI_DESCS + 1),
233 GFP_KERNEL);
234 if (!lookup)
235 return -ENOMEM;
236
237 /*
238 * Ugly system-wide lookup for the NULL device: we know this
239 * is already NULL but explicitly assign it here for people to
240 * know what is going on. (Yes this is an ugly legacy hack, live
241 * with it.)
242 */
243 lookup->dev_id = NULL;
244
245 for (i = 0; i < ATH79K_WIFI_DESCS; i++) {
246 lookup->table[i] =
247 /*
248 * Set the HW offset on the chip and the lookup
249 * index to the same value, so looking up index 0
250 * will get HW offset 0, index 1 HW offset 1 etc.
251 */
252 GPIO_LOOKUP_IDX(label, i, "ath9k", i, GPIO_ACTIVE_HIGH);
253 }
254
255 gpiod_add_lookup_table(lookup);
256
257 return 0;
258}
259#else
260static int ath79_gpio_register_wifi_descriptors(struct device *dev,
261 const char *label)
262{
263 return 0;
264}
265#endif
266
267static int ath79_gpio_probe(struct platform_device *pdev)
268{
269 struct gpio_generic_chip_config config;
270 struct device *dev = &pdev->dev;
271 struct ath79_gpio_ctrl *ctrl;
272 struct gpio_irq_chip *girq;
273 u32 ath79_gpio_count;
274 bool oe_inverted;
275 int err;
276
277 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
278 if (!ctrl)
279 return -ENOMEM;
280
281 err = device_property_read_u32(dev, "ngpios", &ath79_gpio_count);
282 if (err) {
283 dev_err(dev, "ngpios property is not valid\n");
284 return err;
285 }
286
287 oe_inverted = device_is_compatible(dev, "qca,ar9340-gpio");
288
289 if (ath79_gpio_count >= 32) {
290 dev_err(dev, "ngpios must be less than 32\n");
291 return -EINVAL;
292 }
293
294 ctrl->base = devm_platform_ioremap_resource(pdev, 0);
295 if (IS_ERR(ctrl->base))
296 return PTR_ERR(ctrl->base);
297
298 config = (struct gpio_generic_chip_config) {
299 .dev = dev,
300 .sz = 4,
301 .dat = ctrl->base + AR71XX_GPIO_REG_IN,
302 .set = ctrl->base + AR71XX_GPIO_REG_SET,
303 .clr = ctrl->base + AR71XX_GPIO_REG_CLEAR,
304 .dirout = oe_inverted ? NULL : ctrl->base + AR71XX_GPIO_REG_OE,
305 .dirin = oe_inverted ? ctrl->base + AR71XX_GPIO_REG_OE : NULL,
306 };
307
308 err = gpio_generic_chip_init(&ctrl->chip, &config);
309 if (err) {
310 dev_err(dev, "failed to initialize generic GPIO chip\n");
311 return err;
312 }
313
314 /* Optional interrupt setup */
315 if (device_property_read_bool(dev, "interrupt-controller")) {
316 girq = &ctrl->chip.gc.irq;
317 gpio_irq_chip_set_chip(girq, &ath79_gpio_irqchip);
318 girq->parent_handler = ath79_gpio_irq_handler;
319 girq->num_parents = 1;
320 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
321 GFP_KERNEL);
322 if (!girq->parents)
323 return -ENOMEM;
324 girq->parents[0] = platform_get_irq(pdev, 0);
325 girq->default_type = IRQ_TYPE_NONE;
326 girq->handler = handle_simple_irq;
327 }
328
329 err = devm_gpiochip_add_data(dev, &ctrl->chip.gc, ctrl);
330 if (err)
331 return err;
332
333 return ath79_gpio_register_wifi_descriptors(dev, ctrl->chip.gc.label);
334}
335
336static struct platform_driver ath79_gpio_driver = {
337 .driver = {
338 .name = "ath79-gpio",
339 .of_match_table = ath79_gpio_of_match,
340 },
341 .probe = ath79_gpio_probe,
342};
343
344module_platform_driver(ath79_gpio_driver);
345
346MODULE_DESCRIPTION("Atheros AR71XX/AR724X/AR913X GPIO API support");
347MODULE_LICENSE("GPL v2");