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1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include <linux/irqdomain.h>
27#include <linux/pci.h>
28#include <linux/pm_domain.h>
29#include <linux/platform_device.h>
30#include <sound/designware_i2s.h>
31#include <sound/pcm.h>
32#include <linux/acpi.h>
33#include <linux/dmi.h>
34
35#include "amdgpu.h"
36#include "atom.h"
37#include "amdgpu_acp.h"
38
39#include "acp_gfx_if.h"
40
41#define ST_JADEITE 1
42#define ACP_TILE_ON_MASK 0x03
43#define ACP_TILE_OFF_MASK 0x02
44#define ACP_TILE_ON_RETAIN_REG_MASK 0x1f
45#define ACP_TILE_OFF_RETAIN_REG_MASK 0x20
46
47#define ACP_TILE_P1_MASK 0x3e
48#define ACP_TILE_P2_MASK 0x3d
49#define ACP_TILE_DSP0_MASK 0x3b
50#define ACP_TILE_DSP1_MASK 0x37
51
52#define ACP_TILE_DSP2_MASK 0x2f
53
54#define ACP_DMA_REGS_END 0x146c0
55#define ACP_I2S_PLAY_REGS_START 0x14840
56#define ACP_I2S_PLAY_REGS_END 0x148b4
57#define ACP_I2S_CAP_REGS_START 0x148b8
58#define ACP_I2S_CAP_REGS_END 0x1496c
59
60#define ACP_I2S_COMP1_CAP_REG_OFFSET 0xac
61#define ACP_I2S_COMP2_CAP_REG_OFFSET 0xa8
62#define ACP_I2S_COMP1_PLAY_REG_OFFSET 0x6c
63#define ACP_I2S_COMP2_PLAY_REG_OFFSET 0x68
64#define ACP_BT_PLAY_REGS_START 0x14970
65#define ACP_BT_PLAY_REGS_END 0x14a24
66#define ACP_BT_COMP1_REG_OFFSET 0xac
67#define ACP_BT_COMP2_REG_OFFSET 0xa8
68
69#define mmACP_PGFSM_RETAIN_REG 0x51c9
70#define mmACP_PGFSM_CONFIG_REG 0x51ca
71#define mmACP_PGFSM_READ_REG_0 0x51cc
72
73#define mmACP_MEM_SHUT_DOWN_REQ_LO 0x51f8
74#define mmACP_MEM_SHUT_DOWN_REQ_HI 0x51f9
75#define mmACP_MEM_SHUT_DOWN_STS_LO 0x51fa
76#define mmACP_MEM_SHUT_DOWN_STS_HI 0x51fb
77
78#define mmACP_CONTROL 0x5131
79#define mmACP_STATUS 0x5133
80#define mmACP_SOFT_RESET 0x5134
81#define ACP_CONTROL__ClkEn_MASK 0x1
82#define ACP_SOFT_RESET__SoftResetAud_MASK 0x100
83#define ACP_SOFT_RESET__SoftResetAudDone_MASK 0x1000000
84#define ACP_CLOCK_EN_TIME_OUT_VALUE 0x000000FF
85#define ACP_SOFT_RESET_DONE_TIME_OUT_VALUE 0x000000FF
86
87#define ACP_TIMEOUT_LOOP 0x000000FF
88#define ACP_DEVS 4
89#define ACP_SRC_ID 162
90
91static unsigned long acp_machine_id;
92
93enum {
94 ACP_TILE_P1 = 0,
95 ACP_TILE_P2,
96 ACP_TILE_DSP0,
97 ACP_TILE_DSP1,
98 ACP_TILE_DSP2,
99};
100
101static int acp_sw_init(struct amdgpu_ip_block *ip_block)
102{
103 struct amdgpu_device *adev = ip_block->adev;
104
105 adev->acp.parent = adev->dev;
106
107 adev->acp.cgs_device =
108 amdgpu_cgs_create_device(adev);
109 if (!adev->acp.cgs_device)
110 return -EINVAL;
111
112 return 0;
113}
114
115static int acp_sw_fini(struct amdgpu_ip_block *ip_block)
116{
117 struct amdgpu_device *adev = ip_block->adev;
118
119 if (adev->acp.cgs_device)
120 amdgpu_cgs_destroy_device(adev->acp.cgs_device);
121
122 return 0;
123}
124
125struct acp_pm_domain {
126 void *adev;
127 struct generic_pm_domain gpd;
128};
129
130static int acp_poweroff(struct generic_pm_domain *genpd)
131{
132 struct acp_pm_domain *apd;
133 struct amdgpu_device *adev;
134
135 apd = container_of(genpd, struct acp_pm_domain, gpd);
136 adev = apd->adev;
137 /* call smu to POWER GATE ACP block
138 * smu will
139 * 1. turn off the acp clock
140 * 2. power off the acp tiles
141 * 3. check and enter ulv state
142 */
143 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true, 0);
144 return 0;
145}
146
147static int acp_poweron(struct generic_pm_domain *genpd)
148{
149 struct acp_pm_domain *apd;
150 struct amdgpu_device *adev;
151
152 apd = container_of(genpd, struct acp_pm_domain, gpd);
153 adev = apd->adev;
154 /* call smu to UNGATE ACP block
155 * smu will
156 * 1. exit ulv
157 * 2. turn on acp clock
158 * 3. power on acp tiles
159 */
160 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false, 0);
161 return 0;
162}
163
164static int acp_genpd_add_device(struct device *dev, void *data)
165{
166 struct generic_pm_domain *gpd = data;
167 int ret;
168
169 ret = pm_genpd_add_device(gpd, dev);
170 if (ret)
171 dev_err(dev, "Failed to add dev to genpd %d\n", ret);
172
173 return ret;
174}
175
176static int acp_genpd_remove_device(struct device *dev, void *data)
177{
178 int ret;
179
180 ret = pm_genpd_remove_device(dev);
181 if (ret)
182 dev_err(dev, "Failed to remove dev from genpd %d\n", ret);
183
184 /* Continue to remove */
185 return 0;
186}
187
188static int acp_quirk_cb(const struct dmi_system_id *id)
189{
190 acp_machine_id = ST_JADEITE;
191 return 1;
192}
193
194static const struct dmi_system_id acp_quirk_table[] = {
195 {
196 .callback = acp_quirk_cb,
197 .matches = {
198 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AMD"),
199 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Jadeite"),
200 }
201 },
202 {
203 .callback = acp_quirk_cb,
204 .matches = {
205 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "IP3 Technology CO.,Ltd."),
206 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "ASN1D"),
207 },
208 },
209 {
210 .callback = acp_quirk_cb,
211 .matches = {
212 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "Standard"),
213 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "ASN10"),
214 },
215 },
216 {}
217};
218
219/**
220 * acp_hw_init - start and test ACP block
221 *
222 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
223 *
224 */
225static int acp_hw_init(struct amdgpu_ip_block *ip_block)
226{
227 int r;
228 u64 acp_base;
229 u32 val = 0;
230 u32 count = 0;
231
232 struct amdgpu_device *adev = ip_block->adev;
233
234 r = amd_acp_hw_init(adev->acp.cgs_device,
235 ip_block->version->major, ip_block->version->minor);
236 /* -ENODEV means board uses AZ rather than ACP */
237 if (r == -ENODEV) {
238 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true, 0);
239 return 0;
240 } else if (r) {
241 return r;
242 }
243
244 if (adev->rmmio_size == 0 || adev->rmmio_size < 0x5289)
245 return -EINVAL;
246
247 acp_base = adev->rmmio_base;
248 adev->acp.acp_genpd = kzalloc_obj(struct acp_pm_domain);
249 if (!adev->acp.acp_genpd)
250 return -ENOMEM;
251
252 adev->acp.acp_genpd->gpd.name = "ACP_AUDIO";
253 adev->acp.acp_genpd->gpd.power_off = acp_poweroff;
254 adev->acp.acp_genpd->gpd.power_on = acp_poweron;
255 adev->acp.acp_genpd->adev = adev;
256
257 pm_genpd_init(&adev->acp.acp_genpd->gpd, NULL, false);
258 dmi_check_system(acp_quirk_table);
259 switch (acp_machine_id) {
260 case ST_JADEITE:
261 {
262 adev->acp.acp_cell = kzalloc_objs(struct mfd_cell, 2);
263 if (!adev->acp.acp_cell) {
264 r = -ENOMEM;
265 goto failure;
266 }
267
268 adev->acp.acp_res = kzalloc_objs(struct resource, 3);
269 if (!adev->acp.acp_res) {
270 r = -ENOMEM;
271 goto failure;
272 }
273
274 adev->acp.i2s_pdata = kzalloc_objs(struct i2s_platform_data, 1);
275 if (!adev->acp.i2s_pdata) {
276 r = -ENOMEM;
277 goto failure;
278 }
279
280 adev->acp.i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
281 DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
282 adev->acp.i2s_pdata[0].cap = DWC_I2S_PLAY | DWC_I2S_RECORD;
283 adev->acp.i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000;
284 adev->acp.i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET;
285 adev->acp.i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET;
286
287 adev->acp.acp_res[0].name = "acp2x_dma";
288 adev->acp.acp_res[0].flags = IORESOURCE_MEM;
289 adev->acp.acp_res[0].start = acp_base;
290 adev->acp.acp_res[0].end = acp_base + ACP_DMA_REGS_END;
291
292 adev->acp.acp_res[1].name = "acp2x_dw_i2s_play_cap";
293 adev->acp.acp_res[1].flags = IORESOURCE_MEM;
294 adev->acp.acp_res[1].start = acp_base + ACP_I2S_CAP_REGS_START;
295 adev->acp.acp_res[1].end = acp_base + ACP_I2S_CAP_REGS_END;
296
297 adev->acp.acp_res[2].name = "acp2x_dma_irq";
298 adev->acp.acp_res[2].flags = IORESOURCE_IRQ;
299 adev->acp.acp_res[2].start = amdgpu_irq_create_mapping(adev, 162);
300 adev->acp.acp_res[2].end = adev->acp.acp_res[2].start;
301
302 adev->acp.acp_cell[0].name = "acp_audio_dma";
303 adev->acp.acp_cell[0].id = 0;
304 adev->acp.acp_cell[0].num_resources = 3;
305 adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0];
306 adev->acp.acp_cell[0].platform_data = &adev->asic_type;
307 adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type);
308
309 adev->acp.acp_cell[1].name = "designware-i2s";
310 adev->acp.acp_cell[1].id = 1;
311 adev->acp.acp_cell[1].num_resources = 1;
312 adev->acp.acp_cell[1].resources = &adev->acp.acp_res[1];
313 adev->acp.acp_cell[1].platform_data = &adev->acp.i2s_pdata[0];
314 adev->acp.acp_cell[1].pdata_size = sizeof(struct i2s_platform_data);
315 r = mfd_add_devices(adev->acp.parent, 0, adev->acp.acp_cell, 2, NULL, 0, NULL);
316 if (r)
317 goto failure;
318 r = device_for_each_child(adev->acp.parent, &adev->acp.acp_genpd->gpd,
319 acp_genpd_add_device);
320 if (r)
321 goto failure_remove_mfd;
322 break;
323 }
324 default:
325 adev->acp.acp_cell = kzalloc_objs(struct mfd_cell, ACP_DEVS);
326
327 if (!adev->acp.acp_cell) {
328 r = -ENOMEM;
329 goto failure;
330 }
331
332 adev->acp.acp_res = kzalloc_objs(struct resource, 5);
333 if (!adev->acp.acp_res) {
334 r = -ENOMEM;
335 goto failure;
336 }
337
338 adev->acp.i2s_pdata = kzalloc_objs(struct i2s_platform_data, 3);
339 if (!adev->acp.i2s_pdata) {
340 r = -ENOMEM;
341 goto failure;
342 }
343
344 switch (adev->asic_type) {
345 case CHIP_STONEY:
346 adev->acp.i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
347 DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
348 break;
349 default:
350 adev->acp.i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
351 }
352 adev->acp.i2s_pdata[0].cap = DWC_I2S_PLAY;
353 adev->acp.i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000;
354 adev->acp.i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_PLAY_REG_OFFSET;
355 adev->acp.i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_PLAY_REG_OFFSET;
356 switch (adev->asic_type) {
357 case CHIP_STONEY:
358 adev->acp.i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
359 DW_I2S_QUIRK_COMP_PARAM1 |
360 DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
361 break;
362 default:
363 adev->acp.i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
364 DW_I2S_QUIRK_COMP_PARAM1;
365 }
366
367 adev->acp.i2s_pdata[1].cap = DWC_I2S_RECORD;
368 adev->acp.i2s_pdata[1].snd_rates = SNDRV_PCM_RATE_8000_96000;
369 adev->acp.i2s_pdata[1].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET;
370 adev->acp.i2s_pdata[1].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET;
371
372 adev->acp.i2s_pdata[2].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
373 switch (adev->asic_type) {
374 case CHIP_STONEY:
375 adev->acp.i2s_pdata[2].quirks |= DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
376 break;
377 default:
378 break;
379 }
380
381 adev->acp.i2s_pdata[2].cap = DWC_I2S_PLAY | DWC_I2S_RECORD;
382 adev->acp.i2s_pdata[2].snd_rates = SNDRV_PCM_RATE_8000_96000;
383 adev->acp.i2s_pdata[2].i2s_reg_comp1 = ACP_BT_COMP1_REG_OFFSET;
384 adev->acp.i2s_pdata[2].i2s_reg_comp2 = ACP_BT_COMP2_REG_OFFSET;
385
386 adev->acp.acp_res[0].name = "acp2x_dma";
387 adev->acp.acp_res[0].flags = IORESOURCE_MEM;
388 adev->acp.acp_res[0].start = acp_base;
389 adev->acp.acp_res[0].end = acp_base + ACP_DMA_REGS_END;
390
391 adev->acp.acp_res[1].name = "acp2x_dw_i2s_play";
392 adev->acp.acp_res[1].flags = IORESOURCE_MEM;
393 adev->acp.acp_res[1].start = acp_base + ACP_I2S_PLAY_REGS_START;
394 adev->acp.acp_res[1].end = acp_base + ACP_I2S_PLAY_REGS_END;
395
396 adev->acp.acp_res[2].name = "acp2x_dw_i2s_cap";
397 adev->acp.acp_res[2].flags = IORESOURCE_MEM;
398 adev->acp.acp_res[2].start = acp_base + ACP_I2S_CAP_REGS_START;
399 adev->acp.acp_res[2].end = acp_base + ACP_I2S_CAP_REGS_END;
400
401 adev->acp.acp_res[3].name = "acp2x_dw_bt_i2s_play_cap";
402 adev->acp.acp_res[3].flags = IORESOURCE_MEM;
403 adev->acp.acp_res[3].start = acp_base + ACP_BT_PLAY_REGS_START;
404 adev->acp.acp_res[3].end = acp_base + ACP_BT_PLAY_REGS_END;
405
406 adev->acp.acp_res[4].name = "acp2x_dma_irq";
407 adev->acp.acp_res[4].flags = IORESOURCE_IRQ;
408 adev->acp.acp_res[4].start = amdgpu_irq_create_mapping(adev, 162);
409 adev->acp.acp_res[4].end = adev->acp.acp_res[4].start;
410
411 adev->acp.acp_cell[0].name = "acp_audio_dma";
412 adev->acp.acp_cell[0].id = 0;
413 adev->acp.acp_cell[0].num_resources = 5;
414 adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0];
415 adev->acp.acp_cell[0].platform_data = &adev->asic_type;
416 adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type);
417
418 adev->acp.acp_cell[1].name = "designware-i2s";
419 adev->acp.acp_cell[1].id = 1;
420 adev->acp.acp_cell[1].num_resources = 1;
421 adev->acp.acp_cell[1].resources = &adev->acp.acp_res[1];
422 adev->acp.acp_cell[1].platform_data = &adev->acp.i2s_pdata[0];
423 adev->acp.acp_cell[1].pdata_size = sizeof(struct i2s_platform_data);
424
425 adev->acp.acp_cell[2].name = "designware-i2s";
426 adev->acp.acp_cell[2].id = 2;
427 adev->acp.acp_cell[2].num_resources = 1;
428 adev->acp.acp_cell[2].resources = &adev->acp.acp_res[2];
429 adev->acp.acp_cell[2].platform_data = &adev->acp.i2s_pdata[1];
430 adev->acp.acp_cell[2].pdata_size = sizeof(struct i2s_platform_data);
431
432 adev->acp.acp_cell[3].name = "designware-i2s";
433 adev->acp.acp_cell[3].id = 3;
434 adev->acp.acp_cell[3].num_resources = 1;
435 adev->acp.acp_cell[3].resources = &adev->acp.acp_res[3];
436 adev->acp.acp_cell[3].platform_data = &adev->acp.i2s_pdata[2];
437 adev->acp.acp_cell[3].pdata_size = sizeof(struct i2s_platform_data);
438
439 r = mfd_add_devices(adev->acp.parent, 0, adev->acp.acp_cell, ACP_DEVS, NULL, 0, NULL);
440 if (r)
441 goto failure;
442
443 r = device_for_each_child(adev->acp.parent, &adev->acp.acp_genpd->gpd,
444 acp_genpd_add_device);
445 if (r)
446 goto failure_remove_mfd;
447 }
448
449 /* Assert Soft reset of ACP */
450 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
451
452 val |= ACP_SOFT_RESET__SoftResetAud_MASK;
453 cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
454
455 count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
456 while (true) {
457 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
458 if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
459 (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
460 break;
461 if (--count == 0) {
462 dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
463 r = -ETIMEDOUT;
464 goto failure_remove_mfd;
465 }
466 udelay(100);
467 }
468 /* Enable clock to ACP and wait until the clock is enabled */
469 val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL);
470 val = val | ACP_CONTROL__ClkEn_MASK;
471 cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val);
472
473 count = ACP_CLOCK_EN_TIME_OUT_VALUE;
474
475 while (true) {
476 val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS);
477 if (val & (u32) 0x1)
478 break;
479 if (--count == 0) {
480 dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
481 r = -ETIMEDOUT;
482 goto failure_remove_mfd;
483 }
484 udelay(100);
485 }
486 /* Deassert the SOFT RESET flags */
487 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
488 val &= ~ACP_SOFT_RESET__SoftResetAud_MASK;
489 cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
490 return 0;
491
492failure_remove_mfd:
493 device_for_each_child(adev->acp.parent, NULL,
494 acp_genpd_remove_device);
495 mfd_remove_devices(adev->acp.parent);
496
497failure:
498 kfree(adev->acp.i2s_pdata);
499 kfree(adev->acp.acp_res);
500 kfree(adev->acp.acp_cell);
501 kfree(adev->acp.acp_genpd);
502 return r;
503}
504
505/**
506 * acp_hw_fini - stop the hardware block
507 *
508 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
509 *
510 */
511static int acp_hw_fini(struct amdgpu_ip_block *ip_block)
512{
513 u32 val = 0;
514 u32 count = 0;
515 struct amdgpu_device *adev = ip_block->adev;
516 int ret = 0;
517
518 /* return early if no ACP */
519 if (!adev->acp.acp_genpd) {
520 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false, 0);
521 return 0;
522 }
523
524 /* Assert Soft reset of ACP */
525 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
526
527 val |= ACP_SOFT_RESET__SoftResetAud_MASK;
528 cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
529
530 count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
531 while (true) {
532 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
533 if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
534 (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
535 break;
536 if (--count == 0) {
537 dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
538 ret = -ETIMEDOUT;
539 goto out;
540 }
541 udelay(100);
542 }
543 /* Disable ACP clock */
544 val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL);
545 val &= ~ACP_CONTROL__ClkEn_MASK;
546 cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val);
547
548 count = ACP_CLOCK_EN_TIME_OUT_VALUE;
549
550 while (true) {
551 val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS);
552 if (val & (u32) 0x1)
553 break;
554 if (--count == 0) {
555 dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
556 ret = -ETIMEDOUT;
557 goto out;
558 }
559 udelay(100);
560 }
561out:
562 device_for_each_child(adev->acp.parent, NULL,
563 acp_genpd_remove_device);
564
565 mfd_remove_devices(adev->acp.parent);
566 kfree(adev->acp.i2s_pdata);
567 kfree(adev->acp.acp_res);
568 pm_genpd_remove(&adev->acp.acp_genpd->gpd);
569 kfree(adev->acp.acp_genpd);
570 adev->acp.acp_genpd = NULL;
571 kfree(adev->acp.acp_cell);
572
573 return ret;
574}
575
576static int acp_suspend(struct amdgpu_ip_block *ip_block)
577{
578 struct amdgpu_device *adev = ip_block->adev;
579
580 /* power up on suspend */
581 if (!adev->acp.acp_cell)
582 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false, 0);
583 return 0;
584}
585
586static int acp_resume(struct amdgpu_ip_block *ip_block)
587{
588 struct amdgpu_device *adev = ip_block->adev;
589
590 /* power down again on resume */
591 if (!adev->acp.acp_cell)
592 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true, 0);
593 return 0;
594}
595
596static bool acp_is_idle(struct amdgpu_ip_block *ip_block)
597{
598 return true;
599}
600
601static int acp_set_clockgating_state(struct amdgpu_ip_block *ip_block,
602 enum amd_clockgating_state state)
603{
604 return 0;
605}
606
607static int acp_set_powergating_state(struct amdgpu_ip_block *ip_block,
608 enum amd_powergating_state state)
609{
610 struct amdgpu_device *adev = ip_block->adev;
611 bool enable = (state == AMD_PG_STATE_GATE);
612
613 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, enable, 0);
614
615 return 0;
616}
617
618static const struct amd_ip_funcs acp_ip_funcs = {
619 .name = "acp_ip",
620 .sw_init = acp_sw_init,
621 .sw_fini = acp_sw_fini,
622 .hw_init = acp_hw_init,
623 .hw_fini = acp_hw_fini,
624 .suspend = acp_suspend,
625 .resume = acp_resume,
626 .is_idle = acp_is_idle,
627 .set_clockgating_state = acp_set_clockgating_state,
628 .set_powergating_state = acp_set_powergating_state,
629};
630
631const struct amdgpu_ip_block_version acp_ip_block = {
632 .type = AMD_IP_BLOCK_TYPE_ACP,
633 .major = 2,
634 .minor = 2,
635 .rev = 0,
636 .funcs = &acp_ip_funcs,
637};