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259 lines · 6.4 KiB

1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Christian König <[email protected]>
29 */
30
31#include <linux/sort.h>
32#include <linux/uaccess.h>
33
34#include "amdgpu.h"
35#include "amdgpu_trace.h"
36
37#define AMDGPU_BO_LIST_MAX_PRIORITY 32u
38#define AMDGPU_BO_LIST_NUM_BUCKETS (AMDGPU_BO_LIST_MAX_PRIORITY + 1)
39#define AMDGPU_BO_LIST_MAX_ENTRIES (128 * 1024)
40
41static void amdgpu_bo_list_free(struct kref *ref)
42{
43 struct amdgpu_bo_list *list = container_of(ref, struct amdgpu_bo_list,
44 refcount);
45 struct amdgpu_bo_list_entry *e;
46
47 amdgpu_bo_list_for_each_entry(e, list)
48 amdgpu_bo_unref(&e->bo);
49
50 kvfree(list);
51}
52
53static int amdgpu_bo_list_entry_cmp(const void *_a, const void *_b)
54{
55 const struct amdgpu_bo_list_entry *a = _a, *b = _b;
56
57 BUILD_BUG_ON(AMDGPU_BO_LIST_MAX_PRIORITY >= INT_MAX);
58
59 return (int)a->priority - (int)b->priority;
60}
61
62struct amdgpu_bo_list *
63amdgpu_bo_list_create(struct amdgpu_device *adev, struct drm_file *filp,
64 struct drm_amdgpu_bo_list_entry *info, size_t num_entries)
65{
66 unsigned last_entry = 0, first_userptr = num_entries;
67 struct amdgpu_bo_list_entry *array;
68 struct amdgpu_bo_list *list;
69 uint64_t total_size = 0;
70 unsigned i;
71 int r;
72
73 list = kvzalloc_flex(*list, entries, num_entries);
74 if (!list)
75 return ERR_PTR(-ENOMEM);
76
77 kref_init(&list->refcount);
78
79 list->num_entries = num_entries;
80 array = list->entries;
81
82 for (i = 0; i < num_entries; ++i) {
83 struct amdgpu_bo_list_entry *entry;
84 struct drm_gem_object *gobj;
85 struct amdgpu_bo *bo;
86 struct mm_struct *usermm;
87
88 gobj = drm_gem_object_lookup(filp, info[i].bo_handle);
89 if (!gobj) {
90 r = -ENOENT;
91 goto error_free;
92 }
93
94 bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
95 drm_gem_object_put(gobj);
96
97 usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
98 if (usermm) {
99 if (usermm != current->mm) {
100 amdgpu_bo_unref(&bo);
101 r = -EPERM;
102 goto error_free;
103 }
104 entry = &array[--first_userptr];
105 } else {
106 entry = &array[last_entry++];
107 }
108
109 entry->priority = min(info[i].bo_priority,
110 AMDGPU_BO_LIST_MAX_PRIORITY);
111 entry->bo = bo;
112
113 if (bo->preferred_domains == AMDGPU_GEM_DOMAIN_GDS)
114 list->gds_obj = bo;
115 if (bo->preferred_domains == AMDGPU_GEM_DOMAIN_GWS)
116 list->gws_obj = bo;
117 if (bo->preferred_domains == AMDGPU_GEM_DOMAIN_OA)
118 list->oa_obj = bo;
119
120 total_size += amdgpu_bo_size(bo);
121 trace_amdgpu_bo_list_set(list, bo);
122 }
123
124 list->first_userptr = first_userptr;
125 sort(array, last_entry, sizeof(struct amdgpu_bo_list_entry),
126 amdgpu_bo_list_entry_cmp, NULL);
127
128 trace_amdgpu_cs_bo_status(list->num_entries, total_size);
129
130 return list;
131
132error_free:
133 for (i = 0; i < last_entry; ++i)
134 amdgpu_bo_unref(&array[i].bo);
135 for (i = first_userptr; i < num_entries; ++i)
136 amdgpu_bo_unref(&array[i].bo);
137 kvfree(list);
138 return ERR_PTR(r);
139
140}
141
142struct amdgpu_bo_list *amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, u32 id)
143{
144 struct amdgpu_bo_list *list;
145
146 xa_lock(&fpriv->bo_list_handles);
147 list = xa_load(&fpriv->bo_list_handles, id);
148 if (list)
149 kref_get(&list->refcount);
150 else
151 list = ERR_PTR(-ENOENT);
152 xa_unlock(&fpriv->bo_list_handles);
153
154 return list;
155}
156
157void amdgpu_bo_list_put(struct amdgpu_bo_list *list)
158{
159 if (list)
160 kref_put(&list->refcount, amdgpu_bo_list_free);
161}
162
163struct drm_amdgpu_bo_list_entry *
164amdgpu_bo_create_list_entry_array(struct drm_amdgpu_bo_list_in *in)
165{
166 const void __user *uptr = u64_to_user_ptr(in->bo_info_ptr);
167 const uint32_t bo_number = in->bo_number;
168
169 if (bo_number > AMDGPU_BO_LIST_MAX_ENTRIES)
170 return ERR_PTR(-EINVAL);
171
172 if (in->bo_info_size != sizeof(struct drm_amdgpu_bo_list_entry))
173 return ERR_PTR(-EINVAL);
174
175 return vmemdup_array_user(uptr, bo_number,
176 sizeof(struct drm_amdgpu_bo_list_entry));
177}
178
179int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
180 struct drm_file *filp)
181{
182 struct amdgpu_fpriv *fpriv = filp->driver_priv;
183 struct amdgpu_device *adev = drm_to_adev(dev);
184 struct amdgpu_bo_list *list, *prev, *curr;
185 union drm_amdgpu_bo_list *args = data;
186 uint32_t handle = args->in.list_handle;
187 struct drm_amdgpu_bo_list_entry *info;
188 int r;
189
190 switch (args->in.operation) {
191 case AMDGPU_BO_LIST_OP_CREATE:
192 case AMDGPU_BO_LIST_OP_UPDATE:
193 info = amdgpu_bo_create_list_entry_array(&args->in);
194 if (IS_ERR(info))
195 return PTR_ERR(info);
196
197 list = amdgpu_bo_list_create(adev, filp, info,
198 args->in.bo_number);
199 kvfree(info);
200 if (IS_ERR(list))
201 return PTR_ERR(list);
202
203 break;
204
205 case AMDGPU_BO_LIST_OP_DESTROY:
206 list = xa_erase(&fpriv->bo_list_handles, handle);
207 amdgpu_bo_list_put(list);
208 handle = 0;
209
210 break;
211
212 default:
213 return -EINVAL;
214 };
215
216 switch (args->in.operation) {
217 case AMDGPU_BO_LIST_OP_CREATE:
218 r = xa_alloc(&fpriv->bo_list_handles, &handle, list,
219 xa_limit_32b, GFP_KERNEL);
220 if (r)
221 goto error_put_list;
222
223 break;
224
225 case AMDGPU_BO_LIST_OP_UPDATE:
226 curr = xa_load(&fpriv->bo_list_handles, handle);
227 if (!curr) {
228 r = -ENOENT;
229 goto error_put_list;
230 }
231
232 prev = xa_cmpxchg(&fpriv->bo_list_handles, handle, curr, list,
233 GFP_KERNEL);
234 if (xa_is_err(prev)) {
235 r = xa_err(prev);
236 goto error_put_list;
237 } else if (prev != curr) {
238 r = -ENOENT;
239 goto error_put_list;
240 }
241
242 amdgpu_bo_list_put(curr);
243 break;
244
245 case AMDGPU_BO_LIST_OP_DESTROY:
246 default:
247 /* Handled above. */
248 break;
249 }
250
251 memset(args, 0, sizeof(*args));
252 args->out.list_handle = handle;
253
254 return 0;
255
256error_put_list:
257 amdgpu_bo_list_put(list);
258 return r;
259}