projects/linux·blob master · refs

414 lines · 11.8 KiB

1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 *
23 */
24#include <linux/list.h>
25#include <linux/pci.h>
26#include <linux/slab.h>
27
28#include <linux/firmware.h>
29#include <drm/amdgpu_drm.h>
30#include "amdgpu.h"
31#include "atom.h"
32#include "amdgpu_ucode.h"
33
34struct amdgpu_cgs_device {
35 struct cgs_device base;
36 struct amdgpu_device *adev;
37};
38
39#define CGS_FUNC_ADEV \
40 struct amdgpu_device *adev = \
41 ((struct amdgpu_cgs_device *)cgs_device)->adev
42
43
44static uint32_t amdgpu_cgs_read_register(struct cgs_device *cgs_device, unsigned int offset)
45{
46 CGS_FUNC_ADEV;
47 return RREG32(offset);
48}
49
50static void amdgpu_cgs_write_register(struct cgs_device *cgs_device, unsigned int offset,
51 uint32_t value)
52{
53 CGS_FUNC_ADEV;
54 WREG32(offset, value);
55}
56
57static uint32_t amdgpu_cgs_read_ind_register(struct cgs_device *cgs_device,
58 enum cgs_ind_reg space,
59 unsigned int index)
60{
61 CGS_FUNC_ADEV;
62 switch (space) {
63 case CGS_IND_REG__PCIE:
64 return RREG32_PCIE(index);
65 case CGS_IND_REG__SMC:
66 return RREG32_SMC(index);
67 case CGS_IND_REG__UVD_CTX:
68 return RREG32_UVD_CTX(index);
69 case CGS_IND_REG__DIDT:
70 return RREG32_DIDT(index);
71 case CGS_IND_REG_GC_CAC:
72 return RREG32_GC_CAC(index);
73 case CGS_IND_REG_SE_CAC:
74 return RREG32_SE_CAC(index);
75 case CGS_IND_REG__AUDIO_ENDPT:
76 DRM_ERROR("audio endpt register access not implemented.\n");
77 return 0;
78 default:
79 WARN(1, "Invalid indirect register space");
80 return 0;
81 }
82}
83
84static void amdgpu_cgs_write_ind_register(struct cgs_device *cgs_device,
85 enum cgs_ind_reg space,
86 unsigned int index, uint32_t value)
87{
88 CGS_FUNC_ADEV;
89 switch (space) {
90 case CGS_IND_REG__PCIE:
91 return WREG32_PCIE(index, value);
92 case CGS_IND_REG__SMC:
93 return WREG32_SMC(index, value);
94 case CGS_IND_REG__UVD_CTX:
95 return WREG32_UVD_CTX(index, value);
96 case CGS_IND_REG__DIDT:
97 return WREG32_DIDT(index, value);
98 case CGS_IND_REG_GC_CAC:
99 return WREG32_GC_CAC(index, value);
100 case CGS_IND_REG_SE_CAC:
101 return WREG32_SE_CAC(index, value);
102 case CGS_IND_REG__AUDIO_ENDPT:
103 DRM_ERROR("audio endpt register access not implemented.\n");
104 return;
105 default:
106 WARN(1, "Invalid indirect register space");
107 }
108}
109
110static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type)
111{
112 CGS_FUNC_ADEV;
113 enum AMDGPU_UCODE_ID result = AMDGPU_UCODE_ID_MAXIMUM;
114
115 switch (fw_type) {
116 case CGS_UCODE_ID_SDMA0:
117 result = AMDGPU_UCODE_ID_SDMA0;
118 break;
119 case CGS_UCODE_ID_SDMA1:
120 result = AMDGPU_UCODE_ID_SDMA1;
121 break;
122 case CGS_UCODE_ID_CP_CE:
123 result = AMDGPU_UCODE_ID_CP_CE;
124 break;
125 case CGS_UCODE_ID_CP_PFP:
126 result = AMDGPU_UCODE_ID_CP_PFP;
127 break;
128 case CGS_UCODE_ID_CP_ME:
129 result = AMDGPU_UCODE_ID_CP_ME;
130 break;
131 case CGS_UCODE_ID_CP_MEC:
132 case CGS_UCODE_ID_CP_MEC_JT1:
133 result = AMDGPU_UCODE_ID_CP_MEC1;
134 break;
135 case CGS_UCODE_ID_CP_MEC_JT2:
136 /* for VI. JT2 should be the same as JT1, because:
137 1, MEC2 and MEC1 use exactly same FW.
138 2, JT2 is not pached but JT1 is.
139 */
140 if (adev->asic_type >= CHIP_TOPAZ)
141 result = AMDGPU_UCODE_ID_CP_MEC1;
142 else
143 result = AMDGPU_UCODE_ID_CP_MEC2;
144 break;
145 case CGS_UCODE_ID_RLC_G:
146 result = AMDGPU_UCODE_ID_RLC_G;
147 break;
148 case CGS_UCODE_ID_STORAGE:
149 result = AMDGPU_UCODE_ID_STORAGE;
150 break;
151 default:
152 DRM_ERROR("Firmware type not supported\n");
153 }
154 return result;
155}
156
157static uint16_t amdgpu_get_firmware_version(struct cgs_device *cgs_device,
158 enum cgs_ucode_id type)
159{
160 CGS_FUNC_ADEV;
161 uint16_t fw_version = 0;
162
163 switch (type) {
164 case CGS_UCODE_ID_SDMA0:
165 fw_version = adev->sdma.instance[0].fw_version;
166 break;
167 case CGS_UCODE_ID_SDMA1:
168 fw_version = adev->sdma.instance[1].fw_version;
169 break;
170 case CGS_UCODE_ID_CP_CE:
171 fw_version = adev->gfx.ce_fw_version;
172 break;
173 case CGS_UCODE_ID_CP_PFP:
174 fw_version = adev->gfx.pfp_fw_version;
175 break;
176 case CGS_UCODE_ID_CP_ME:
177 fw_version = adev->gfx.me_fw_version;
178 break;
179 case CGS_UCODE_ID_CP_MEC:
180 fw_version = adev->gfx.mec_fw_version;
181 break;
182 case CGS_UCODE_ID_CP_MEC_JT1:
183 fw_version = adev->gfx.mec_fw_version;
184 break;
185 case CGS_UCODE_ID_CP_MEC_JT2:
186 fw_version = adev->gfx.mec_fw_version;
187 break;
188 case CGS_UCODE_ID_RLC_G:
189 fw_version = adev->gfx.rlc_fw_version;
190 break;
191 case CGS_UCODE_ID_STORAGE:
192 break;
193 default:
194 DRM_ERROR("firmware type %d do not have version\n", type);
195 break;
196 }
197 return fw_version;
198}
199
200static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
201 enum cgs_ucode_id type,
202 struct cgs_firmware_info *info)
203{
204 CGS_FUNC_ADEV;
205
206 if (type != CGS_UCODE_ID_SMU && type != CGS_UCODE_ID_SMU_SK) {
207 uint64_t gpu_addr;
208 uint32_t data_size;
209 const struct gfx_firmware_header_v1_0 *header;
210 enum AMDGPU_UCODE_ID id;
211 struct amdgpu_firmware_info *ucode;
212
213 id = fw_type_convert(cgs_device, type);
214 if (id >= AMDGPU_UCODE_ID_MAXIMUM)
215 return -EINVAL;
216
217 ucode = &adev->firmware.ucode[id];
218 if (ucode->fw == NULL)
219 return -EINVAL;
220
221 gpu_addr = ucode->mc_addr;
222 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
223 data_size = le32_to_cpu(header->header.ucode_size_bytes);
224
225 if ((type == CGS_UCODE_ID_CP_MEC_JT1) ||
226 (type == CGS_UCODE_ID_CP_MEC_JT2)) {
227 gpu_addr += ALIGN(le32_to_cpu(header->header.ucode_size_bytes), PAGE_SIZE);
228 data_size = le32_to_cpu(header->jt_size) << 2;
229 }
230
231 info->kptr = ucode->kaddr;
232 info->image_size = data_size;
233 info->mc_addr = gpu_addr;
234 info->version = (uint16_t)le32_to_cpu(header->header.ucode_version);
235
236 if (type == CGS_UCODE_ID_CP_MEC)
237 info->image_size = le32_to_cpu(header->jt_offset) << 2;
238
239 info->fw_version = amdgpu_get_firmware_version(cgs_device, type);
240 info->feature_version = (uint16_t)le32_to_cpu(header->ucode_feature_version);
241 } else {
242 const char *fw_name = NULL;
243 int err = 0;
244 uint32_t ucode_size;
245 uint32_t ucode_start_address;
246 const uint8_t *src;
247 const struct smc_firmware_header_v1_0 *hdr;
248 const struct common_firmware_header *header;
249 struct amdgpu_firmware_info *ucode = NULL;
250
251 if (!adev->pm.fw) {
252 switch (adev->asic_type) {
253 case CHIP_BONAIRE:
254 if ((adev->pdev->revision == 0x80) ||
255 (adev->pdev->revision == 0x81) ||
256 (adev->pdev->device == 0x665f)) {
257 info->is_kicker = true;
258 fw_name = "bonaire_k_smc.bin";
259 } else {
260 fw_name = "bonaire_smc.bin";
261 }
262 break;
263 case CHIP_HAWAII:
264 if (adev->pdev->revision == 0x80) {
265 info->is_kicker = true;
266 fw_name = "hawaii_k_smc.bin";
267 } else {
268 fw_name = "hawaii_smc.bin";
269 }
270 break;
271 case CHIP_TOPAZ:
272 if (((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x81)) ||
273 ((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x83)) ||
274 ((adev->pdev->device == 0x6907) && (adev->pdev->revision == 0x87)) ||
275 ((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0xD1)) ||
276 ((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0xD3))) {
277 info->is_kicker = true;
278 fw_name = "topaz_k_smc.bin";
279 } else
280 fw_name = "topaz_smc.bin";
281 break;
282 case CHIP_TONGA:
283 if (((adev->pdev->device == 0x6939) && (adev->pdev->revision == 0xf1)) ||
284 ((adev->pdev->device == 0x6938) && (adev->pdev->revision == 0xf1))) {
285 info->is_kicker = true;
286 fw_name = "tonga_k_smc.bin";
287 } else
288 fw_name = "tonga_smc.bin";
289 break;
290 case CHIP_FIJI:
291 fw_name = "fiji_smc.bin";
292 break;
293 case CHIP_POLARIS11:
294 if (type == CGS_UCODE_ID_SMU) {
295 if (ASICID_IS_P21(adev->pdev->device, adev->pdev->revision)) {
296 info->is_kicker = true;
297 fw_name = "polaris11_k_smc.bin";
298 } else if (ASICID_IS_P31(adev->pdev->device, adev->pdev->revision)) {
299 info->is_kicker = true;
300 fw_name = "polaris11_k2_smc.bin";
301 } else {
302 fw_name = "polaris11_smc.bin";
303 }
304 } else if (type == CGS_UCODE_ID_SMU_SK) {
305 fw_name = "polaris11_smc_sk.bin";
306 }
307 break;
308 case CHIP_POLARIS10:
309 if (type == CGS_UCODE_ID_SMU) {
310 if (ASICID_IS_P20(adev->pdev->device, adev->pdev->revision)) {
311 info->is_kicker = true;
312 fw_name = "polaris10_k_smc.bin";
313 } else if (ASICID_IS_P30(adev->pdev->device, adev->pdev->revision)) {
314 info->is_kicker = true;
315 fw_name = "polaris10_k2_smc.bin";
316 } else {
317 fw_name = "polaris10_smc.bin";
318 }
319 } else if (type == CGS_UCODE_ID_SMU_SK) {
320 fw_name = "polaris10_smc_sk.bin";
321 }
322 break;
323 case CHIP_POLARIS12:
324 if (ASICID_IS_P23(adev->pdev->device, adev->pdev->revision)) {
325 info->is_kicker = true;
326 fw_name = "polaris12_k_smc.bin";
327 } else {
328 fw_name = "polaris12_smc.bin";
329 }
330 break;
331 case CHIP_VEGAM:
332 fw_name = "vegam_smc.bin";
333 break;
334 case CHIP_VEGA10:
335 if ((adev->pdev->device == 0x687f) &&
336 ((adev->pdev->revision == 0xc0) ||
337 (adev->pdev->revision == 0xc1) ||
338 (adev->pdev->revision == 0xc3)))
339 fw_name = "vega10_acg_smc.bin";
340 else
341 fw_name = "vega10_smc.bin";
342 break;
343 case CHIP_VEGA12:
344 fw_name = "vega12_smc.bin";
345 break;
346 case CHIP_VEGA20:
347 fw_name = "vega20_smc.bin";
348 break;
349 default:
350 drm_err(adev_to_drm(adev), "SMC firmware not supported\n");
351 return -EINVAL;
352 }
353
354 err = amdgpu_ucode_request(adev, &adev->pm.fw,
355 AMDGPU_UCODE_REQUIRED,
356 "amdgpu/%s", fw_name);
357 if (err) {
358 amdgpu_ucode_release(&adev->pm.fw);
359 return err;
360 }
361
362 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
363 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
364 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
365 ucode->fw = adev->pm.fw;
366 header = (const struct common_firmware_header *)ucode->fw->data;
367 adev->firmware.fw_size +=
368 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
369 }
370 }
371
372 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
373 amdgpu_ucode_print_smc_hdr(&hdr->header);
374 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
375 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
376 ucode_start_address = le32_to_cpu(hdr->ucode_start_addr);
377 src = (const uint8_t *)(adev->pm.fw->data +
378 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
379
380 info->version = adev->pm.fw_version;
381 info->image_size = ucode_size;
382 info->ucode_start_address = ucode_start_address;
383 info->kptr = (void *)src;
384 }
385 return 0;
386}
387
388static const struct cgs_ops amdgpu_cgs_ops = {
389 .read_register = amdgpu_cgs_read_register,
390 .write_register = amdgpu_cgs_write_register,
391 .read_ind_register = amdgpu_cgs_read_ind_register,
392 .write_ind_register = amdgpu_cgs_write_ind_register,
393 .get_firmware_info = amdgpu_cgs_get_firmware_info,
394};
395
396struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev)
397{
398 struct amdgpu_cgs_device *cgs_device = kmalloc_obj(*cgs_device);
399
400 if (!cgs_device) {
401 drm_err(adev_to_drm(adev), "Couldn't allocate CGS device structure\n");
402 return NULL;
403 }
404
405 cgs_device->base.ops = &amdgpu_cgs_ops;
406 cgs_device->adev = adev;
407
408 return (struct cgs_device *)cgs_device;
409}
410
411void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device)
412{
413 kfree(cgs_device);
414}