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1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright 2025 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24
25#ifndef __AMDGPU_CPER_H__
26#define __AMDGPU_CPER_H__
27
28#include "amd_cper.h"
29
30#define CPER_MAX_ALLOWED_COUNT 0x1000
31#define CPER_MAX_RING_SIZE 0X100000
32#define HDR_LEN (sizeof(struct cper_hdr))
33#define SEC_DESC_LEN (sizeof(struct cper_sec_desc))
34
35#define BOOT_SEC_LEN (sizeof(struct cper_sec_crashdump_boot))
36#define FATAL_SEC_LEN (sizeof(struct cper_sec_crashdump_fatal))
37#define NONSTD_SEC_LEN (sizeof(struct cper_sec_nonstd_err))
38
39#define SEC_DESC_OFFSET(idx) (HDR_LEN + (SEC_DESC_LEN * idx))
40
41#define BOOT_SEC_OFFSET(count, idx) (HDR_LEN + (SEC_DESC_LEN * count) + (BOOT_SEC_LEN * idx))
42#define FATAL_SEC_OFFSET(count, idx) (HDR_LEN + (SEC_DESC_LEN * count) + (FATAL_SEC_LEN * idx))
43#define NONSTD_SEC_OFFSET(count, idx) (HDR_LEN + (SEC_DESC_LEN * count) + (NONSTD_SEC_LEN * idx))
44
45enum amdgpu_cper_type {
46 AMDGPU_CPER_TYPE_RUNTIME,
47 AMDGPU_CPER_TYPE_FATAL,
48 AMDGPU_CPER_TYPE_BOOT,
49 AMDGPU_CPER_TYPE_BP_THRESHOLD,
50};
51
52struct amdgpu_cper {
53 bool enabled;
54
55 atomic_t unique_id;
56 struct mutex cper_lock;
57
58 /* Lifetime CPERs generated */
59 uint32_t count;
60 uint32_t max_count;
61
62 uint32_t wptr;
63
64 void *ring[CPER_MAX_ALLOWED_COUNT];
65 struct amdgpu_ring ring_buf;
66 struct mutex ring_lock;
67};
68
69void amdgpu_cper_entry_fill_hdr(struct amdgpu_device *adev,
70 struct cper_hdr *hdr,
71 enum amdgpu_cper_type type,
72 enum cper_error_severity sev);
73int amdgpu_cper_entry_fill_fatal_section(struct amdgpu_device *adev,
74 struct cper_hdr *hdr,
75 uint32_t idx,
76 struct cper_sec_crashdump_reg_data reg_data);
77int amdgpu_cper_entry_fill_runtime_section(struct amdgpu_device *adev,
78 struct cper_hdr *hdr,
79 uint32_t idx,
80 enum cper_error_severity sev,
81 uint32_t *reg_dump,
82 uint32_t reg_count);
83int amdgpu_cper_entry_fill_bad_page_threshold_section(struct amdgpu_device *adev,
84 struct cper_hdr *hdr,
85 uint32_t section_idx);
86
87struct cper_hdr *amdgpu_cper_alloc_entry(struct amdgpu_device *adev,
88 enum amdgpu_cper_type type,
89 uint16_t section_count);
90/* Bad page threshold is encoded into separated cper entry */
91int amdgpu_cper_generate_bp_threshold_record(struct amdgpu_device *adev);
92void amdgpu_cper_ring_write(struct amdgpu_ring *ring,
93 void *src, int count);
94int amdgpu_cper_init(struct amdgpu_device *adev);
95int amdgpu_cper_deferred_init(struct amdgpu_device *adev);
96int amdgpu_cper_fini(struct amdgpu_device *adev);
97
98#endif