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| 2 | * Copyright 2020 Advanced Micro Devices, Inc.
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| 3 | *
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a
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| 5 | * copy of this software and associated documentation files (the "Software"),
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| 6 | * to deal in the Software without restriction, including without limitation
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the
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| 9 | * Software is furnished to do so, subject to the following conditions:
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| 10 | *
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| 11 | * The above copyright notice and this permission notice shall be included in
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| 12 | * all copies or substantial portions of the Software.
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| 13 | *
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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| 20 | * OTHER DEALINGS IN THE SOFTWARE.
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| 21 | *
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| 22 |
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| 23 |
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| 24 | #ifndef __AMDGPU_DF_H__
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| 25 | #define __AMDGPU_DF_H__
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| 26 |
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| 27 | struct amdgpu_df_hash_status {
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| 28 | bool hash_64k;
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| 29 | bool hash_2m;
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| 30 | bool hash_1g;
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| 31 | };
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| 32 |
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| 33 | struct amdgpu_df_funcs {
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| 34 | void (*sw_init)(struct amdgpu_device *adev);
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| 35 | void (*sw_fini)(struct amdgpu_device *adev);
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| 36 | void (*hw_init)(struct amdgpu_device *adev);
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| 37 | void (*enable_broadcast_mode)(struct amdgpu_device *adev,
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| 38 | bool enable);
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| 39 | u32 (*get_fb_channel_number)(struct amdgpu_device *adev);
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| 40 | u32 (*get_hbm_channel_number)(struct amdgpu_device *adev);
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| 41 | void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
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| 42 | bool enable);
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| 43 | void (*get_clockgating_state)(struct amdgpu_device *adev,
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| 44 | u64 *flags);
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| 45 | void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev,
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| 46 | bool enable);
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| 47 | int (*pmc_start)(struct amdgpu_device *adev, uint64_t config,
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| 48 | int counter_idx, int is_add);
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| 49 | int (*pmc_stop)(struct amdgpu_device *adev, uint64_t config,
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| 50 | int counter_idx, int is_remove);
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| 51 | void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config,
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| 52 | int counter_idx, uint64_t *count);
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| 53 | uint64_t (*get_fica)(struct amdgpu_device *adev, uint32_t ficaa_val);
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| 54 | void (*set_fica)(struct amdgpu_device *adev, uint32_t ficaa_val,
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| 55 | uint32_t ficadl_val, uint32_t ficadh_val);
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| 56 | bool (*query_ras_poison_mode)(struct amdgpu_device *adev);
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| 57 | };
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| 58 |
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| 59 | struct amdgpu_df {
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| 60 | struct amdgpu_df_hash_status hash_status;
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| 61 | const struct amdgpu_df_funcs *funcs;
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| 62 | };
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| 63 |
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| 64 | #endif
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