| 1 | |
| 2 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
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| 3 | * All Rights Reserved.
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| 4 | *
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| 5 | * Permission is hereby granted, free of charge, to any person obtaining a
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| 6 | * copy of this software and associated documentation files (the "Software"),
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| 7 | * to deal in the Software without restriction, including without limitation
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| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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| 9 | * and/or sell copies of the Software, and to permit persons to whom the
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| 10 | * Software is furnished to do so, subject to the following conditions:
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| 11 | *
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| 12 | * The above copyright notice and this permission notice (including the next
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| 13 | * paragraph) shall be included in all copies or substantial portions of the
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| 14 | * Software.
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| 15 | *
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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| 19 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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| 22 | * OTHER DEALINGS IN THE SOFTWARE.
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| 23 |
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| 24 |
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| 25 | #include <drm/amdgpu_drm.h>
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| 26 | #include <drm/clients/drm_client_setup.h>
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| 27 | #include <drm/drm_drv.h>
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| 28 | #include <drm/drm_fbdev_ttm.h>
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| 29 | #include <drm/drm_gem.h>
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| 30 | #include <drm/drm_managed.h>
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| 31 | #include <drm/drm_pciids.h>
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| 32 | #include <drm/drm_probe_helper.h>
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| 33 | #include <drm/drm_vblank.h>
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| 34 |
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| 35 | #include <linux/cc_platform.h>
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| 36 | #include <linux/dynamic_debug.h>
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| 37 | #include <linux/module.h>
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| 38 | #include <linux/mmu_notifier.h>
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| 39 | #include <linux/pm_runtime.h>
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| 40 | #include <linux/suspend.h>
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| 41 | #include <linux/vga_switcheroo.h>
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| 42 |
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| 43 | #include "amdgpu.h"
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| 44 | #include "amdgpu_amdkfd.h"
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| 45 | #include "amdgpu_dma_buf.h"
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| 46 | #include "amdgpu_drv.h"
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| 47 | #include "amdgpu_fdinfo.h"
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| 48 | #include "amdgpu_irq.h"
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| 49 | #include "amdgpu_psp.h"
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| 50 | #include "amdgpu_ras.h"
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| 51 | #include "amdgpu_reset.h"
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| 52 | #include "amdgpu_sched.h"
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| 53 | #include "amdgpu_xgmi.h"
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| 54 | #include "amdgpu_userq.h"
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| 55 | #include "amdgpu_userq_fence.h"
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| 56 | #include "../amdxcp/amdgpu_xcp_drv.h"
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| 57 |
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| 58 | |
| 59 | * KMS wrapper.
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| 60 | * - 3.0.0 - initial driver
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| 61 | * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
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| 62 | * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
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| 63 | * at the end of IBs.
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| 64 | * - 3.3.0 - Add VM support for UVD on supported hardware.
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| 65 | * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
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| 66 | * - 3.5.0 - Add support for new UVD_NO_OP register.
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| 67 | * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
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| 68 | * - 3.7.0 - Add support for VCE clock list packet
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| 69 | * - 3.8.0 - Add support raster config init in the kernel
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| 70 | * - 3.9.0 - Add support for memory query info about VRAM and GTT.
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| 71 | * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
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| 72 | * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
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| 73 | * - 3.12.0 - Add query for double offchip LDS buffers
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| 74 | * - 3.13.0 - Add PRT support
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| 75 | * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
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| 76 | * - 3.15.0 - Export more gpu info for gfx9
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| 77 | * - 3.16.0 - Add reserved vmid support
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| 78 | * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
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| 79 | * - 3.18.0 - Export gpu always on cu bitmap
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| 80 | * - 3.19.0 - Add support for UVD MJPEG decode
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| 81 | * - 3.20.0 - Add support for local BOs
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| 82 | * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
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| 83 | * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
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| 84 | * - 3.23.0 - Add query for VRAM lost counter
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| 85 | * - 3.24.0 - Add high priority compute support for gfx9
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| 86 | * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
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| 87 | * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
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| 88 | * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation.
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| 89 | * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
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| 90 | * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
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| 91 | * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
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| 92 | * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
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| 93 | * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
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| 94 | * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
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| 95 | * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
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| 96 | * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
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| 97 | * - 3.36.0 - Allow reading more status registers on si/cik
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| 98 | * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness
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| 99 | * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC
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| 100 | * - 3.39.0 - DMABUF implicit sync does a full pipeline sync
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| 101 | * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ
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| 102 | * - 3.41.0 - Add video codec query
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| 103 | * - 3.42.0 - Add 16bpc fixed point display support
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| 104 | * - 3.43.0 - Add device hot plug/unplug support
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| 105 | * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B
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| 106 | * - 3.45.0 - Add context ioctl stable pstate interface
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| 107 | * - 3.46.0 - To enable hot plug amdgpu tests in libdrm
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| 108 | * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags
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| 109 | * - 3.48.0 - Add IP discovery version info to HW INFO
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| 110 | * - 3.49.0 - Add gang submit into CS IOCTL
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| 111 | * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock
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| 112 | * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock
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| 113 | * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl
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| 114 | * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields:
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| 115 | * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size,
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| 116 | * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi
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| 117 | * 3.53.0 - Support for GFX11 CP GFX shadowing
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| 118 | * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support
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| 119 | * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query
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| 120 | * - 3.56.0 - Update IB start address and size alignment for decode and encode
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| 121 | * - 3.57.0 - Compute tunneling on GFX10+
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| 122 | * - 3.58.0 - Add GFX12 DCC support
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| 123 | * - 3.59.0 - Cleared VRAM
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| 124 | * - 3.60.0 - Add AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE (Vulkan requirement)
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| 125 | * - 3.61.0 - Contains fix for RV/PCO compute queues
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| 126 | * - 3.62.0 - Add AMDGPU_IDS_FLAGS_MODE_PF, AMDGPU_IDS_FLAGS_MODE_VF & AMDGPU_IDS_FLAGS_MODE_PT
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| 127 | * - 3.63.0 - GFX12 display DCC supports 256B max compressed block size
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| 128 | * - 3.64.0 - Userq IP support query
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| 129 |
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| 130 | #define KMS_DRIVER_MAJOR 3
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| 131 | #define KMS_DRIVER_MINOR 64
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| 132 | #define KMS_DRIVER_PATCHLEVEL 0
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| 133 |
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| 134 | |
| 135 | * amdgpu.debug module options. Are all disabled by default
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| 136 |
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| 137 | enum AMDGPU_DEBUG_MASK {
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| 138 | AMDGPU_DEBUG_VM = BIT(0),
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| 139 | AMDGPU_DEBUG_LARGEBAR = BIT(1),
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| 140 | AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2),
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| 141 | AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3),
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| 142 | AMDGPU_DEBUG_ENABLE_EXP_RESETS = BIT(5),
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| 143 | AMDGPU_DEBUG_DISABLE_GPU_RING_RESET = BIT(6),
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| 144 | AMDGPU_DEBUG_SMU_POOL = BIT(7),
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| 145 | AMDGPU_DEBUG_VM_USERPTR = BIT(8),
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| 146 | AMDGPU_DEBUG_DISABLE_RAS_CE_LOG = BIT(9),
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| 147 | AMDGPU_DEBUG_ENABLE_CE_CS = BIT(10),
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| 148 | AMDGPU_DEBUG_HIBERNATION_THAW_RESUME_GPU = BIT(11),
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| 149 | AMDGPU_DEBUG_DISABLE_IP_BLOCK_SOFT_RESET = BIT(12),
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| 150 | };
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| 151 |
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| 152 | unsigned int amdgpu_vram_limit = UINT_MAX;
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| 153 | int amdgpu_vis_vram_limit;
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| 154 | int amdgpu_gart_size = -1;
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| 155 | int amdgpu_gtt_size = -1;
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| 156 | int amdgpu_moverate = -1;
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| 157 | int amdgpu_audio = -1;
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| 158 | int amdgpu_disp_priority;
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| 159 | int amdgpu_hw_i2c;
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| 160 | int amdgpu_pcie_gen2 = -1;
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| 161 | int amdgpu_msi = -1;
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| 162 | char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
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| 163 | int amdgpu_dpm = -1;
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| 164 | int amdgpu_fw_load_type = -1;
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| 165 | int amdgpu_aspm = -1;
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| 166 | int amdgpu_runtime_pm = -1;
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| 167 | uint amdgpu_ip_block_mask = 0xffffffff;
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| 168 | int amdgpu_bapm = -1;
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| 169 | int amdgpu_deep_color;
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| 170 | int amdgpu_vm_size = -1;
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| 171 | int amdgpu_vm_fragment_size = -1;
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| 172 | int amdgpu_vm_block_size = -1;
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| 173 | int amdgpu_vm_fault_stop;
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| 174 | int amdgpu_vm_update_mode = -1;
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| 175 | int amdgpu_exp_hw_support;
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| 176 | int amdgpu_dc = -1;
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| 177 | int amdgpu_sched_jobs = 32;
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| 178 | int amdgpu_sched_hw_submission = 2;
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| 179 | uint amdgpu_pcie_gen_cap;
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| 180 | uint amdgpu_pcie_lane_cap;
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| 181 | u64 amdgpu_cg_mask = 0xffffffffffffffff;
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| 182 | uint amdgpu_pg_mask = 0xffffffff;
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| 183 | uint amdgpu_sdma_phase_quantum = 32;
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| 184 | char *amdgpu_disable_cu;
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| 185 | char *amdgpu_virtual_display;
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| 186 | int amdgpu_enforce_isolation = -1;
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| 187 | int amdgpu_modeset = -1;
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| 188 |
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| 189 | |
| 190 | * migration and restoration of backing memory when handling
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| 191 | * recoverable page faults.
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| 192 | *
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| 193 | * The value is given as log(numPages(buffer)); for a 2 MiB
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| 194 | * buffer it computes to be 9
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| 195 |
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| 196 | uint amdgpu_svm_default_granularity = 9;
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| 197 |
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| 198 | |
| 199 | * OverDrive(bit 14) disabled by default
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| 200 | * GFX DCS(bit 19) disabled by default
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| 201 |
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| 202 | uint amdgpu_pp_feature_mask = 0xfff7bfff;
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| 203 | uint amdgpu_force_long_training;
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| 204 | int amdgpu_lbpw = -1;
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| 205 | int amdgpu_compute_multipipe = -1;
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| 206 | int amdgpu_gpu_recovery = -1;
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| 207 | int amdgpu_emu_mode;
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| 208 | uint amdgpu_smu_memory_pool_size;
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| 209 | int amdgpu_smu_pptable_id = -1;
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| 210 | |
| 211 | * FBC (bit 0) disabled by default
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| 212 | * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default
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| 213 | * - With this, for multiple monitors in sync(e.g. with the same model),
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| 214 | * mclk switching will be allowed. And the mclk will be not foced to the
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| 215 | * highest. That helps saving some idle power.
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| 216 | * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default
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| 217 | * PSR (bit 3) disabled by default
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| 218 | * EDP NO POWER SEQUENCING (bit 4) disabled by default
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| 219 |
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| 220 | uint amdgpu_dc_feature_mask = 2;
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| 221 | uint amdgpu_dc_debug_mask;
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| 222 | uint amdgpu_dc_visual_confirm;
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| 223 | int amdgpu_async_gfx_ring = 1;
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| 224 | int amdgpu_mcbp = -1;
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| 225 | int amdgpu_discovery = -1;
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| 226 | int amdgpu_mes_log_enable = 0;
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| 227 | int amdgpu_uni_mes = 1;
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| 228 | int amdgpu_noretry = -1;
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| 229 | int amdgpu_force_asic_type = -1;
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| 230 | int amdgpu_tmz = -1;
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| 231 | uint amdgpu_freesync_vid_mode;
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| 232 | int amdgpu_reset_method = -1;
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| 233 | int amdgpu_num_kcq = -1;
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| 234 | int amdgpu_smartshift_bias;
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| 235 | int amdgpu_use_xgmi_p2p = 1;
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| 236 | int amdgpu_vcnfw_log;
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| 237 | int amdgpu_sg_display = -1;
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| 238 | int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE;
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| 239 | int amdgpu_umsch_mm;
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| 240 | int amdgpu_seamless = -1;
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| 241 | uint amdgpu_debug_mask;
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| 242 | int amdgpu_agp = -1;
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| 243 | int amdgpu_wbrf = -1;
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| 244 | int amdgpu_damage_clips = -1;
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| 245 | int amdgpu_umsch_mm_fwlog;
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| 246 | int amdgpu_rebar = -1;
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| 247 | int amdgpu_user_queue = -1;
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| 248 | uint amdgpu_hdmi_hpd_debounce_delay_ms;
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| 249 | int amdgpu_ptl = -1;
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| 250 |
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| 251 | DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
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| 252 | "DRM_UT_CORE",
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| 253 | "DRM_UT_DRIVER",
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| 254 | "DRM_UT_KMS",
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| 255 | "DRM_UT_PRIME",
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| 256 | "DRM_UT_ATOMIC",
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| 257 | "DRM_UT_VBL",
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| 258 | "DRM_UT_STATE",
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| 259 | "DRM_UT_LEASE",
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| 260 | "DRM_UT_DP",
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| 261 | "DRM_UT_DRMRES");
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| 262 |
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| 263 | struct amdgpu_mgpu_info mgpu_info = {
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| 264 | .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
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| 265 | };
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| 266 | int amdgpu_ras_enable = -1;
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| 267 | uint amdgpu_ras_mask = 0xffffffff;
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| 268 | int amdgpu_bad_page_threshold = -1;
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| 269 | struct amdgpu_watchdog_timer amdgpu_watchdog_timer = {
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| 270 | .timeout_fatal_disable = false,
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| 271 | .period = 0x0,
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| 272 | };
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| 273 |
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| 274 | |
| 275 | * DOC: vramlimit (int)
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| 276 | * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM).
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| 277 |
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| 278 | MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
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| 279 | module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
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| 280 |
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| 281 | |
| 282 | * DOC: vis_vramlimit (int)
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| 283 | * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM).
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| 284 |
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| 285 | MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
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| 286 | module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
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| 287 |
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| 288 | |
| 289 | * DOC: gartsize (uint)
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| 290 | * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing.
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| 291 | * The default is -1 (The size depends on asic).
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| 292 |
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| 293 | MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)");
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| 294 | module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
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| 295 |
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| 296 | |
| 297 | * DOC: gttsize (int)
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| 298 | * Restrict the size of GTT domain (for userspace use) in MiB for testing.
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| 299 | * The default is -1 (Use value specified by TTM).
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| 300 | * This parameter is deprecated and will be removed in the future.
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| 301 |
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| 302 | MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)");
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| 303 | module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
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| 304 |
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| 305 | |
| 306 | * DOC: moverate (int)
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| 307 | * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
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| 308 |
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| 309 | MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
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| 310 | module_param_named(moverate, amdgpu_moverate, int, 0600);
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| 311 |
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| 312 | |
| 313 | * DOC: audio (int)
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| 314 | * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it.
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| 315 |
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| 316 | MODULE_PARM_DESC(audio, "HDMI/DP Audio enable for non DC displays (-1 = auto, 0 = disable, 1 = enable)");
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| 317 | module_param_named(audio, amdgpu_audio, int, 0444);
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| 318 |
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| 319 | |
| 320 | * DOC: disp_priority (int)
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| 321 | * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto).
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| 322 |
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| 323 | MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
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| 324 | module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
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| 325 |
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| 326 | |
| 327 | * DOC: hw_i2c (int)
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| 328 | * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled).
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| 329 |
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| 330 | MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
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| 331 | module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
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| 332 |
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| 333 | |
| 334 | * DOC: pcie_gen2 (int)
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| 335 | * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled).
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| 336 |
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| 337 | MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
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| 338 | module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
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| 339 |
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| 340 | |
| 341 | * DOC: msi (int)
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| 342 | * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled).
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| 343 |
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| 344 | MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
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| 345 | module_param_named(msi, amdgpu_msi, int, 0444);
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| 346 |
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| 347 | |
| 348 | * DOC: svm_default_granularity (uint)
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| 349 | * Used in buffer migration and handling of recoverable page faults
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| 350 |
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| 351 | MODULE_PARM_DESC(svm_default_granularity, "SVM's default granularity in log(2^Pages), default 9 = 2^9 = 2 MiB");
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| 352 | module_param_named(svm_default_granularity, amdgpu_svm_default_granularity, uint, 0644);
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| 353 |
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| 354 | |
| 355 | * DOC: lockup_timeout (string)
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| 356 | * Set GPU scheduler timeout value in ms.
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| 357 | *
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| 358 | * The format can be [single value] for setting all timeouts at once or
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| 359 | * [GFX,Compute,SDMA,Video] to set individual timeouts.
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| 360 | * Negative values mean infinity.
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| 361 | *
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| 362 | * By default(with no lockup_timeout settings), the timeout for all queues is 2000.
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| 363 |
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| 364 | MODULE_PARM_DESC(lockup_timeout,
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| 365 | "GPU lockup timeout in ms (default: 2000. 0: keep default value. negative: infinity timeout), format: [single value for all] or [GFX,Compute,SDMA,Video].");
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| 366 | module_param_string(lockup_timeout, amdgpu_lockup_timeout,
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| 367 | sizeof(amdgpu_lockup_timeout), 0444);
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| 368 |
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| 369 | |
| 370 | * DOC: dpm (int)
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| 371 | * Override for dynamic power management setting
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| 372 | * (0 = disable, 1 = enable)
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| 373 | * The default is -1 (auto).
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| 374 |
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| 375 | MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
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| 376 | module_param_named(dpm, amdgpu_dpm, int, 0444);
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| 377 |
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| 378 | |
| 379 | * DOC: fw_load_type (int)
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| 380 | * Set different firmware loading type for debugging, if supported.
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| 381 | * Set to 0 to force direct loading if supported by the ASIC. Set
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| 382 | * to -1 to select the default loading mode for the ASIC, as defined
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| 383 | * by the driver. The default is -1 (auto).
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| 384 |
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| 385 | MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)");
|
| 386 | module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
|
| 387 |
|
| 388 | |
| 389 | * DOC: aspm (int)
|
| 390 | * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled).
|
| 391 |
|
| 392 | MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
|
| 393 | module_param_named(aspm, amdgpu_aspm, int, 0444);
|
| 394 |
|
| 395 | |
| 396 | * DOC: runpm (int)
|
| 397 | * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down
|
| 398 | * the dGPUs when they are idle if supported. The default is -1 (auto enable).
|
| 399 | * Setting the value to 0 disables this functionality.
|
| 400 | * Setting the value to -2 is auto enabled with power down when displays are attached.
|
| 401 |
|
| 402 | MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = auto with displays)");
|
| 403 | module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
|
| 404 |
|
| 405 | |
| 406 | * DOC: ip_block_mask (uint)
|
| 407 | * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.).
|
| 408 | * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have
|
| 409 | * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in
|
| 410 | * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device).
|
| 411 |
|
| 412 | MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
|
| 413 | module_param_named_unsafe(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
|
| 414 |
|
| 415 | |
| 416 | * DOC: bapm (int)
|
| 417 | * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it.
|
| 418 | * The default -1 (auto, enabled)
|
| 419 |
|
| 420 | MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
|
| 421 | module_param_named(bapm, amdgpu_bapm, int, 0444);
|
| 422 |
|
| 423 | |
| 424 | * DOC: deep_color (int)
|
| 425 | * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled).
|
| 426 |
|
| 427 | MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
|
| 428 | module_param_named(deep_color, amdgpu_deep_color, int, 0444);
|
| 429 |
|
| 430 | |
| 431 | * DOC: vm_size (int)
|
| 432 | * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic).
|
| 433 |
|
| 434 | MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
|
| 435 | module_param_named(vm_size, amdgpu_vm_size, int, 0444);
|
| 436 |
|
| 437 | |
| 438 | * DOC: vm_fragment_size (int)
|
| 439 | * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic).
|
| 440 |
|
| 441 | MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
|
| 442 | module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
|
| 443 |
|
| 444 | |
| 445 | * DOC: vm_block_size (int)
|
| 446 | * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic).
|
| 447 |
|
| 448 | MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
|
| 449 | module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
|
| 450 |
|
| 451 | |
| 452 | * DOC: vm_fault_stop (int)
|
| 453 | * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop).
|
| 454 |
|
| 455 | MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
|
| 456 | module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
|
| 457 |
|
| 458 | |
| 459 | * DOC: vm_update_mode (int)
|
| 460 | * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default
|
| 461 | * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never).
|
| 462 |
|
| 463 | MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
|
| 464 | module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
|
| 465 |
|
| 466 | |
| 467 | * DOC: exp_hw_support (int)
|
| 468 | * Enable experimental hw support (1 = enable). The default is 0 (disabled).
|
| 469 |
|
| 470 | MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
|
| 471 | module_param_named_unsafe(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
|
| 472 |
|
| 473 | |
| 474 | * DOC: dc (int)
|
| 475 | * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic).
|
| 476 |
|
| 477 | MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
|
| 478 | module_param_named(dc, amdgpu_dc, int, 0444);
|
| 479 |
|
| 480 | |
| 481 | * DOC: sched_jobs (int)
|
| 482 | * Override the max number of jobs supported in the sw queue. The default is 32.
|
| 483 |
|
| 484 | MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
|
| 485 | module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
|
| 486 |
|
| 487 | |
| 488 | * DOC: sched_hw_submission (int)
|
| 489 | * Override the max number of HW submissions. The default is 2.
|
| 490 |
|
| 491 | MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
|
| 492 | module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
|
| 493 |
|
| 494 | |
| 495 | * DOC: ppfeaturemask (hexint)
|
| 496 | * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
|
| 497 | * The default is the current set of stable power features.
|
| 498 |
|
| 499 | MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
|
| 500 | module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444);
|
| 501 |
|
| 502 | |
| 503 | * DOC: forcelongtraining (uint)
|
| 504 | * Force long memory training in resume.
|
| 505 | * The default is zero, indicates short training in resume.
|
| 506 |
|
| 507 | MODULE_PARM_DESC(forcelongtraining, "force memory long training");
|
| 508 | module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444);
|
| 509 |
|
| 510 | |
| 511 | * DOC: pcie_gen_cap (uint)
|
| 512 | * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
|
| 513 | * The default is 0 (automatic for each asic).
|
| 514 |
|
| 515 | MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
|
| 516 | module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
|
| 517 |
|
| 518 | |
| 519 | * DOC: pcie_lane_cap (uint)
|
| 520 | * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
|
| 521 | * The default is 0 (automatic for each asic).
|
| 522 |
|
| 523 | MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
|
| 524 | module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
|
| 525 |
|
| 526 | |
| 527 | * DOC: cg_mask (ullong)
|
| 528 | * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in
|
| 529 | * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled).
|
| 530 |
|
| 531 | MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
|
| 532 | module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444);
|
| 533 |
|
| 534 | |
| 535 | * DOC: pg_mask (uint)
|
| 536 | * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in
|
| 537 | * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
|
| 538 |
|
| 539 | MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
|
| 540 | module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
|
| 541 |
|
| 542 | |
| 543 | * DOC: sdma_phase_quantum (uint)
|
| 544 | * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32.
|
| 545 |
|
| 546 | MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
|
| 547 | module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
|
| 548 |
|
| 549 | |
| 550 | * DOC: disable_cu (charp)
|
| 551 | * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL.
|
| 552 |
|
| 553 | MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
|
| 554 | module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
|
| 555 |
|
| 556 | |
| 557 | * DOC: virtual_display (charp)
|
| 558 | * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards
|
| 559 | * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of
|
| 560 | * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci
|
| 561 | * device at 26:00.0. The default is NULL.
|
| 562 |
|
| 563 | MODULE_PARM_DESC(virtual_display,
|
| 564 | "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
|
| 565 | module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
|
| 566 |
|
| 567 | |
| 568 | * DOC: lbpw (int)
|
| 569 | * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled).
|
| 570 |
|
| 571 | MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
|
| 572 | module_param_named(lbpw, amdgpu_lbpw, int, 0444);
|
| 573 |
|
| 574 | MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
|
| 575 | module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
|
| 576 |
|
| 577 | |
| 578 | * DOC: gpu_recovery (int)
|
| 579 | * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV).
|
| 580 |
|
| 581 | MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)");
|
| 582 | module_param_named_unsafe(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
|
| 583 |
|
| 584 | |
| 585 | * DOC: emu_mode (int)
|
| 586 | * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).
|
| 587 |
|
| 588 | MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
|
| 589 | module_param_named_unsafe(emu_mode, amdgpu_emu_mode, int, 0444);
|
| 590 |
|
| 591 | |
| 592 | * DOC: ras_enable (int)
|
| 593 | * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))
|
| 594 |
|
| 595 | MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
|
| 596 | module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);
|
| 597 |
|
| 598 | |
| 599 | * DOC: ras_mask (uint)
|
| 600 | * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1
|
| 601 | * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
|
| 602 |
|
| 603 | MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
|
| 604 | module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
|
| 605 |
|
| 606 | |
| 607 | * DOC: timeout_fatal_disable (bool)
|
| 608 | * Disable Watchdog timeout fatal error event
|
| 609 |
|
| 610 | MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)");
|
| 611 | module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644);
|
| 612 |
|
| 613 | |
| 614 | * DOC: timeout_period (uint)
|
| 615 | * Modify the watchdog timeout max_cycles as (1 << period)
|
| 616 |
|
| 617 | MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)");
|
| 618 | module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644);
|
| 619 |
|
| 620 | |
| 621 | * DOC: si_support (int)
|
| 622 | * 1 = enabled, 0 = disabled, -1 = default
|
| 623 | *
|
| 624 | * SI (Southern Islands) are first generation GCN GPUs, supported by both
|
| 625 | * drivers: radeon (old) and amdgpu (new). This parameter controls whether
|
| 626 | * amdgpu should support SI.
|
| 627 | * By default, SI dedicated GPUs are supported by amdgpu.
|
| 628 | * Only relevant when CONFIG_DRM_AMDGPU_SI is enabled to build SI support in amdgpu.
|
| 629 | * See also radeon.si_support which should be disabled when amdgpu.si_support is
|
| 630 | * enabled, and vice versa.
|
| 631 |
|
| 632 | int amdgpu_si_support = -1;
|
| 633 | #ifdef CONFIG_DRM_AMDGPU_SI
|
| 634 | MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled, -1 = default)");
|
| 635 | module_param_named(si_support, amdgpu_si_support, int, 0444);
|
| 636 | #endif
|
| 637 |
|
| 638 | |
| 639 | * DOC: cik_support (int)
|
| 640 | * 1 = enabled, 0 = disabled, -1 = default
|
| 641 | *
|
| 642 | * CIK (Sea Islands) are second generation GCN GPUs, supported by both
|
| 643 | * drivers: radeon (old) and amdgpu (new). This parameter controls whether
|
| 644 | * amdgpu should support CIK.
|
| 645 | * By default, CIK dedicated GPUs and APUs are supported by amdgpu.
|
| 646 | * Only relevant when CONFIG_DRM_AMDGPU_CIK is enabled to build CIK support in amdgpu.
|
| 647 | * See also radeon.cik_support which should be disabled when amdgpu.cik_support is
|
| 648 | * enabled, and vice versa.
|
| 649 |
|
| 650 | int amdgpu_cik_support = -1;
|
| 651 | #ifdef CONFIG_DRM_AMDGPU_CIK
|
| 652 | MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled, -1 = default)");
|
| 653 | module_param_named(cik_support, amdgpu_cik_support, int, 0444);
|
| 654 | #endif
|
| 655 |
|
| 656 | |
| 657 | * DOC: smu_memory_pool_size (uint)
|
| 658 | * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB.
|
| 659 | * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled).
|
| 660 |
|
| 661 | MODULE_PARM_DESC(smu_memory_pool_size,
|
| 662 | "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
|
| 663 | module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
|
| 664 |
|
| 665 | |
| 666 | * DOC: async_gfx_ring (int)
|
| 667 | * It is used to enable gfx rings that could be configured with different prioritites or equal priorities
|
| 668 |
|
| 669 | MODULE_PARM_DESC(async_gfx_ring,
|
| 670 | "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))");
|
| 671 | module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444);
|
| 672 |
|
| 673 | |
| 674 | * DOC: mcbp (int)
|
| 675 | * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default))
|
| 676 |
|
| 677 | MODULE_PARM_DESC(mcbp,
|
| 678 | "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)");
|
| 679 | module_param_named(mcbp, amdgpu_mcbp, int, 0444);
|
| 680 |
|
| 681 | |
| 682 | * DOC: discovery (int)
|
| 683 | * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM.
|
| 684 | * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file)
|
| 685 |
|
| 686 | MODULE_PARM_DESC(discovery,
|
| 687 | "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM");
|
| 688 | module_param_named(discovery, amdgpu_discovery, int, 0444);
|
| 689 |
|
| 690 | |
| 691 | * DOC: mes_log_enable (int)
|
| 692 | * Enable Micro Engine Scheduler log. This is used to enable/disable MES internal log.
|
| 693 | * (0 = disabled (default), 1 = enabled)
|
| 694 |
|
| 695 | MODULE_PARM_DESC(mes_log_enable,
|
| 696 | "Enable Micro Engine Scheduler log (0 = disabled (default), 1 = enabled)");
|
| 697 | module_param_named(mes_log_enable, amdgpu_mes_log_enable, int, 0444);
|
| 698 |
|
| 699 | |
| 700 | * DOC: uni_mes (int)
|
| 701 | * Enable Unified Micro Engine Scheduler. This is a new engine pipe for unified scheduler.
|
| 702 | * (0 = disabled (default), 1 = enabled)
|
| 703 |
|
| 704 | MODULE_PARM_DESC(uni_mes,
|
| 705 | "Enable Unified Micro Engine Scheduler (0 = disabled, 1 = enabled(default)");
|
| 706 | module_param_named(uni_mes, amdgpu_uni_mes, int, 0444);
|
| 707 |
|
| 708 | |
| 709 | * DOC: noretry (int)
|
| 710 | * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that
|
| 711 | * do not support per-process XNACK this also disables retry page faults.
|
| 712 | * (0 = retry enabled, 1 = retry disabled, -1 auto (default))
|
| 713 |
|
| 714 | MODULE_PARM_DESC(noretry,
|
| 715 | "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))");
|
| 716 | module_param_named(noretry, amdgpu_noretry, int, 0644);
|
| 717 |
|
| 718 | |
| 719 | * DOC: force_asic_type (int)
|
| 720 | * A non negative value used to specify the asic type for all supported GPUs.
|
| 721 |
|
| 722 | MODULE_PARM_DESC(force_asic_type,
|
| 723 | "A non negative value used to specify the asic type for all supported GPUs");
|
| 724 | module_param_named_unsafe(force_asic_type, amdgpu_force_asic_type, int, 0444);
|
| 725 |
|
| 726 | |
| 727 | * DOC: use_xgmi_p2p (int)
|
| 728 | * Enables/disables XGMI P2P interface (0 = disable, 1 = enable).
|
| 729 |
|
| 730 | MODULE_PARM_DESC(use_xgmi_p2p,
|
| 731 | "Enable XGMI P2P interface (0 = disable; 1 = enable (default))");
|
| 732 | module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444);
|
| 733 |
|
| 734 |
|
| 735 | #ifdef CONFIG_HSA_AMD
|
| 736 | |
| 737 | * DOC: sched_policy (int)
|
| 738 | * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription.
|
| 739 | * Setting 1 disables over-subscription. Setting 2 disables HWS and statically
|
| 740 | * assigns queues to HQDs.
|
| 741 |
|
| 742 | int sched_policy = KFD_SCHED_POLICY_HWS;
|
| 743 | module_param_unsafe(sched_policy, int, 0444);
|
| 744 | MODULE_PARM_DESC(sched_policy,
|
| 745 | "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
|
| 746 |
|
| 747 | |
| 748 | * DOC: hws_max_conc_proc (int)
|
| 749 | * Maximum number of processes that HWS can schedule concurrently. The maximum is the
|
| 750 | * number of VMIDs assigned to the HWS, which is also the default.
|
| 751 |
|
| 752 | int hws_max_conc_proc = -1;
|
| 753 | module_param(hws_max_conc_proc, int, 0444);
|
| 754 | MODULE_PARM_DESC(hws_max_conc_proc,
|
| 755 | "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))");
|
| 756 |
|
| 757 | |
| 758 | * DOC: cwsr_enable (int)
|
| 759 | * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in
|
| 760 | * the middle of a compute wave. Default is 1 to enable this feature. Setting 0
|
| 761 | * disables it.
|
| 762 |
|
| 763 | int cwsr_enable = 1;
|
| 764 | module_param(cwsr_enable, int, 0444);
|
| 765 | MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))");
|
| 766 |
|
| 767 | |
| 768 | * DOC: max_num_of_queues_per_device (int)
|
| 769 | * Maximum number of queues per device. Valid setting is between 1 and 4096. Default
|
| 770 | * is 4096.
|
| 771 |
|
| 772 | int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT;
|
| 773 | module_param(max_num_of_queues_per_device, int, 0444);
|
| 774 | MODULE_PARM_DESC(max_num_of_queues_per_device,
|
| 775 | "Maximum number of supported queues per device (1 = Minimum, 4096 = default)");
|
| 776 |
|
| 777 | |
| 778 | * DOC: send_sigterm (int)
|
| 779 | * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm
|
| 780 | * but just print errors on dmesg. Setting 1 enables sending sigterm.
|
| 781 |
|
| 782 | int send_sigterm;
|
| 783 | module_param(send_sigterm, int, 0444);
|
| 784 | MODULE_PARM_DESC(send_sigterm,
|
| 785 | "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)");
|
| 786 |
|
| 787 | |
| 788 | * DOC: halt_if_hws_hang (int)
|
| 789 | * Halt if HWS hang is detected. Default value, 0, disables the halt on hang.
|
| 790 | * Setting 1 enables halt on hang.
|
| 791 |
|
| 792 | int halt_if_hws_hang;
|
| 793 | module_param_unsafe(halt_if_hws_hang, int, 0644);
|
| 794 | MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
|
| 795 |
|
| 796 | |
| 797 | * DOC: hws_gws_support(bool)
|
| 798 | * Assume that HWS supports GWS barriers regardless of what firmware version
|
| 799 | * check says. Default value: false (rely on MEC2 firmware version check).
|
| 800 |
|
| 801 | bool hws_gws_support;
|
| 802 | module_param_unsafe(hws_gws_support, bool, 0444);
|
| 803 | MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)");
|
| 804 |
|
| 805 | |
| 806 | * DOC: queue_preemption_timeout_ms (int)
|
| 807 | * queue preemption timeout in ms (1 = Minimum, 9000 = default)
|
| 808 |
|
| 809 | int queue_preemption_timeout_ms = 9000;
|
| 810 | module_param(queue_preemption_timeout_ms, int, 0644);
|
| 811 | MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)");
|
| 812 |
|
| 813 | |
| 814 | * DOC: debug_evictions(bool)
|
| 815 | * Enable extra debug messages to help determine the cause of evictions
|
| 816 |
|
| 817 | bool debug_evictions;
|
| 818 | module_param(debug_evictions, bool, 0644);
|
| 819 | MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)");
|
| 820 |
|
| 821 | |
| 822 | * DOC: no_system_mem_limit(bool)
|
| 823 | * Disable system memory limit, to support multiple process shared memory
|
| 824 |
|
| 825 | bool no_system_mem_limit;
|
| 826 | module_param(no_system_mem_limit, bool, 0644);
|
| 827 | MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)");
|
| 828 |
|
| 829 | |
| 830 | * DOC: no_queue_eviction_on_vm_fault (int)
|
| 831 | * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction).
|
| 832 |
|
| 833 | int amdgpu_no_queue_eviction_on_vm_fault;
|
| 834 | MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)");
|
| 835 | module_param_named_unsafe(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444);
|
| 836 | #endif
|
| 837 |
|
| 838 | |
| 839 | * DOC: mtype_local (int)
|
| 840 |
|
| 841 | int amdgpu_mtype_local = -1;
|
| 842 | MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (default: ASIC dependent, 0 = MTYPE_RW, 1 = MTYPE_NC, 2 = MTYPE_CC)");
|
| 843 | module_param_named_unsafe(mtype_local, amdgpu_mtype_local, int, 0444);
|
| 844 |
|
| 845 | |
| 846 | * DOC: pcie_p2p (bool)
|
| 847 | * Enable PCIe P2P (requires large-BAR). Default value: true (on)
|
| 848 |
|
| 849 | #ifdef CONFIG_HSA_AMD_P2P
|
| 850 | bool pcie_p2p = true;
|
| 851 | module_param(pcie_p2p, bool, 0444);
|
| 852 | MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))");
|
| 853 | #endif
|
| 854 |
|
| 855 | |
| 856 | * DOC: dcfeaturemask (uint)
|
| 857 | * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
|
| 858 | * The default is the current set of stable display features.
|
| 859 |
|
| 860 | MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))");
|
| 861 | module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);
|
| 862 |
|
| 863 | |
| 864 | * DOC: dcdebugmask (uint)
|
| 865 | * Display debug options. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
|
| 866 |
|
| 867 | MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))");
|
| 868 | module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444);
|
| 869 |
|
| 870 | MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)");
|
| 871 | module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444);
|
| 872 |
|
| 873 | |
| 874 | * DOC: abmlevel (uint)
|
| 875 | * Override the default ABM (Adaptive Backlight Management) level used for DC
|
| 876 | * enabled hardware. Requires DMCU to be supported and loaded.
|
| 877 | * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by
|
| 878 | * default. Values 1-4 control the maximum allowable brightness reduction via
|
| 879 | * the ABM algorithm, with 1 being the least reduction and 4 being the most
|
| 880 | * reduction.
|
| 881 | *
|
| 882 | * Defaults to -1, or auto. Userspace can only override this level after
|
| 883 | * boot if it's set to auto.
|
| 884 |
|
| 885 | int amdgpu_dm_abm_level = -1;
|
| 886 | MODULE_PARM_DESC(abmlevel,
|
| 887 | "ABM level (0 = off, 1-4 = backlight reduction level, -1 auto (default))");
|
| 888 | module_param_named(abmlevel, amdgpu_dm_abm_level, int, 0444);
|
| 889 |
|
| 890 | int amdgpu_backlight = -1;
|
| 891 | MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))");
|
| 892 | module_param_named(backlight, amdgpu_backlight, bint, 0444);
|
| 893 |
|
| 894 | |
| 895 | * DOC: damageclips (int)
|
| 896 | * Enable or disable damage clips support. If damage clips support is disabled,
|
| 897 | * we will force full frame updates, irrespective of what user space sends to
|
| 898 | * us.
|
| 899 | *
|
| 900 | * Defaults to -1 (where it is enabled unless a PSR-SU display is detected).
|
| 901 |
|
| 902 | MODULE_PARM_DESC(damageclips,
|
| 903 | "Damage clips support (0 = disable, 1 = enable, -1 auto (default))");
|
| 904 | module_param_named(damageclips, amdgpu_damage_clips, int, 0444);
|
| 905 |
|
| 906 | |
| 907 | * DOC: tmz (int)
|
| 908 | * Trusted Memory Zone (TMZ) is a method to protect data being written
|
| 909 | * to or read from memory.
|
| 910 | *
|
| 911 | * The default value: 0 (off). TODO: change to auto till it is completed.
|
| 912 |
|
| 913 | MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)");
|
| 914 | module_param_named(tmz, amdgpu_tmz, int, 0444);
|
| 915 |
|
| 916 | |
| 917 | * DOC: freesync_video (uint)
|
| 918 | * Enable the optimization to adjust front porch timing to achieve seamless
|
| 919 | * mode change experience when setting a freesync supported mode for which full
|
| 920 | * modeset is not needed.
|
| 921 | *
|
| 922 | * The Display Core will add a set of modes derived from the base FreeSync
|
| 923 | * video mode into the corresponding connector's mode list based on commonly
|
| 924 | * used refresh rates and VRR range of the connected display, when users enable
|
| 925 | * this feature. From the userspace perspective, they can see a seamless mode
|
| 926 | * change experience when the change between different refresh rates under the
|
| 927 | * same resolution. Additionally, userspace applications such as Video playback
|
| 928 | * can read this modeset list and change the refresh rate based on the video
|
| 929 | * frame rate. Finally, the userspace can also derive an appropriate mode for a
|
| 930 | * particular refresh rate based on the FreeSync Mode and add it to the
|
| 931 | * connector's mode list.
|
| 932 | *
|
| 933 | * Note: This is an experimental feature.
|
| 934 | *
|
| 935 | * The default value: 0 (off).
|
| 936 |
|
| 937 | MODULE_PARM_DESC(
|
| 938 | freesync_video,
|
| 939 | "Adds additional modes via VRR for refresh changes without a full modeset (0 = off (default), 1 = on)");
|
| 940 | module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444);
|
| 941 |
|
| 942 | |
| 943 | * DOC: reset_method (int)
|
| 944 | * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)
|
| 945 |
|
| 946 | MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)");
|
| 947 | module_param_named_unsafe(reset_method, amdgpu_reset_method, int, 0644);
|
| 948 |
|
| 949 | |
| 950 | * DOC: bad_page_threshold (int) Bad page threshold is specifies the
|
| 951 | * threshold value of faulty pages detected by RAS ECC, which may
|
| 952 | * result in the GPU entering bad status when the number of total
|
| 953 | * faulty pages by ECC exceeds the threshold value.
|
| 954 |
|
| 955 | MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = threshold determined by a formula, 0 < threshold < max records, user-defined threshold)");
|
| 956 | module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444);
|
| 957 |
|
| 958 | MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)");
|
| 959 | module_param_named(num_kcq, amdgpu_num_kcq, int, 0444);
|
| 960 |
|
| 961 | |
| 962 | * DOC: vcnfw_log (int)
|
| 963 | * Enable vcnfw log output for debugging, the default is disabled.
|
| 964 |
|
| 965 | MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)");
|
| 966 | module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444);
|
| 967 |
|
| 968 | |
| 969 | * DOC: sg_display (int)
|
| 970 | * Disable S/G (scatter/gather) display (i.e., display from system memory).
|
| 971 | * This option is only relevant on APUs. Set this option to 0 to disable
|
| 972 | * S/G display if you experience flickering or other issues under memory
|
| 973 | * pressure and report the issue.
|
| 974 |
|
| 975 | MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)");
|
| 976 | module_param_named(sg_display, amdgpu_sg_display, int, 0444);
|
| 977 |
|
| 978 | |
| 979 | * DOC: umsch_mm (int)
|
| 980 | * Enable Multi Media User Mode Scheduler. This is a HW scheduling engine for VCN and VPE.
|
| 981 | * (0 = disabled (default), 1 = enabled)
|
| 982 |
|
| 983 | MODULE_PARM_DESC(umsch_mm,
|
| 984 | "Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled)");
|
| 985 | module_param_named(umsch_mm, amdgpu_umsch_mm, int, 0444);
|
| 986 |
|
| 987 | |
| 988 | * DOC: umsch_mm_fwlog (int)
|
| 989 | * Enable umschfw log output for debugging, the default is disabled.
|
| 990 |
|
| 991 | MODULE_PARM_DESC(umsch_mm_fwlog, "Enable umschfw log(0 = disable (default value), 1 = enable)");
|
| 992 | module_param_named(umsch_mm_fwlog, amdgpu_umsch_mm_fwlog, int, 0444);
|
| 993 |
|
| 994 | |
| 995 | * DOC: smu_pptable_id (int)
|
| 996 | * Used to override pptable id. id = 0 use VBIOS pptable.
|
| 997 | * id > 0 use the soft pptable with specicfied id.
|
| 998 |
|
| 999 | MODULE_PARM_DESC(smu_pptable_id,
|
| 1000 | "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)");
|
| 1001 | module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444);
|
| 1002 |
|
| 1003 | |
| 1004 | * DOC: partition_mode (int)
|
| 1005 | * Used to override the default SPX mode.
|
| 1006 |
|
| 1007 | MODULE_PARM_DESC(
|
| 1008 | user_partt_mode,
|
| 1009 | "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \
|
| 1010 | 0 = AMDGPU_SPX_PARTITION_MODE, \
|
| 1011 | 1 = AMDGPU_DPX_PARTITION_MODE, \
|
| 1012 | 2 = AMDGPU_TPX_PARTITION_MODE, \
|
| 1013 | 3 = AMDGPU_QPX_PARTITION_MODE, \
|
| 1014 | 4 = AMDGPU_CPX_PARTITION_MODE)");
|
| 1015 | module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444);
|
| 1016 |
|
| 1017 |
|
| 1018 | |
| 1019 | * DOC: enforce_isolation (int)
|
| 1020 | * enforce process isolation between graphics and compute.
|
| 1021 | * (-1 = auto, 0 = disable, 1 = enable, 2 = enable legacy mode, 3 = enable without cleaner shader)
|
| 1022 |
|
| 1023 | module_param_named(enforce_isolation, amdgpu_enforce_isolation, int, 0444);
|
| 1024 | MODULE_PARM_DESC(enforce_isolation,
|
| 1025 | "enforce process isolation between graphics and compute. (-1 = auto, 0 = disable, 1 = enable, 2 = enable legacy mode, 3 = enable without cleaner shader)");
|
| 1026 |
|
| 1027 | |
| 1028 | * DOC: modeset (int)
|
| 1029 | * Override nomodeset (1 = override, -1 = auto). The default is -1 (auto).
|
| 1030 |
|
| 1031 | MODULE_PARM_DESC(modeset, "Override nomodeset (1 = enable, -1 = auto)");
|
| 1032 | module_param_named(modeset, amdgpu_modeset, int, 0444);
|
| 1033 |
|
| 1034 | |
| 1035 | * DOC: seamless (int)
|
| 1036 | * Seamless boot will keep the image on the screen during the boot process.
|
| 1037 |
|
| 1038 | MODULE_PARM_DESC(seamless, "Seamless boot (-1 = auto (default), 0 = disable, 1 = enable)");
|
| 1039 | module_param_named(seamless, amdgpu_seamless, int, 0444);
|
| 1040 |
|
| 1041 | |
| 1042 | * DOC: debug_mask (uint)
|
| 1043 | * Debug options for amdgpu, work as a binary mask with the following options:
|
| 1044 | *
|
| 1045 | * - 0x1: Debug VM handling
|
| 1046 | * - 0x2: Enable simulating large-bar capability on non-large bar system. This
|
| 1047 | * limits the VRAM size reported to ROCm applications to the visible
|
| 1048 | * size, usually 256MB.
|
| 1049 | * - 0x4: Disable GPU soft recovery, always do a full reset
|
| 1050 | * - 0x8: Use VRAM for firmware loading
|
| 1051 | * - 0x10: Enable ACA based RAS logging
|
| 1052 | * - 0x20: Enable experimental resets
|
| 1053 | * - 0x40: Disable ring resets
|
| 1054 | * - 0x80: Use VRAM for SMU pool
|
| 1055 |
|
| 1056 | MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default");
|
| 1057 | module_param_named_unsafe(debug_mask, amdgpu_debug_mask, uint, 0444);
|
| 1058 |
|
| 1059 | |
| 1060 | * DOC: agp (int)
|
| 1061 | * Enable the AGP aperture. This provides an aperture in the GPU's internal
|
| 1062 | * address space for direct access to system memory. Note that these accesses
|
| 1063 | * are non-snooped, so they are only used for access to uncached memory.
|
| 1064 |
|
| 1065 | MODULE_PARM_DESC(agp, "AGP (-1 = auto (default), 0 = disable, 1 = enable)");
|
| 1066 | module_param_named(agp, amdgpu_agp, int, 0444);
|
| 1067 |
|
| 1068 | |
| 1069 | * DOC: wbrf (int)
|
| 1070 | * Enable Wifi RFI interference mitigation feature.
|
| 1071 | * Due to electrical and mechanical constraints there may be likely interference of
|
| 1072 | * relatively high-powered harmonics of the (G-)DDR memory clocks with local radio
|
| 1073 | * module frequency bands used by Wifi 6/6e/7. To mitigate the possible RFI interference,
|
| 1074 | * with this feature enabled, PMFW will use either “shadowed P-State” or “P-State” based
|
| 1075 | * on active list of frequencies in-use (to be avoided) as part of initial setting or
|
| 1076 | * P-state transition. However, there may be potential performance impact with this
|
| 1077 | * feature enabled.
|
| 1078 | * (0 = disabled, 1 = enabled, -1 = auto (default setting, will be enabled if supported))
|
| 1079 |
|
| 1080 | MODULE_PARM_DESC(wbrf,
|
| 1081 | "Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 = auto(default)");
|
| 1082 | module_param_named(wbrf, amdgpu_wbrf, int, 0444);
|
| 1083 |
|
| 1084 | |
| 1085 | * DOC: rebar (int)
|
| 1086 | * Allow BAR resizing. Disable this to prevent the driver from attempting
|
| 1087 | * to resize the BAR if the GPU supports it and there is available MMIO space.
|
| 1088 | * Note that this just prevents the driver from resizing the BAR. The BIOS
|
| 1089 | * may have already resized the BAR at boot time.
|
| 1090 |
|
| 1091 | MODULE_PARM_DESC(rebar, "Resizable BAR (-1 = auto (default), 0 = disable, 1 = enable)");
|
| 1092 | module_param_named(rebar, amdgpu_rebar, int, 0444);
|
| 1093 |
|
| 1094 | |
| 1095 | * DOC: user_queue (int)
|
| 1096 | * Enable user queues on systems that support user queues. Possible values:
|
| 1097 | *
|
| 1098 | * - -1 = auto (ASIC specific default)
|
| 1099 | * - 0 = user queues disabled
|
| 1100 | * - 1 = user queues enabled and kernel queues enabled (if supported)
|
| 1101 | * - 2 = user queues enabled and kernel queues disabled
|
| 1102 |
|
| 1103 | MODULE_PARM_DESC(user_queue, "Enable user queues (-1 = auto (default), 0 = disable, 1 = enable, 2 = enable UQs and disable KQs)");
|
| 1104 | module_param_named(user_queue, amdgpu_user_queue, int, 0444);
|
| 1105 |
|
| 1106 | |
| 1107 | * DOC: hdmi_hpd_debounce_delay_ms (uint)
|
| 1108 | * HDMI HPD disconnect debounce delay in milliseconds.
|
| 1109 | *
|
| 1110 | * Used to filter short disconnect->reconnect HPD toggles some HDMI sinks
|
| 1111 | * generate while entering/leaving power save. Set to 0 to disable by default.
|
| 1112 |
|
| 1113 | MODULE_PARM_DESC(hdmi_hpd_debounce_delay_ms, "HDMI HPD disconnect debounce delay in milliseconds (0 to disable (by default), 1500 is common)");
|
| 1114 | module_param_named(hdmi_hpd_debounce_delay_ms, amdgpu_hdmi_hpd_debounce_delay_ms, uint, 0644);
|
| 1115 |
|
| 1116 | |
| 1117 | * DOC: ptl (int)
|
| 1118 | * Enable PTL feature at boot time. Possible values:
|
| 1119 | *
|
| 1120 | * - -1 = auto (ASIC specific default)
|
| 1121 | * - 0 = disable PTL (default)
|
| 1122 | * - 1 = enable PTL
|
| 1123 | * - 2 = permanently disable PTL (cannot be re-enabled at runtime)
|
| 1124 |
|
| 1125 | MODULE_PARM_DESC(ptl, "Enable PTL (-1 = auto, 0 = disable (default), 1 = enable, 2 = permanently disable)");
|
| 1126 | module_param_named(ptl, amdgpu_ptl, int, 0444);
|
| 1127 |
|
| 1128 | |
| 1129 | * They are supported by the mach64, r128, radeon drivers
|
| 1130 |
|
| 1131 | static const u16 amdgpu_unsupported_pciidlist[] = {
|
| 1132 |
|
| 1133 | 0x4354,
|
| 1134 | 0x4358,
|
| 1135 | 0x4554,
|
| 1136 | 0x4742,
|
| 1137 | 0x4744,
|
| 1138 | 0x4749,
|
| 1139 | 0x474C,
|
| 1140 | 0x474D,
|
| 1141 | 0x474E,
|
| 1142 | 0x474F,
|
| 1143 | 0x4750,
|
| 1144 | 0x4751,
|
| 1145 | 0x4752,
|
| 1146 | 0x4753,
|
| 1147 | 0x4754,
|
| 1148 | 0x4755,
|
| 1149 | 0x4756,
|
| 1150 | 0x4757,
|
| 1151 | 0x4758,
|
| 1152 | 0x4759,
|
| 1153 | 0x475A,
|
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| 1724 | 0x9906,
|
| 1725 | 0x9907,
|
| 1726 | 0x9908,
|
| 1727 | 0x9909,
|
| 1728 | 0x990A,
|
| 1729 | 0x990B,
|
| 1730 | 0x990C,
|
| 1731 | 0x990D,
|
| 1732 | 0x990E,
|
| 1733 | 0x990F,
|
| 1734 | 0x9910,
|
| 1735 | 0x9913,
|
| 1736 | 0x9917,
|
| 1737 | 0x9918,
|
| 1738 | 0x9919,
|
| 1739 | 0x9990,
|
| 1740 | 0x9991,
|
| 1741 | 0x9992,
|
| 1742 | 0x9993,
|
| 1743 | 0x9994,
|
| 1744 | 0x9995,
|
| 1745 | 0x9996,
|
| 1746 | 0x9997,
|
| 1747 | 0x9998,
|
| 1748 | 0x9999,
|
| 1749 | 0x999A,
|
| 1750 | 0x999B,
|
| 1751 | 0x999C,
|
| 1752 | 0x999D,
|
| 1753 | 0x99A0,
|
| 1754 | 0x99A2,
|
| 1755 | 0x99A4,
|
| 1756 |
|
| 1757 | 0x3171,
|
| 1758 | 0x3e70,
|
| 1759 | 0x4164,
|
| 1760 | 0x4165,
|
| 1761 | 0x4166,
|
| 1762 | 0x4168,
|
| 1763 | 0x4170,
|
| 1764 | 0x4171,
|
| 1765 | 0x4172,
|
| 1766 | 0x4173,
|
| 1767 | 0x496e,
|
| 1768 | 0x4a69,
|
| 1769 | 0x4a6a,
|
| 1770 | 0x4a6b,
|
| 1771 | 0x4a70,
|
| 1772 | 0x4a74,
|
| 1773 | 0x4b69,
|
| 1774 | 0x4b6b,
|
| 1775 | 0x4b6c,
|
| 1776 | 0x4c6e,
|
| 1777 | 0x4e64,
|
| 1778 | 0x4e65,
|
| 1779 | 0x4e66,
|
| 1780 | 0x4e67,
|
| 1781 | 0x4e68,
|
| 1782 | 0x4e69,
|
| 1783 | 0x4e6a,
|
| 1784 | 0x4e71,
|
| 1785 | 0x4f73,
|
| 1786 | 0x5569,
|
| 1787 | 0x556b,
|
| 1788 | 0x556d,
|
| 1789 | 0x556f,
|
| 1790 | 0x5571,
|
| 1791 | 0x5854,
|
| 1792 | 0x5874,
|
| 1793 | 0x5940,
|
| 1794 | 0x5941,
|
| 1795 | 0x5b70,
|
| 1796 | 0x5b72,
|
| 1797 | 0x5b73,
|
| 1798 | 0x5b74,
|
| 1799 | 0x5b75,
|
| 1800 | 0x5d44,
|
| 1801 | 0x5d45,
|
| 1802 | 0x5d6d,
|
| 1803 | 0x5d6f,
|
| 1804 | 0x5d72,
|
| 1805 | 0x5d77,
|
| 1806 | 0x5e6b,
|
| 1807 | 0x5e6d,
|
| 1808 | 0x7120,
|
| 1809 | 0x7124,
|
| 1810 | 0x7129,
|
| 1811 | 0x712e,
|
| 1812 | 0x712f,
|
| 1813 | 0x7162,
|
| 1814 | 0x7163,
|
| 1815 | 0x7166,
|
| 1816 | 0x7167,
|
| 1817 | 0x7172,
|
| 1818 | 0x7173,
|
| 1819 | 0x71a0,
|
| 1820 | 0x71a1,
|
| 1821 | 0x71a3,
|
| 1822 | 0x71a7,
|
| 1823 | 0x71bb,
|
| 1824 | 0x71e0,
|
| 1825 | 0x71e1,
|
| 1826 | 0x71e2,
|
| 1827 | 0x71e6,
|
| 1828 | 0x71e7,
|
| 1829 | 0x71f2,
|
| 1830 | 0x7269,
|
| 1831 | 0x726b,
|
| 1832 | 0x726e,
|
| 1833 | 0x72a0,
|
| 1834 | 0x72a8,
|
| 1835 | 0x72b1,
|
| 1836 | 0x72b3,
|
| 1837 | 0x793f,
|
| 1838 | };
|
| 1839 |
|
| 1840 | static const struct pci_device_id pciidlist[] = {
|
| 1841 | { PCI_DEVICE(0x1002, 0x6780), .driver_data = CHIP_TAHITI },
|
| 1842 | { PCI_DEVICE(0x1002, 0x6784), .driver_data = CHIP_TAHITI },
|
| 1843 | { PCI_DEVICE(0x1002, 0x6788), .driver_data = CHIP_TAHITI },
|
| 1844 | { PCI_DEVICE(0x1002, 0x678A), .driver_data = CHIP_TAHITI },
|
| 1845 | { PCI_DEVICE(0x1002, 0x6790), .driver_data = CHIP_TAHITI },
|
| 1846 | { PCI_DEVICE(0x1002, 0x6791), .driver_data = CHIP_TAHITI },
|
| 1847 | { PCI_DEVICE(0x1002, 0x6792), .driver_data = CHIP_TAHITI },
|
| 1848 | { PCI_DEVICE(0x1002, 0x6798), .driver_data = CHIP_TAHITI },
|
| 1849 | { PCI_DEVICE(0x1002, 0x6799), .driver_data = CHIP_TAHITI },
|
| 1850 | { PCI_DEVICE(0x1002, 0x679A), .driver_data = CHIP_TAHITI },
|
| 1851 | { PCI_DEVICE(0x1002, 0x679B), .driver_data = CHIP_TAHITI },
|
| 1852 | { PCI_DEVICE(0x1002, 0x679E), .driver_data = CHIP_TAHITI },
|
| 1853 | { PCI_DEVICE(0x1002, 0x679F), .driver_data = CHIP_TAHITI },
|
| 1854 | { PCI_DEVICE(0x1002, 0x6800), .driver_data = CHIP_PITCAIRN|AMD_IS_MOBILITY },
|
| 1855 | { PCI_DEVICE(0x1002, 0x6801), .driver_data = CHIP_PITCAIRN|AMD_IS_MOBILITY },
|
| 1856 | { PCI_DEVICE(0x1002, 0x6802), .driver_data = CHIP_PITCAIRN|AMD_IS_MOBILITY },
|
| 1857 | { PCI_DEVICE(0x1002, 0x6806), .driver_data = CHIP_PITCAIRN },
|
| 1858 | { PCI_DEVICE(0x1002, 0x6808), .driver_data = CHIP_PITCAIRN },
|
| 1859 | { PCI_DEVICE(0x1002, 0x6809), .driver_data = CHIP_PITCAIRN },
|
| 1860 | { PCI_DEVICE(0x1002, 0x6810), .driver_data = CHIP_PITCAIRN },
|
| 1861 | { PCI_DEVICE(0x1002, 0x6811), .driver_data = CHIP_PITCAIRN },
|
| 1862 | { PCI_DEVICE(0x1002, 0x6816), .driver_data = CHIP_PITCAIRN },
|
| 1863 | { PCI_DEVICE(0x1002, 0x6817), .driver_data = CHIP_PITCAIRN },
|
| 1864 | { PCI_DEVICE(0x1002, 0x6818), .driver_data = CHIP_PITCAIRN },
|
| 1865 | { PCI_DEVICE(0x1002, 0x6819), .driver_data = CHIP_PITCAIRN },
|
| 1866 | { PCI_DEVICE(0x1002, 0x6600), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY },
|
| 1867 | { PCI_DEVICE(0x1002, 0x6601), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY },
|
| 1868 | { PCI_DEVICE(0x1002, 0x6602), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY },
|
| 1869 | { PCI_DEVICE(0x1002, 0x6603), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY },
|
| 1870 | { PCI_DEVICE(0x1002, 0x6604), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY },
|
| 1871 | { PCI_DEVICE(0x1002, 0x6605), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY },
|
| 1872 | { PCI_DEVICE(0x1002, 0x6606), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY },
|
| 1873 | { PCI_DEVICE(0x1002, 0x6607), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY },
|
| 1874 | { PCI_DEVICE(0x1002, 0x6608), .driver_data = CHIP_OLAND },
|
| 1875 | { PCI_DEVICE(0x1002, 0x6610), .driver_data = CHIP_OLAND },
|
| 1876 | { PCI_DEVICE(0x1002, 0x6611), .driver_data = CHIP_OLAND },
|
| 1877 | { PCI_DEVICE(0x1002, 0x6613), .driver_data = CHIP_OLAND },
|
| 1878 | { PCI_DEVICE(0x1002, 0x6617), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY },
|
| 1879 | { PCI_DEVICE(0x1002, 0x6620), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY },
|
| 1880 | { PCI_DEVICE(0x1002, 0x6621), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY },
|
| 1881 | { PCI_DEVICE(0x1002, 0x6623), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY },
|
| 1882 | { PCI_DEVICE(0x1002, 0x6631), .driver_data = CHIP_OLAND },
|
| 1883 | { PCI_DEVICE(0x1002, 0x6820), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY },
|
| 1884 | { PCI_DEVICE(0x1002, 0x6821), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY },
|
| 1885 | { PCI_DEVICE(0x1002, 0x6822), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY },
|
| 1886 | { PCI_DEVICE(0x1002, 0x6823), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY },
|
| 1887 | { PCI_DEVICE(0x1002, 0x6824), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY },
|
| 1888 | { PCI_DEVICE(0x1002, 0x6825), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY },
|
| 1889 | { PCI_DEVICE(0x1002, 0x6826), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY },
|
| 1890 | { PCI_DEVICE(0x1002, 0x6827), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY },
|
| 1891 | { PCI_DEVICE(0x1002, 0x6828), .driver_data = CHIP_VERDE },
|
| 1892 | { PCI_DEVICE(0x1002, 0x6829), .driver_data = CHIP_VERDE },
|
| 1893 | { PCI_DEVICE(0x1002, 0x682A), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY },
|
| 1894 | { PCI_DEVICE(0x1002, 0x682B), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY },
|
| 1895 | { PCI_DEVICE(0x1002, 0x682C), .driver_data = CHIP_VERDE },
|
| 1896 | { PCI_DEVICE(0x1002, 0x682D), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY },
|
| 1897 | { PCI_DEVICE(0x1002, 0x682F), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY },
|
| 1898 | { PCI_DEVICE(0x1002, 0x6830), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY },
|
| 1899 | { PCI_DEVICE(0x1002, 0x6831), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY },
|
| 1900 | { PCI_DEVICE(0x1002, 0x6835), .driver_data = CHIP_VERDE },
|
| 1901 | { PCI_DEVICE(0x1002, 0x6837), .driver_data = CHIP_VERDE },
|
| 1902 | { PCI_DEVICE(0x1002, 0x6838), .driver_data = CHIP_VERDE },
|
| 1903 | { PCI_DEVICE(0x1002, 0x6839), .driver_data = CHIP_VERDE },
|
| 1904 | { PCI_DEVICE(0x1002, 0x683B), .driver_data = CHIP_VERDE },
|
| 1905 | { PCI_DEVICE(0x1002, 0x683D), .driver_data = CHIP_VERDE },
|
| 1906 | { PCI_DEVICE(0x1002, 0x683F), .driver_data = CHIP_VERDE },
|
| 1907 | { PCI_DEVICE(0x1002, 0x6660), .driver_data = CHIP_HAINAN|AMD_IS_MOBILITY },
|
| 1908 | { PCI_DEVICE(0x1002, 0x6663), .driver_data = CHIP_HAINAN|AMD_IS_MOBILITY },
|
| 1909 | { PCI_DEVICE(0x1002, 0x6664), .driver_data = CHIP_HAINAN|AMD_IS_MOBILITY },
|
| 1910 | { PCI_DEVICE(0x1002, 0x6665), .driver_data = CHIP_HAINAN|AMD_IS_MOBILITY },
|
| 1911 | { PCI_DEVICE(0x1002, 0x6667), .driver_data = CHIP_HAINAN|AMD_IS_MOBILITY },
|
| 1912 | { PCI_DEVICE(0x1002, 0x666F), .driver_data = CHIP_HAINAN|AMD_IS_MOBILITY },
|
| 1913 |
|
| 1914 | { PCI_DEVICE(0x1002, 0x1304), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU },
|
| 1915 | { PCI_DEVICE(0x1002, 0x1305), .driver_data = CHIP_KAVERI|AMD_IS_APU },
|
| 1916 | { PCI_DEVICE(0x1002, 0x1306), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU },
|
| 1917 | { PCI_DEVICE(0x1002, 0x1307), .driver_data = CHIP_KAVERI|AMD_IS_APU },
|
| 1918 | { PCI_DEVICE(0x1002, 0x1309), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU },
|
| 1919 | { PCI_DEVICE(0x1002, 0x130A), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU },
|
| 1920 | { PCI_DEVICE(0x1002, 0x130B), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU },
|
| 1921 | { PCI_DEVICE(0x1002, 0x130C), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU },
|
| 1922 | { PCI_DEVICE(0x1002, 0x130D), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU },
|
| 1923 | { PCI_DEVICE(0x1002, 0x130E), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU },
|
| 1924 | { PCI_DEVICE(0x1002, 0x130F), .driver_data = CHIP_KAVERI|AMD_IS_APU },
|
| 1925 | { PCI_DEVICE(0x1002, 0x1310), .driver_data = CHIP_KAVERI|AMD_IS_APU },
|
| 1926 | { PCI_DEVICE(0x1002, 0x1311), .driver_data = CHIP_KAVERI|AMD_IS_APU },
|
| 1927 | { PCI_DEVICE(0x1002, 0x1312), .driver_data = CHIP_KAVERI|AMD_IS_APU },
|
| 1928 | { PCI_DEVICE(0x1002, 0x1313), .driver_data = CHIP_KAVERI|AMD_IS_APU },
|
| 1929 | { PCI_DEVICE(0x1002, 0x1315), .driver_data = CHIP_KAVERI|AMD_IS_APU },
|
| 1930 | { PCI_DEVICE(0x1002, 0x1316), .driver_data = CHIP_KAVERI|AMD_IS_APU },
|
| 1931 | { PCI_DEVICE(0x1002, 0x1317), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU },
|
| 1932 | { PCI_DEVICE(0x1002, 0x1318), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU },
|
| 1933 | { PCI_DEVICE(0x1002, 0x131B), .driver_data = CHIP_KAVERI|AMD_IS_APU },
|
| 1934 | { PCI_DEVICE(0x1002, 0x131C), .driver_data = CHIP_KAVERI|AMD_IS_APU },
|
| 1935 | { PCI_DEVICE(0x1002, 0x131D), .driver_data = CHIP_KAVERI|AMD_IS_APU },
|
| 1936 |
|
| 1937 | { PCI_DEVICE(0x1002, 0x6640), .driver_data = CHIP_BONAIRE|AMD_IS_MOBILITY },
|
| 1938 | { PCI_DEVICE(0x1002, 0x6641), .driver_data = CHIP_BONAIRE|AMD_IS_MOBILITY },
|
| 1939 | { PCI_DEVICE(0x1002, 0x6646), .driver_data = CHIP_BONAIRE|AMD_IS_MOBILITY },
|
| 1940 | { PCI_DEVICE(0x1002, 0x6647), .driver_data = CHIP_BONAIRE|AMD_IS_MOBILITY },
|
| 1941 | { PCI_DEVICE(0x1002, 0x6649), .driver_data = CHIP_BONAIRE },
|
| 1942 | { PCI_DEVICE(0x1002, 0x664D), .driver_data = CHIP_BONAIRE },
|
| 1943 | { PCI_DEVICE(0x1002, 0x6650), .driver_data = CHIP_BONAIRE },
|
| 1944 | { PCI_DEVICE(0x1002, 0x6651), .driver_data = CHIP_BONAIRE },
|
| 1945 | { PCI_DEVICE(0x1002, 0x6658), .driver_data = CHIP_BONAIRE },
|
| 1946 | { PCI_DEVICE(0x1002, 0x665c), .driver_data = CHIP_BONAIRE },
|
| 1947 | { PCI_DEVICE(0x1002, 0x665d), .driver_data = CHIP_BONAIRE },
|
| 1948 | { PCI_DEVICE(0x1002, 0x665f), .driver_data = CHIP_BONAIRE },
|
| 1949 |
|
| 1950 | { PCI_DEVICE(0x1002, 0x67A0), .driver_data = CHIP_HAWAII },
|
| 1951 | { PCI_DEVICE(0x1002, 0x67A1), .driver_data = CHIP_HAWAII },
|
| 1952 | { PCI_DEVICE(0x1002, 0x67A2), .driver_data = CHIP_HAWAII },
|
| 1953 | { PCI_DEVICE(0x1002, 0x67A8), .driver_data = CHIP_HAWAII },
|
| 1954 | { PCI_DEVICE(0x1002, 0x67A9), .driver_data = CHIP_HAWAII },
|
| 1955 | { PCI_DEVICE(0x1002, 0x67AA), .driver_data = CHIP_HAWAII },
|
| 1956 | { PCI_DEVICE(0x1002, 0x67B0), .driver_data = CHIP_HAWAII },
|
| 1957 | { PCI_DEVICE(0x1002, 0x67B1), .driver_data = CHIP_HAWAII },
|
| 1958 | { PCI_DEVICE(0x1002, 0x67B8), .driver_data = CHIP_HAWAII },
|
| 1959 | { PCI_DEVICE(0x1002, 0x67B9), .driver_data = CHIP_HAWAII },
|
| 1960 | { PCI_DEVICE(0x1002, 0x67BA), .driver_data = CHIP_HAWAII },
|
| 1961 | { PCI_DEVICE(0x1002, 0x67BE), .driver_data = CHIP_HAWAII },
|
| 1962 |
|
| 1963 | { PCI_DEVICE(0x1002, 0x9830), .driver_data = CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU },
|
| 1964 | { PCI_DEVICE(0x1002, 0x9831), .driver_data = CHIP_KABINI|AMD_IS_APU },
|
| 1965 | { PCI_DEVICE(0x1002, 0x9832), .driver_data = CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU },
|
| 1966 | { PCI_DEVICE(0x1002, 0x9833), .driver_data = CHIP_KABINI|AMD_IS_APU },
|
| 1967 | { PCI_DEVICE(0x1002, 0x9834), .driver_data = CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU },
|
| 1968 | { PCI_DEVICE(0x1002, 0x9835), .driver_data = CHIP_KABINI|AMD_IS_APU },
|
| 1969 | { PCI_DEVICE(0x1002, 0x9836), .driver_data = CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU },
|
| 1970 | { PCI_DEVICE(0x1002, 0x9837), .driver_data = CHIP_KABINI|AMD_IS_APU },
|
| 1971 | { PCI_DEVICE(0x1002, 0x9838), .driver_data = CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU },
|
| 1972 | { PCI_DEVICE(0x1002, 0x9839), .driver_data = CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU },
|
| 1973 | { PCI_DEVICE(0x1002, 0x983a), .driver_data = CHIP_KABINI|AMD_IS_APU },
|
| 1974 | { PCI_DEVICE(0x1002, 0x983b), .driver_data = CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU },
|
| 1975 | { PCI_DEVICE(0x1002, 0x983c), .driver_data = CHIP_KABINI|AMD_IS_APU },
|
| 1976 | { PCI_DEVICE(0x1002, 0x983d), .driver_data = CHIP_KABINI|AMD_IS_APU },
|
| 1977 | { PCI_DEVICE(0x1002, 0x983e), .driver_data = CHIP_KABINI|AMD_IS_APU },
|
| 1978 | { PCI_DEVICE(0x1002, 0x983f), .driver_data = CHIP_KABINI|AMD_IS_APU },
|
| 1979 |
|
| 1980 | { PCI_DEVICE(0x1002, 0x9850), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU },
|
| 1981 | { PCI_DEVICE(0x1002, 0x9851), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU },
|
| 1982 | { PCI_DEVICE(0x1002, 0x9852), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU },
|
| 1983 | { PCI_DEVICE(0x1002, 0x9853), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU },
|
| 1984 | { PCI_DEVICE(0x1002, 0x9854), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU },
|
| 1985 | { PCI_DEVICE(0x1002, 0x9855), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU },
|
| 1986 | { PCI_DEVICE(0x1002, 0x9856), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU },
|
| 1987 | { PCI_DEVICE(0x1002, 0x9857), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU },
|
| 1988 | { PCI_DEVICE(0x1002, 0x9858), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU },
|
| 1989 | { PCI_DEVICE(0x1002, 0x9859), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU },
|
| 1990 | { PCI_DEVICE(0x1002, 0x985A), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU },
|
| 1991 | { PCI_DEVICE(0x1002, 0x985B), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU },
|
| 1992 | { PCI_DEVICE(0x1002, 0x985C), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU },
|
| 1993 | { PCI_DEVICE(0x1002, 0x985D), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU },
|
| 1994 | { PCI_DEVICE(0x1002, 0x985E), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU },
|
| 1995 | { PCI_DEVICE(0x1002, 0x985F), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU },
|
| 1996 |
|
| 1997 | { PCI_DEVICE(0x1002, 0x6900), .driver_data = CHIP_TOPAZ },
|
| 1998 | { PCI_DEVICE(0x1002, 0x6901), .driver_data = CHIP_TOPAZ },
|
| 1999 | { PCI_DEVICE(0x1002, 0x6902), .driver_data = CHIP_TOPAZ },
|
| 2000 | { PCI_DEVICE(0x1002, 0x6903), .driver_data = CHIP_TOPAZ },
|
| 2001 | { PCI_DEVICE(0x1002, 0x6907), .driver_data = CHIP_TOPAZ },
|
| 2002 |
|
| 2003 | { PCI_DEVICE(0x1002, 0x6920), .driver_data = CHIP_TONGA },
|
| 2004 | { PCI_DEVICE(0x1002, 0x6921), .driver_data = CHIP_TONGA },
|
| 2005 | { PCI_DEVICE(0x1002, 0x6928), .driver_data = CHIP_TONGA },
|
| 2006 | { PCI_DEVICE(0x1002, 0x6929), .driver_data = CHIP_TONGA },
|
| 2007 | { PCI_DEVICE(0x1002, 0x692B), .driver_data = CHIP_TONGA },
|
| 2008 | { PCI_DEVICE(0x1002, 0x692F), .driver_data = CHIP_TONGA },
|
| 2009 | { PCI_DEVICE(0x1002, 0x6930), .driver_data = CHIP_TONGA },
|
| 2010 | { PCI_DEVICE(0x1002, 0x6938), .driver_data = CHIP_TONGA },
|
| 2011 | { PCI_DEVICE(0x1002, 0x6939), .driver_data = CHIP_TONGA },
|
| 2012 | { PCI_DEVICE(0x1002, 0x693B), .driver_data = CHIP_TONGA },
|
| 2013 |
|
| 2014 | { PCI_DEVICE(0x1002, 0x7300), .driver_data = CHIP_FIJI },
|
| 2015 | { PCI_DEVICE(0x1002, 0x730F), .driver_data = CHIP_FIJI },
|
| 2016 |
|
| 2017 | { PCI_DEVICE(0x1002, 0x9870), .driver_data = CHIP_CARRIZO|AMD_IS_APU },
|
| 2018 | { PCI_DEVICE(0x1002, 0x9874), .driver_data = CHIP_CARRIZO|AMD_IS_APU },
|
| 2019 | { PCI_DEVICE(0x1002, 0x9875), .driver_data = CHIP_CARRIZO|AMD_IS_APU },
|
| 2020 | { PCI_DEVICE(0x1002, 0x9876), .driver_data = CHIP_CARRIZO|AMD_IS_APU },
|
| 2021 | { PCI_DEVICE(0x1002, 0x9877), .driver_data = CHIP_CARRIZO|AMD_IS_APU },
|
| 2022 |
|
| 2023 | { PCI_DEVICE(0x1002, 0x98E4), .driver_data = CHIP_STONEY|AMD_IS_APU },
|
| 2024 |
|
| 2025 | { PCI_DEVICE(0x1002, 0x67E0), .driver_data = CHIP_POLARIS11 },
|
| 2026 | { PCI_DEVICE(0x1002, 0x67E3), .driver_data = CHIP_POLARIS11 },
|
| 2027 | { PCI_DEVICE(0x1002, 0x67E8), .driver_data = CHIP_POLARIS11 },
|
| 2028 | { PCI_DEVICE(0x1002, 0x67EB), .driver_data = CHIP_POLARIS11 },
|
| 2029 | { PCI_DEVICE(0x1002, 0x67EF), .driver_data = CHIP_POLARIS11 },
|
| 2030 | { PCI_DEVICE(0x1002, 0x67FF), .driver_data = CHIP_POLARIS11 },
|
| 2031 | { PCI_DEVICE(0x1002, 0x67E1), .driver_data = CHIP_POLARIS11 },
|
| 2032 | { PCI_DEVICE(0x1002, 0x67E7), .driver_data = CHIP_POLARIS11 },
|
| 2033 | { PCI_DEVICE(0x1002, 0x67E9), .driver_data = CHIP_POLARIS11 },
|
| 2034 |
|
| 2035 | { PCI_DEVICE(0x1002, 0x67C0), .driver_data = CHIP_POLARIS10 },
|
| 2036 | { PCI_DEVICE(0x1002, 0x67C1), .driver_data = CHIP_POLARIS10 },
|
| 2037 | { PCI_DEVICE(0x1002, 0x67C2), .driver_data = CHIP_POLARIS10 },
|
| 2038 | { PCI_DEVICE(0x1002, 0x67C4), .driver_data = CHIP_POLARIS10 },
|
| 2039 | { PCI_DEVICE(0x1002, 0x67C7), .driver_data = CHIP_POLARIS10 },
|
| 2040 | { PCI_DEVICE(0x1002, 0x67D0), .driver_data = CHIP_POLARIS10 },
|
| 2041 | { PCI_DEVICE(0x1002, 0x67D4), .driver_data = CHIP_POLARIS10 },
|
| 2042 | { PCI_DEVICE(0x1002, 0x67DF), .driver_data = CHIP_POLARIS10 },
|
| 2043 | { PCI_DEVICE(0x1002, 0x67C8), .driver_data = CHIP_POLARIS10 },
|
| 2044 | { PCI_DEVICE(0x1002, 0x67C9), .driver_data = CHIP_POLARIS10 },
|
| 2045 | { PCI_DEVICE(0x1002, 0x67CA), .driver_data = CHIP_POLARIS10 },
|
| 2046 | { PCI_DEVICE(0x1002, 0x67CC), .driver_data = CHIP_POLARIS10 },
|
| 2047 | { PCI_DEVICE(0x1002, 0x67CF), .driver_data = CHIP_POLARIS10 },
|
| 2048 | { PCI_DEVICE(0x1002, 0x6FDF), .driver_data = CHIP_POLARIS10 },
|
| 2049 |
|
| 2050 | { PCI_DEVICE(0x1002, 0x6980), .driver_data = CHIP_POLARIS12 },
|
| 2051 | { PCI_DEVICE(0x1002, 0x6981), .driver_data = CHIP_POLARIS12 },
|
| 2052 | { PCI_DEVICE(0x1002, 0x6985), .driver_data = CHIP_POLARIS12 },
|
| 2053 | { PCI_DEVICE(0x1002, 0x6986), .driver_data = CHIP_POLARIS12 },
|
| 2054 | { PCI_DEVICE(0x1002, 0x6987), .driver_data = CHIP_POLARIS12 },
|
| 2055 | { PCI_DEVICE(0x1002, 0x698F), .driver_data = CHIP_POLARIS12 },
|
| 2056 | { PCI_DEVICE(0x1002, 0x6995), .driver_data = CHIP_POLARIS12 },
|
| 2057 | { PCI_DEVICE(0x1002, 0x6997), .driver_data = CHIP_POLARIS12 },
|
| 2058 | { PCI_DEVICE(0x1002, 0x699F), .driver_data = CHIP_POLARIS12 },
|
| 2059 |
|
| 2060 | { PCI_DEVICE(0x1002, 0x694C), .driver_data = CHIP_VEGAM },
|
| 2061 | { PCI_DEVICE(0x1002, 0x694E), .driver_data = CHIP_VEGAM },
|
| 2062 | { PCI_DEVICE(0x1002, 0x694F), .driver_data = CHIP_VEGAM },
|
| 2063 |
|
| 2064 | { PCI_DEVICE(0x1002, 0x6860), .driver_data = CHIP_VEGA10 },
|
| 2065 | { PCI_DEVICE(0x1002, 0x6861), .driver_data = CHIP_VEGA10 },
|
| 2066 | { PCI_DEVICE(0x1002, 0x6862), .driver_data = CHIP_VEGA10 },
|
| 2067 | { PCI_DEVICE(0x1002, 0x6863), .driver_data = CHIP_VEGA10 },
|
| 2068 | { PCI_DEVICE(0x1002, 0x6864), .driver_data = CHIP_VEGA10 },
|
| 2069 | { PCI_DEVICE(0x1002, 0x6867), .driver_data = CHIP_VEGA10 },
|
| 2070 | { PCI_DEVICE(0x1002, 0x6868), .driver_data = CHIP_VEGA10 },
|
| 2071 | { PCI_DEVICE(0x1002, 0x6869), .driver_data = CHIP_VEGA10 },
|
| 2072 | { PCI_DEVICE(0x1002, 0x686a), .driver_data = CHIP_VEGA10 },
|
| 2073 | { PCI_DEVICE(0x1002, 0x686b), .driver_data = CHIP_VEGA10 },
|
| 2074 | { PCI_DEVICE(0x1002, 0x686c), .driver_data = CHIP_VEGA10 },
|
| 2075 | { PCI_DEVICE(0x1002, 0x686d), .driver_data = CHIP_VEGA10 },
|
| 2076 | { PCI_DEVICE(0x1002, 0x686e), .driver_data = CHIP_VEGA10 },
|
| 2077 | { PCI_DEVICE(0x1002, 0x686f), .driver_data = CHIP_VEGA10 },
|
| 2078 | { PCI_DEVICE(0x1002, 0x687f), .driver_data = CHIP_VEGA10 },
|
| 2079 |
|
| 2080 | { PCI_DEVICE(0x1002, 0x69A0), .driver_data = CHIP_VEGA12 },
|
| 2081 | { PCI_DEVICE(0x1002, 0x69A1), .driver_data = CHIP_VEGA12 },
|
| 2082 | { PCI_DEVICE(0x1002, 0x69A2), .driver_data = CHIP_VEGA12 },
|
| 2083 | { PCI_DEVICE(0x1002, 0x69A3), .driver_data = CHIP_VEGA12 },
|
| 2084 | { PCI_DEVICE(0x1002, 0x69AF), .driver_data = CHIP_VEGA12 },
|
| 2085 |
|
| 2086 | { PCI_DEVICE(0x1002, 0x66A0), .driver_data = CHIP_VEGA20 },
|
| 2087 | { PCI_DEVICE(0x1002, 0x66A1), .driver_data = CHIP_VEGA20 },
|
| 2088 | { PCI_DEVICE(0x1002, 0x66A2), .driver_data = CHIP_VEGA20 },
|
| 2089 | { PCI_DEVICE(0x1002, 0x66A3), .driver_data = CHIP_VEGA20 },
|
| 2090 | { PCI_DEVICE(0x1002, 0x66A4), .driver_data = CHIP_VEGA20 },
|
| 2091 | { PCI_DEVICE(0x1002, 0x66A7), .driver_data = CHIP_VEGA20 },
|
| 2092 | { PCI_DEVICE(0x1002, 0x66AF), .driver_data = CHIP_VEGA20 },
|
| 2093 |
|
| 2094 | { PCI_DEVICE(0x1002, 0x15dd), .driver_data = CHIP_RAVEN|AMD_IS_APU },
|
| 2095 | { PCI_DEVICE(0x1002, 0x15d8), .driver_data = CHIP_RAVEN|AMD_IS_APU },
|
| 2096 |
|
| 2097 | { PCI_DEVICE(0x1002, 0x738C), .driver_data = CHIP_ARCTURUS },
|
| 2098 | { PCI_DEVICE(0x1002, 0x7388), .driver_data = CHIP_ARCTURUS },
|
| 2099 | { PCI_DEVICE(0x1002, 0x738E), .driver_data = CHIP_ARCTURUS },
|
| 2100 | { PCI_DEVICE(0x1002, 0x7390), .driver_data = CHIP_ARCTURUS },
|
| 2101 |
|
| 2102 | { PCI_DEVICE(0x1002, 0x7310), .driver_data = CHIP_NAVI10 },
|
| 2103 | { PCI_DEVICE(0x1002, 0x7312), .driver_data = CHIP_NAVI10 },
|
| 2104 | { PCI_DEVICE(0x1002, 0x7318), .driver_data = CHIP_NAVI10 },
|
| 2105 | { PCI_DEVICE(0x1002, 0x7319), .driver_data = CHIP_NAVI10 },
|
| 2106 | { PCI_DEVICE(0x1002, 0x731A), .driver_data = CHIP_NAVI10 },
|
| 2107 | { PCI_DEVICE(0x1002, 0x731B), .driver_data = CHIP_NAVI10 },
|
| 2108 | { PCI_DEVICE(0x1002, 0x731E), .driver_data = CHIP_NAVI10 },
|
| 2109 | { PCI_DEVICE(0x1002, 0x731F), .driver_data = CHIP_NAVI10 },
|
| 2110 |
|
| 2111 | { PCI_DEVICE(0x1002, 0x7340), .driver_data = CHIP_NAVI14 },
|
| 2112 | { PCI_DEVICE(0x1002, 0x7341), .driver_data = CHIP_NAVI14 },
|
| 2113 | { PCI_DEVICE(0x1002, 0x7347), .driver_data = CHIP_NAVI14 },
|
| 2114 | { PCI_DEVICE(0x1002, 0x734F), .driver_data = CHIP_NAVI14 },
|
| 2115 |
|
| 2116 |
|
| 2117 | { PCI_DEVICE(0x1002, 0x15E7), .driver_data = CHIP_RENOIR|AMD_IS_APU },
|
| 2118 | { PCI_DEVICE(0x1002, 0x1636), .driver_data = CHIP_RENOIR|AMD_IS_APU },
|
| 2119 | { PCI_DEVICE(0x1002, 0x1638), .driver_data = CHIP_RENOIR|AMD_IS_APU },
|
| 2120 | { PCI_DEVICE(0x1002, 0x164C), .driver_data = CHIP_RENOIR|AMD_IS_APU },
|
| 2121 |
|
| 2122 |
|
| 2123 | { PCI_DEVICE(0x1002, 0x7360), .driver_data = CHIP_NAVI12 },
|
| 2124 | { PCI_DEVICE(0x1002, 0x7362), .driver_data = CHIP_NAVI12 },
|
| 2125 |
|
| 2126 |
|
| 2127 | { PCI_DEVICE(0x1002, 0x73A0), .driver_data = CHIP_SIENNA_CICHLID },
|
| 2128 | { PCI_DEVICE(0x1002, 0x73A1), .driver_data = CHIP_SIENNA_CICHLID },
|
| 2129 | { PCI_DEVICE(0x1002, 0x73A2), .driver_data = CHIP_SIENNA_CICHLID },
|
| 2130 | { PCI_DEVICE(0x1002, 0x73A3), .driver_data = CHIP_SIENNA_CICHLID },
|
| 2131 | { PCI_DEVICE(0x1002, 0x73A5), .driver_data = CHIP_SIENNA_CICHLID },
|
| 2132 | { PCI_DEVICE(0x1002, 0x73A8), .driver_data = CHIP_SIENNA_CICHLID },
|
| 2133 | { PCI_DEVICE(0x1002, 0x73A9), .driver_data = CHIP_SIENNA_CICHLID },
|
| 2134 | { PCI_DEVICE(0x1002, 0x73AB), .driver_data = CHIP_SIENNA_CICHLID },
|
| 2135 | { PCI_DEVICE(0x1002, 0x73AC), .driver_data = CHIP_SIENNA_CICHLID },
|
| 2136 | { PCI_DEVICE(0x1002, 0x73AD), .driver_data = CHIP_SIENNA_CICHLID },
|
| 2137 | { PCI_DEVICE(0x1002, 0x73AE), .driver_data = CHIP_SIENNA_CICHLID },
|
| 2138 | { PCI_DEVICE(0x1002, 0x73AF), .driver_data = CHIP_SIENNA_CICHLID },
|
| 2139 | { PCI_DEVICE(0x1002, 0x73BF), .driver_data = CHIP_SIENNA_CICHLID },
|
| 2140 |
|
| 2141 |
|
| 2142 | { PCI_DEVICE(0x1002, 0x164D), .driver_data = CHIP_YELLOW_CARP|AMD_IS_APU },
|
| 2143 | { PCI_DEVICE(0x1002, 0x1681), .driver_data = CHIP_YELLOW_CARP|AMD_IS_APU },
|
| 2144 |
|
| 2145 |
|
| 2146 | { PCI_DEVICE(0x1002, 0x73C0), .driver_data = CHIP_NAVY_FLOUNDER },
|
| 2147 | { PCI_DEVICE(0x1002, 0x73C1), .driver_data = CHIP_NAVY_FLOUNDER },
|
| 2148 | { PCI_DEVICE(0x1002, 0x73C3), .driver_data = CHIP_NAVY_FLOUNDER },
|
| 2149 | { PCI_DEVICE(0x1002, 0x73DA), .driver_data = CHIP_NAVY_FLOUNDER },
|
| 2150 | { PCI_DEVICE(0x1002, 0x73DB), .driver_data = CHIP_NAVY_FLOUNDER },
|
| 2151 | { PCI_DEVICE(0x1002, 0x73DC), .driver_data = CHIP_NAVY_FLOUNDER },
|
| 2152 | { PCI_DEVICE(0x1002, 0x73DD), .driver_data = CHIP_NAVY_FLOUNDER },
|
| 2153 | { PCI_DEVICE(0x1002, 0x73DE), .driver_data = CHIP_NAVY_FLOUNDER },
|
| 2154 | { PCI_DEVICE(0x1002, 0x73DF), .driver_data = CHIP_NAVY_FLOUNDER },
|
| 2155 |
|
| 2156 |
|
| 2157 | { PCI_DEVICE(0x1002, 0x73E0), .driver_data = CHIP_DIMGREY_CAVEFISH },
|
| 2158 | { PCI_DEVICE(0x1002, 0x73E1), .driver_data = CHIP_DIMGREY_CAVEFISH },
|
| 2159 | { PCI_DEVICE(0x1002, 0x73E2), .driver_data = CHIP_DIMGREY_CAVEFISH },
|
| 2160 | { PCI_DEVICE(0x1002, 0x73E3), .driver_data = CHIP_DIMGREY_CAVEFISH },
|
| 2161 | { PCI_DEVICE(0x1002, 0x73E8), .driver_data = CHIP_DIMGREY_CAVEFISH },
|
| 2162 | { PCI_DEVICE(0x1002, 0x73E9), .driver_data = CHIP_DIMGREY_CAVEFISH },
|
| 2163 | { PCI_DEVICE(0x1002, 0x73EA), .driver_data = CHIP_DIMGREY_CAVEFISH },
|
| 2164 | { PCI_DEVICE(0x1002, 0x73EB), .driver_data = CHIP_DIMGREY_CAVEFISH },
|
| 2165 | { PCI_DEVICE(0x1002, 0x73EC), .driver_data = CHIP_DIMGREY_CAVEFISH },
|
| 2166 | { PCI_DEVICE(0x1002, 0x73ED), .driver_data = CHIP_DIMGREY_CAVEFISH },
|
| 2167 | { PCI_DEVICE(0x1002, 0x73EF), .driver_data = CHIP_DIMGREY_CAVEFISH },
|
| 2168 | { PCI_DEVICE(0x1002, 0x73FF), .driver_data = CHIP_DIMGREY_CAVEFISH },
|
| 2169 |
|
| 2170 |
|
| 2171 | { PCI_DEVICE(0x1002, 0x7408), .driver_data = CHIP_ALDEBARAN },
|
| 2172 | { PCI_DEVICE(0x1002, 0x740C), .driver_data = CHIP_ALDEBARAN },
|
| 2173 | { PCI_DEVICE(0x1002, 0x740F), .driver_data = CHIP_ALDEBARAN },
|
| 2174 | { PCI_DEVICE(0x1002, 0x7410), .driver_data = CHIP_ALDEBARAN },
|
| 2175 |
|
| 2176 |
|
| 2177 | { PCI_DEVICE(0x1002, 0x13DB), .driver_data = CHIP_CYAN_SKILLFISH|AMD_IS_APU },
|
| 2178 | { PCI_DEVICE(0x1002, 0x13F9), .driver_data = CHIP_CYAN_SKILLFISH|AMD_IS_APU },
|
| 2179 | { PCI_DEVICE(0x1002, 0x13FA), .driver_data = CHIP_CYAN_SKILLFISH|AMD_IS_APU },
|
| 2180 | { PCI_DEVICE(0x1002, 0x13FB), .driver_data = CHIP_CYAN_SKILLFISH|AMD_IS_APU },
|
| 2181 | { PCI_DEVICE(0x1002, 0x13FC), .driver_data = CHIP_CYAN_SKILLFISH|AMD_IS_APU },
|
| 2182 | { PCI_DEVICE(0x1002, 0x13FE), .driver_data = CHIP_CYAN_SKILLFISH|AMD_IS_APU },
|
| 2183 | { PCI_DEVICE(0x1002, 0x143F), .driver_data = CHIP_CYAN_SKILLFISH|AMD_IS_APU },
|
| 2184 |
|
| 2185 |
|
| 2186 | { PCI_DEVICE(0x1002, 0x7420), .driver_data = CHIP_BEIGE_GOBY },
|
| 2187 | { PCI_DEVICE(0x1002, 0x7421), .driver_data = CHIP_BEIGE_GOBY },
|
| 2188 | { PCI_DEVICE(0x1002, 0x7422), .driver_data = CHIP_BEIGE_GOBY },
|
| 2189 | { PCI_DEVICE(0x1002, 0x7423), .driver_data = CHIP_BEIGE_GOBY },
|
| 2190 | { PCI_DEVICE(0x1002, 0x7424), .driver_data = CHIP_BEIGE_GOBY },
|
| 2191 | { PCI_DEVICE(0x1002, 0x743F), .driver_data = CHIP_BEIGE_GOBY },
|
| 2192 |
|
| 2193 | { PCI_DEVICE(0x1002, PCI_ANY_ID),
|
| 2194 | .class = PCI_CLASS_DISPLAY_VGA << 8,
|
| 2195 | .class_mask = 0xffffff,
|
| 2196 | .driver_data = CHIP_IP_DISCOVERY },
|
| 2197 |
|
| 2198 | { PCI_DEVICE(0x1002, PCI_ANY_ID),
|
| 2199 | .class = PCI_CLASS_DISPLAY_OTHER << 8,
|
| 2200 | .class_mask = 0xffffff,
|
| 2201 | .driver_data = CHIP_IP_DISCOVERY },
|
| 2202 |
|
| 2203 | { PCI_DEVICE(0x1002, PCI_ANY_ID),
|
| 2204 | .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8,
|
| 2205 | .class_mask = 0xffffff,
|
| 2206 | .driver_data = CHIP_IP_DISCOVERY },
|
| 2207 |
|
| 2208 | { }
|
| 2209 | };
|
| 2210 |
|
| 2211 | MODULE_DEVICE_TABLE(pci, pciidlist);
|
| 2212 |
|
| 2213 | static const struct amdgpu_asic_type_quirk asic_type_quirks[] = {
|
| 2214 |
|
| 2215 | {0x67FF, 0xE3, CHIP_POLARIS10},
|
| 2216 | {0x67FF, 0xE7, CHIP_POLARIS10},
|
| 2217 | {0x67FF, 0xF3, CHIP_POLARIS10},
|
| 2218 | {0x67FF, 0xF7, CHIP_POLARIS10},
|
| 2219 | };
|
| 2220 |
|
| 2221 | static const struct drm_driver amdgpu_kms_driver;
|
| 2222 |
|
| 2223 | static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev)
|
| 2224 | {
|
| 2225 | struct pci_dev *p = NULL;
|
| 2226 | int i;
|
| 2227 |
|
| 2228 | |
| 2229 | * 1 - audio
|
| 2230 | * 2 - USB
|
| 2231 | * 3 - UCSI
|
| 2232 |
|
| 2233 | for (i = 1; i < 4; i++) {
|
| 2234 | p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
|
| 2235 | adev->pdev->bus->number, i);
|
| 2236 | if (p) {
|
| 2237 | pm_runtime_get_sync(&p->dev);
|
| 2238 | pm_runtime_put_autosuspend(&p->dev);
|
| 2239 | pci_dev_put(p);
|
| 2240 | }
|
| 2241 | }
|
| 2242 | }
|
| 2243 |
|
| 2244 | static void amdgpu_init_debug_options(struct amdgpu_device *adev)
|
| 2245 | {
|
| 2246 | if (amdgpu_debug_mask & AMDGPU_DEBUG_VM) {
|
| 2247 | pr_info("debug: VM handling debug enabled\n");
|
| 2248 | adev->debug_vm = true;
|
| 2249 | }
|
| 2250 |
|
| 2251 | if (amdgpu_debug_mask & AMDGPU_DEBUG_LARGEBAR) {
|
| 2252 | pr_info("debug: enabled simulating large-bar capability on non-large bar system\n");
|
| 2253 | adev->debug_largebar = true;
|
| 2254 | }
|
| 2255 |
|
| 2256 | if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY) {
|
| 2257 | pr_info("debug: soft recovery disabled\n");
|
| 2258 | adev->debug_disable_soft_recovery = true;
|
| 2259 | }
|
| 2260 |
|
| 2261 | if (amdgpu_debug_mask & AMDGPU_DEBUG_USE_VRAM_FW_BUF) {
|
| 2262 | pr_info("debug: place fw in vram for frontdoor loading\n");
|
| 2263 | adev->debug_use_vram_fw_buf = true;
|
| 2264 | }
|
| 2265 |
|
| 2266 | if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_EXP_RESETS) {
|
| 2267 | pr_info("debug: enable experimental reset features\n");
|
| 2268 | adev->debug_exp_resets = true;
|
| 2269 | }
|
| 2270 |
|
| 2271 | if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_RING_RESET) {
|
| 2272 | pr_info("debug: ring reset disabled\n");
|
| 2273 | adev->debug_disable_gpu_ring_reset = true;
|
| 2274 | }
|
| 2275 | if (amdgpu_debug_mask & AMDGPU_DEBUG_SMU_POOL) {
|
| 2276 | pr_info("debug: use vram for smu pool\n");
|
| 2277 | adev->pm.smu_debug_mask |= SMU_DEBUG_POOL_USE_VRAM;
|
| 2278 | }
|
| 2279 | if (amdgpu_debug_mask & AMDGPU_DEBUG_VM_USERPTR) {
|
| 2280 | pr_info("debug: VM mode debug for userptr is enabled\n");
|
| 2281 | adev->debug_vm_userptr = true;
|
| 2282 | }
|
| 2283 |
|
| 2284 | if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_RAS_CE_LOG) {
|
| 2285 | pr_info("debug: disable kernel logs of correctable errors\n");
|
| 2286 | adev->debug_disable_ce_logs = true;
|
| 2287 | }
|
| 2288 |
|
| 2289 | if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_CE_CS) {
|
| 2290 | pr_info("debug: allowing command submission to CE engine\n");
|
| 2291 | adev->debug_enable_ce_cs = true;
|
| 2292 | }
|
| 2293 |
|
| 2294 | if (amdgpu_debug_mask & AMDGPU_DEBUG_HIBERNATION_THAW_RESUME_GPU) {
|
| 2295 | pr_info("debug: resume gpu in thaw() of hibernation\n");
|
| 2296 | adev->debug_hibernation_thaw_resume_gpu = true;
|
| 2297 | }
|
| 2298 |
|
| 2299 | if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_IP_BLOCK_SOFT_RESET) {
|
| 2300 | pr_info("debug: IP block soft reset disabled\n");
|
| 2301 | adev->debug_disable_ip_block_soft_reset = true;
|
| 2302 | }
|
| 2303 | }
|
| 2304 |
|
| 2305 | static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags)
|
| 2306 | {
|
| 2307 | int i;
|
| 2308 |
|
| 2309 | for (i = 0; i < ARRAY_SIZE(asic_type_quirks); i++) {
|
| 2310 | if (pdev->device == asic_type_quirks[i].device &&
|
| 2311 | pdev->revision == asic_type_quirks[i].revision) {
|
| 2312 | flags &= ~AMD_ASIC_MASK;
|
| 2313 | flags |= asic_type_quirks[i].type;
|
| 2314 | break;
|
| 2315 | }
|
| 2316 | }
|
| 2317 |
|
| 2318 | return flags;
|
| 2319 | }
|
| 2320 |
|
| 2321 | static bool amdgpu_support_enabled(struct device *dev,
|
| 2322 | const enum amd_asic_type family)
|
| 2323 | {
|
| 2324 | const char *gen;
|
| 2325 | const char *param;
|
| 2326 | int module_param = -1;
|
| 2327 | bool radeon_support_built = IS_ENABLED(CONFIG_DRM_RADEON);
|
| 2328 | bool amdgpu_support_built = false;
|
| 2329 | bool support_by_default = false;
|
| 2330 |
|
| 2331 | switch (family) {
|
| 2332 | case CHIP_TAHITI:
|
| 2333 | case CHIP_PITCAIRN:
|
| 2334 | case CHIP_VERDE:
|
| 2335 | case CHIP_OLAND:
|
| 2336 | case CHIP_HAINAN:
|
| 2337 | gen = "SI";
|
| 2338 | param = "si_support";
|
| 2339 | module_param = amdgpu_si_support;
|
| 2340 | amdgpu_support_built = IS_ENABLED(CONFIG_DRM_AMDGPU_SI);
|
| 2341 | support_by_default = true;
|
| 2342 | break;
|
| 2343 |
|
| 2344 | case CHIP_BONAIRE:
|
| 2345 | case CHIP_HAWAII:
|
| 2346 | case CHIP_KAVERI:
|
| 2347 | case CHIP_KABINI:
|
| 2348 | case CHIP_MULLINS:
|
| 2349 | gen = "CIK";
|
| 2350 | param = "cik_support";
|
| 2351 | module_param = amdgpu_cik_support;
|
| 2352 | amdgpu_support_built = IS_ENABLED(CONFIG_DRM_AMDGPU_CIK);
|
| 2353 | support_by_default = true;
|
| 2354 | break;
|
| 2355 |
|
| 2356 | default:
|
| 2357 |
|
| 2358 | return true;
|
| 2359 | }
|
| 2360 |
|
| 2361 | if (!amdgpu_support_built) {
|
| 2362 | dev_info(dev, "amdgpu built without %s support\n", gen);
|
| 2363 | return false;
|
| 2364 | }
|
| 2365 |
|
| 2366 | if ((module_param == -1 && (support_by_default || !radeon_support_built)) ||
|
| 2367 | module_param == 1) {
|
| 2368 | if (radeon_support_built)
|
| 2369 | dev_info(dev, "%s support provided by amdgpu.\n"
|
| 2370 | "Use radeon.%s=1 amdgpu.%s=0 to override.\n",
|
| 2371 | gen, param, param);
|
| 2372 |
|
| 2373 | return true;
|
| 2374 | }
|
| 2375 |
|
| 2376 | if (radeon_support_built)
|
| 2377 | dev_info(dev, "%s support provided by radeon.\n"
|
| 2378 | "Use radeon.%s=0 amdgpu.%s=1 to override.\n",
|
| 2379 | gen, param, param);
|
| 2380 | else if (module_param == 0)
|
| 2381 | dev_info(dev, "%s support disabled by module param\n", gen);
|
| 2382 |
|
| 2383 | return false;
|
| 2384 | }
|
| 2385 |
|
| 2386 | static int amdgpu_pci_probe(struct pci_dev *pdev,
|
| 2387 | const struct pci_device_id *ent)
|
| 2388 | {
|
| 2389 | struct drm_device *ddev;
|
| 2390 | struct amdgpu_device *adev;
|
| 2391 | unsigned long flags = ent->driver_data;
|
| 2392 | int ret, retry = 0, i;
|
| 2393 | bool supports_atomic = false;
|
| 2394 |
|
| 2395 | if ((pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA ||
|
| 2396 | (pdev->class >> 8) == PCI_CLASS_DISPLAY_OTHER) {
|
| 2397 | if (drm_firmware_drivers_only() && amdgpu_modeset == -1)
|
| 2398 | return -EINVAL;
|
| 2399 | }
|
| 2400 |
|
| 2401 |
|
| 2402 | for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) {
|
| 2403 | if (amdgpu_unsupported_pciidlist[i] == pdev->device)
|
| 2404 | return -ENODEV;
|
| 2405 | }
|
| 2406 |
|
| 2407 | if (amdgpu_virtual_display ||
|
| 2408 | amdgpu_device_asic_has_dc_support(pdev, flags & AMD_ASIC_MASK))
|
| 2409 | supports_atomic = true;
|
| 2410 |
|
| 2411 | if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
|
| 2412 | dev_info(&pdev->dev, "This hardware requires experimental hardware support.\n"
|
| 2413 | "See modparam exp_hw_support\n");
|
| 2414 | return -ENODEV;
|
| 2415 | }
|
| 2416 |
|
| 2417 | flags = amdgpu_fix_asic_type(pdev, flags);
|
| 2418 |
|
| 2419 | |
| 2420 | * however, SME requires an indirect IOMMU mapping because the encryption
|
| 2421 | * bit is beyond the DMA mask of the chip.
|
| 2422 |
|
| 2423 | if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) &&
|
| 2424 | ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) {
|
| 2425 | dev_info(&pdev->dev,
|
| 2426 | "SME is not compatible with RAVEN\n");
|
| 2427 | return -ENOTSUPP;
|
| 2428 | }
|
| 2429 |
|
| 2430 | if (!amdgpu_support_enabled(&pdev->dev, flags & AMD_ASIC_MASK))
|
| 2431 | return -ENODEV;
|
| 2432 |
|
| 2433 | adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev);
|
| 2434 | if (IS_ERR(adev))
|
| 2435 | return PTR_ERR(adev);
|
| 2436 |
|
| 2437 | adev->dev = &pdev->dev;
|
| 2438 | adev->pdev = pdev;
|
| 2439 | ddev = adev_to_drm(adev);
|
| 2440 |
|
| 2441 | if (!supports_atomic)
|
| 2442 | ddev->driver_features &= ~DRIVER_ATOMIC;
|
| 2443 |
|
| 2444 | ret = pci_enable_device(pdev);
|
| 2445 | if (ret)
|
| 2446 | return ret;
|
| 2447 |
|
| 2448 | pci_set_drvdata(pdev, ddev);
|
| 2449 |
|
| 2450 | amdgpu_init_debug_options(adev);
|
| 2451 |
|
| 2452 | ret = amdgpu_driver_load_kms(adev, flags);
|
| 2453 | if (ret)
|
| 2454 | goto err_pci;
|
| 2455 |
|
| 2456 | retry_init:
|
| 2457 | ret = drm_dev_register(ddev, flags);
|
| 2458 | if (ret == -EAGAIN && ++retry <= 3) {
|
| 2459 | drm_info(adev_to_drm(adev), "retry init %d\n", retry);
|
| 2460 |
|
| 2461 | msleep(5000);
|
| 2462 | goto retry_init;
|
| 2463 | } else if (ret) {
|
| 2464 | goto err_pci;
|
| 2465 | }
|
| 2466 |
|
| 2467 | ret = amdgpu_xcp_dev_register(adev, ent);
|
| 2468 | if (ret)
|
| 2469 | goto err_pci;
|
| 2470 |
|
| 2471 | ret = amdgpu_amdkfd_drm_client_create(adev);
|
| 2472 | if (ret)
|
| 2473 | goto err_pci;
|
| 2474 |
|
| 2475 | |
| 2476 | * 1. don't init fbdev on hw without DCE
|
| 2477 | * 2. don't init fbdev if there are no connectors
|
| 2478 |
|
| 2479 | if (adev->mode_info.mode_config_initialized &&
|
| 2480 | !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) {
|
| 2481 | const struct drm_format_info *format;
|
| 2482 |
|
| 2483 |
|
| 2484 | if (adev->gmc.real_vram_size <= (32*1024*1024))
|
| 2485 | format = drm_format_info(DRM_FORMAT_C8);
|
| 2486 | else
|
| 2487 | format = NULL;
|
| 2488 |
|
| 2489 | drm_client_setup(adev_to_drm(adev), format);
|
| 2490 | }
|
| 2491 |
|
| 2492 | ret = amdgpu_debugfs_init(adev);
|
| 2493 | if (ret)
|
| 2494 | DRM_ERROR("Creating debugfs files failed (%d).\n", ret);
|
| 2495 |
|
| 2496 | if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {
|
| 2497 |
|
| 2498 | if (amdgpu_device_supports_px(adev))
|
| 2499 | dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
|
| 2500 |
|
| 2501 | if (amdgpu_device_supports_boco(adev))
|
| 2502 | dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE |
|
| 2503 | DPM_FLAG_SMART_SUSPEND |
|
| 2504 | DPM_FLAG_MAY_SKIP_RESUME);
|
| 2505 | pm_runtime_use_autosuspend(ddev->dev);
|
| 2506 | pm_runtime_set_autosuspend_delay(ddev->dev, 5000);
|
| 2507 |
|
| 2508 | pm_runtime_allow(ddev->dev);
|
| 2509 |
|
| 2510 | pm_runtime_put_autosuspend(ddev->dev);
|
| 2511 |
|
| 2512 | pci_wake_from_d3(pdev, TRUE);
|
| 2513 |
|
| 2514 | |
| 2515 | * For runpm implemented via BACO, PMFW will handle the
|
| 2516 | * timing for BACO in and out:
|
| 2517 | * - put ASIC into BACO state only when both video and
|
| 2518 | * audio functions are in D3 state.
|
| 2519 | * - pull ASIC out of BACO state when either video or
|
| 2520 | * audio function is in D0 state.
|
| 2521 | * Also, at startup, PMFW assumes both functions are in
|
| 2522 | * D0 state.
|
| 2523 | *
|
| 2524 | * So if snd driver was loaded prior to amdgpu driver
|
| 2525 | * and audio function was put into D3 state, there will
|
| 2526 | * be no PMFW-aware D-state transition(D0->D3) on runpm
|
| 2527 | * suspend. Thus the BACO will be not correctly kicked in.
|
| 2528 | *
|
| 2529 | * Via amdgpu_get_secondary_funcs(), the audio dev is put
|
| 2530 | * into D0 state. Then there will be a PMFW-aware D-state
|
| 2531 | * transition(D0->D3) on runpm suspend.
|
| 2532 |
|
| 2533 | if (amdgpu_device_supports_baco(adev) &&
|
| 2534 | !(adev->flags & AMD_IS_APU) &&
|
| 2535 | adev->asic_type >= CHIP_NAVI10)
|
| 2536 | amdgpu_get_secondary_funcs(adev);
|
| 2537 | }
|
| 2538 |
|
| 2539 | return 0;
|
| 2540 |
|
| 2541 | err_pci:
|
| 2542 | pci_disable_device(pdev);
|
| 2543 | return ret;
|
| 2544 | }
|
| 2545 |
|
| 2546 | static void
|
| 2547 | amdgpu_pci_remove(struct pci_dev *pdev)
|
| 2548 | {
|
| 2549 | struct drm_device *dev = pci_get_drvdata(pdev);
|
| 2550 | struct amdgpu_device *adev = drm_to_adev(dev);
|
| 2551 |
|
| 2552 | amdgpu_ras_eeprom_check_and_recover(adev);
|
| 2553 | amdgpu_xcp_dev_unplug(adev);
|
| 2554 | amdgpu_gmc_prepare_nps_mode_change(adev);
|
| 2555 | drm_dev_unplug(dev);
|
| 2556 |
|
| 2557 | if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {
|
| 2558 | pm_runtime_get_sync(dev->dev);
|
| 2559 | pm_runtime_forbid(dev->dev);
|
| 2560 | pm_runtime_dont_use_autosuspend(dev->dev);
|
| 2561 | }
|
| 2562 |
|
| 2563 | amdgpu_driver_unload_kms(dev);
|
| 2564 |
|
| 2565 | amdgpu_discovery_sysfs_early_fini(pdev);
|
| 2566 |
|
| 2567 | |
| 2568 | * Flush any in flight DMA operations from device.
|
| 2569 | * Clear the Bus Master Enable bit and then wait on the PCIe Device
|
| 2570 | * StatusTransactions Pending bit.
|
| 2571 |
|
| 2572 | pci_disable_device(pdev);
|
| 2573 | pci_wait_for_pending_transaction(pdev);
|
| 2574 | }
|
| 2575 |
|
| 2576 | static void
|
| 2577 | amdgpu_pci_shutdown(struct pci_dev *pdev)
|
| 2578 | {
|
| 2579 | struct drm_device *dev = pci_get_drvdata(pdev);
|
| 2580 | struct amdgpu_device *adev = drm_to_adev(dev);
|
| 2581 |
|
| 2582 | if (amdgpu_ras_intr_triggered())
|
| 2583 | return;
|
| 2584 |
|
| 2585 |
|
| 2586 | if (adev->in_s4 && adev->in_suspend)
|
| 2587 | return;
|
| 2588 |
|
| 2589 | |
| 2590 | * torn down properly on reboot/shutdown.
|
| 2591 | * unfortunately we can't detect certain
|
| 2592 | * hypervisors so just do this all the time.
|
| 2593 |
|
| 2594 | if (!amdgpu_passthrough(adev))
|
| 2595 | adev->mp1_state = PP_MP1_STATE_UNLOAD;
|
| 2596 | amdgpu_device_prepare(dev);
|
| 2597 | amdgpu_device_suspend(dev, true);
|
| 2598 | adev->mp1_state = PP_MP1_STATE_NONE;
|
| 2599 | }
|
| 2600 |
|
| 2601 | static int amdgpu_pmops_prepare(struct device *dev)
|
| 2602 | {
|
| 2603 | struct drm_device *drm_dev = dev_get_drvdata(dev);
|
| 2604 | struct amdgpu_device *adev = drm_to_adev(drm_dev);
|
| 2605 |
|
| 2606 |
|
| 2607 | if (adev->in_s4 && adev->in_suspend)
|
| 2608 | return 0;
|
| 2609 |
|
| 2610 | |
| 2611 | * DPM_FLAG_SMART_SUSPEND works properly
|
| 2612 |
|
| 2613 | if (amdgpu_device_supports_boco(adev) && pm_runtime_suspended(dev))
|
| 2614 | return 1;
|
| 2615 |
|
| 2616 | |
| 2617 | * then skip suspend
|
| 2618 |
|
| 2619 | if (!amdgpu_acpi_is_s0ix_active(adev) &&
|
| 2620 | !amdgpu_acpi_is_s3_active(adev))
|
| 2621 | return 1;
|
| 2622 |
|
| 2623 | return amdgpu_device_prepare(drm_dev);
|
| 2624 | }
|
| 2625 |
|
| 2626 | static void amdgpu_pmops_complete(struct device *dev)
|
| 2627 | {
|
| 2628 | amdgpu_device_complete(dev_get_drvdata(dev));
|
| 2629 | }
|
| 2630 |
|
| 2631 | static int amdgpu_pmops_suspend(struct device *dev)
|
| 2632 | {
|
| 2633 | struct drm_device *drm_dev = dev_get_drvdata(dev);
|
| 2634 | struct amdgpu_device *adev = drm_to_adev(drm_dev);
|
| 2635 |
|
| 2636 | if (amdgpu_acpi_is_s0ix_active(adev))
|
| 2637 | adev->in_s0ix = true;
|
| 2638 | else if (amdgpu_acpi_is_s3_active(adev))
|
| 2639 | adev->in_s3 = true;
|
| 2640 | if (!adev->in_s0ix && !adev->in_s3) {
|
| 2641 | #if IS_ENABLED(CONFIG_SUSPEND)
|
| 2642 |
|
| 2643 | if (adev->last_suspend_state != PM_SUSPEND_ON &&
|
| 2644 | adev->last_suspend_state != pm_suspend_target_state) {
|
| 2645 | drm_err_once(drm_dev, "Unsupported suspend state %d\n",
|
| 2646 | pm_suspend_target_state);
|
| 2647 | return -EINVAL;
|
| 2648 | }
|
| 2649 | #endif
|
| 2650 | return 0;
|
| 2651 | }
|
| 2652 |
|
| 2653 | #if IS_ENABLED(CONFIG_SUSPEND)
|
| 2654 |
|
| 2655 | adev->last_suspend_state = pm_suspend_target_state;
|
| 2656 | #endif
|
| 2657 |
|
| 2658 | return amdgpu_device_suspend(drm_dev, true);
|
| 2659 | }
|
| 2660 |
|
| 2661 | static int amdgpu_pmops_suspend_noirq(struct device *dev)
|
| 2662 | {
|
| 2663 | struct drm_device *drm_dev = dev_get_drvdata(dev);
|
| 2664 | struct amdgpu_device *adev = drm_to_adev(drm_dev);
|
| 2665 | int r;
|
| 2666 |
|
| 2667 | |
| 2668 | * A GPU parked by vga_switcheroo has no power and no PCIe link, so the
|
| 2669 | * ASIC reset below would fail and abort the whole noirq suspend phase.
|
| 2670 | * Bail out like amdgpu_device_prepare/suspend/resume() already do.
|
| 2671 |
|
| 2672 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
|
| 2673 | return 0;
|
| 2674 |
|
| 2675 | if (amdgpu_acpi_should_gpu_reset(adev)) {
|
| 2676 | amdgpu_device_lock_reset_domain(adev->reset_domain);
|
| 2677 | r = amdgpu_asic_reset(adev);
|
| 2678 | amdgpu_device_unlock_reset_domain(adev->reset_domain);
|
| 2679 | return r;
|
| 2680 | }
|
| 2681 |
|
| 2682 | return 0;
|
| 2683 | }
|
| 2684 |
|
| 2685 | static int amdgpu_pmops_resume(struct device *dev)
|
| 2686 | {
|
| 2687 | struct drm_device *drm_dev = dev_get_drvdata(dev);
|
| 2688 | struct amdgpu_device *adev = drm_to_adev(drm_dev);
|
| 2689 | int r;
|
| 2690 |
|
| 2691 | if (!adev->in_s0ix && !adev->in_s3)
|
| 2692 | return 0;
|
| 2693 |
|
| 2694 |
|
| 2695 | if (!pci_device_is_present(adev->pdev))
|
| 2696 | adev->no_hw_access = true;
|
| 2697 |
|
| 2698 | r = amdgpu_device_resume(drm_dev, true);
|
| 2699 | if (amdgpu_acpi_is_s0ix_active(adev))
|
| 2700 | adev->in_s0ix = false;
|
| 2701 | else
|
| 2702 | adev->in_s3 = false;
|
| 2703 | return r;
|
| 2704 | }
|
| 2705 |
|
| 2706 | static int amdgpu_pmops_freeze(struct device *dev)
|
| 2707 | {
|
| 2708 | struct drm_device *drm_dev = dev_get_drvdata(dev);
|
| 2709 | struct amdgpu_device *adev = drm_to_adev(drm_dev);
|
| 2710 | int r;
|
| 2711 |
|
| 2712 | r = amdgpu_device_suspend(drm_dev, true);
|
| 2713 | if (r)
|
| 2714 | return r;
|
| 2715 |
|
| 2716 | if (amdgpu_acpi_should_gpu_reset(adev)) {
|
| 2717 | amdgpu_device_lock_reset_domain(adev->reset_domain);
|
| 2718 | r = amdgpu_asic_reset(adev);
|
| 2719 | amdgpu_device_unlock_reset_domain(adev->reset_domain);
|
| 2720 | return r;
|
| 2721 | }
|
| 2722 | return 0;
|
| 2723 | }
|
| 2724 |
|
| 2725 | static int amdgpu_pmops_thaw(struct device *dev)
|
| 2726 | {
|
| 2727 | struct drm_device *drm_dev = dev_get_drvdata(dev);
|
| 2728 | struct amdgpu_device *adev = drm_to_adev(drm_dev);
|
| 2729 |
|
| 2730 |
|
| 2731 | if (!adev->debug_hibernation_thaw_resume_gpu &&
|
| 2732 | !pm_hibernate_is_recovering() &&
|
| 2733 | !pm_hibernation_mode_is_suspend())
|
| 2734 | return 0;
|
| 2735 |
|
| 2736 | return amdgpu_device_resume(drm_dev, true);
|
| 2737 | }
|
| 2738 |
|
| 2739 | static int amdgpu_pmops_poweroff(struct device *dev)
|
| 2740 | {
|
| 2741 | struct drm_device *drm_dev = dev_get_drvdata(dev);
|
| 2742 | struct amdgpu_device *adev = drm_to_adev(drm_dev);
|
| 2743 |
|
| 2744 |
|
| 2745 | if (adev->in_s4 && adev->in_suspend)
|
| 2746 | return 0;
|
| 2747 |
|
| 2748 | return amdgpu_device_suspend(drm_dev, true);
|
| 2749 | }
|
| 2750 |
|
| 2751 | static int amdgpu_pmops_restore(struct device *dev)
|
| 2752 | {
|
| 2753 | struct drm_device *drm_dev = dev_get_drvdata(dev);
|
| 2754 |
|
| 2755 | return amdgpu_device_resume(drm_dev, true);
|
| 2756 | }
|
| 2757 |
|
| 2758 | static int amdgpu_runtime_idle_check_display(struct device *dev)
|
| 2759 | {
|
| 2760 | struct pci_dev *pdev = to_pci_dev(dev);
|
| 2761 | struct drm_device *drm_dev = pci_get_drvdata(pdev);
|
| 2762 | struct amdgpu_device *adev = drm_to_adev(drm_dev);
|
| 2763 |
|
| 2764 | if (adev->mode_info.num_crtc) {
|
| 2765 | struct drm_connector *list_connector;
|
| 2766 | struct drm_connector_list_iter iter;
|
| 2767 | int ret = 0;
|
| 2768 |
|
| 2769 | if (amdgpu_runtime_pm != -2) {
|
| 2770 | |
| 2771 | * possible display wakeups after runtime resume due to
|
| 2772 | * hotplug events in case any displays were connected while
|
| 2773 | * the GPU was in suspend. Remove this once that is fixed.
|
| 2774 |
|
| 2775 | mutex_lock(&drm_dev->mode_config.mutex);
|
| 2776 | drm_connector_list_iter_begin(drm_dev, &iter);
|
| 2777 | drm_for_each_connector_iter(list_connector, &iter) {
|
| 2778 | if (list_connector->status == connector_status_connected) {
|
| 2779 | ret = -EBUSY;
|
| 2780 | break;
|
| 2781 | }
|
| 2782 | }
|
| 2783 | drm_connector_list_iter_end(&iter);
|
| 2784 | mutex_unlock(&drm_dev->mode_config.mutex);
|
| 2785 |
|
| 2786 | if (ret)
|
| 2787 | return ret;
|
| 2788 | }
|
| 2789 |
|
| 2790 | if (adev->dc_enabled) {
|
| 2791 | struct drm_crtc *crtc;
|
| 2792 |
|
| 2793 | drm_for_each_crtc(crtc, drm_dev) {
|
| 2794 | drm_modeset_lock(&crtc->mutex, NULL);
|
| 2795 | if (crtc->state->active)
|
| 2796 | ret = -EBUSY;
|
| 2797 | drm_modeset_unlock(&crtc->mutex);
|
| 2798 | if (ret < 0)
|
| 2799 | break;
|
| 2800 | }
|
| 2801 | } else {
|
| 2802 | mutex_lock(&drm_dev->mode_config.mutex);
|
| 2803 | drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);
|
| 2804 |
|
| 2805 | drm_connector_list_iter_begin(drm_dev, &iter);
|
| 2806 | drm_for_each_connector_iter(list_connector, &iter) {
|
| 2807 | if (list_connector->dpms == DRM_MODE_DPMS_ON) {
|
| 2808 | ret = -EBUSY;
|
| 2809 | break;
|
| 2810 | }
|
| 2811 | }
|
| 2812 |
|
| 2813 | drm_connector_list_iter_end(&iter);
|
| 2814 |
|
| 2815 | drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);
|
| 2816 | mutex_unlock(&drm_dev->mode_config.mutex);
|
| 2817 | }
|
| 2818 | if (ret)
|
| 2819 | return ret;
|
| 2820 | }
|
| 2821 |
|
| 2822 | return 0;
|
| 2823 | }
|
| 2824 |
|
| 2825 | static int amdgpu_runtime_idle_check_userq(struct device *dev)
|
| 2826 | {
|
| 2827 | struct pci_dev *pdev = to_pci_dev(dev);
|
| 2828 | struct drm_device *drm_dev = pci_get_drvdata(pdev);
|
| 2829 | struct amdgpu_device *adev = drm_to_adev(drm_dev);
|
| 2830 |
|
| 2831 | return xa_empty(&adev->userq_doorbell_xa) ? 0 : -EBUSY;
|
| 2832 | }
|
| 2833 |
|
| 2834 | static int amdgpu_pmops_runtime_checks(struct device *dev)
|
| 2835 | {
|
| 2836 | struct drm_device *drm_dev = dev_get_drvdata(dev);
|
| 2837 | struct amdgpu_device *adev = drm_to_adev(drm_dev);
|
| 2838 | int ret;
|
| 2839 |
|
| 2840 | if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) {
|
| 2841 | pm_runtime_forbid(dev);
|
| 2842 | return -EBUSY;
|
| 2843 | }
|
| 2844 |
|
| 2845 | ret = amdgpu_runtime_idle_check_display(dev);
|
| 2846 | if (ret)
|
| 2847 | return ret;
|
| 2848 |
|
| 2849 | return amdgpu_runtime_idle_check_userq(dev);
|
| 2850 | }
|
| 2851 |
|
| 2852 | static int amdgpu_pmops_runtime_idle(struct device *dev)
|
| 2853 | {
|
| 2854 | int ret;
|
| 2855 |
|
| 2856 | ret = amdgpu_pmops_runtime_checks(dev);
|
| 2857 | pm_runtime_autosuspend(dev);
|
| 2858 | return ret;
|
| 2859 | }
|
| 2860 |
|
| 2861 | static int amdgpu_pmops_runtime_suspend(struct device *dev)
|
| 2862 | {
|
| 2863 | struct pci_dev *pdev = to_pci_dev(dev);
|
| 2864 | struct drm_device *drm_dev = pci_get_drvdata(pdev);
|
| 2865 | struct amdgpu_device *adev = drm_to_adev(drm_dev);
|
| 2866 | int ret, i;
|
| 2867 |
|
| 2868 | ret = amdgpu_pmops_runtime_checks(dev);
|
| 2869 | if (ret)
|
| 2870 | return ret;
|
| 2871 |
|
| 2872 |
|
| 2873 | for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
|
| 2874 | struct amdgpu_ring *ring = adev->rings[i];
|
| 2875 |
|
| 2876 | if (ring && ring->sched.ready) {
|
| 2877 | ret = amdgpu_fence_wait_empty(ring);
|
| 2878 | if (ret)
|
| 2879 | return -EBUSY;
|
| 2880 | }
|
| 2881 | }
|
| 2882 |
|
| 2883 | adev->in_runpm = true;
|
| 2884 | if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX)
|
| 2885 | drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
|
| 2886 |
|
| 2887 | |
| 2888 | * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some
|
| 2889 | * proper cleanups and put itself into a state ready for PNP. That
|
| 2890 | * can address some random resuming failure observed on BOCO capable
|
| 2891 | * platforms.
|
| 2892 | * TODO: this may be also needed for PX capable platform.
|
| 2893 |
|
| 2894 | if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO)
|
| 2895 | adev->mp1_state = PP_MP1_STATE_UNLOAD;
|
| 2896 |
|
| 2897 | ret = amdgpu_device_prepare(drm_dev);
|
| 2898 | if (ret)
|
| 2899 | return ret;
|
| 2900 | ret = amdgpu_device_suspend(drm_dev, false);
|
| 2901 | if (ret) {
|
| 2902 | adev->in_runpm = false;
|
| 2903 | if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO)
|
| 2904 | adev->mp1_state = PP_MP1_STATE_NONE;
|
| 2905 | return ret;
|
| 2906 | }
|
| 2907 |
|
| 2908 | if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO)
|
| 2909 | adev->mp1_state = PP_MP1_STATE_NONE;
|
| 2910 |
|
| 2911 | if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) {
|
| 2912 | |
| 2913 | * PCI core handles it for _PR3.
|
| 2914 |
|
| 2915 | amdgpu_device_cache_pci_state(pdev);
|
| 2916 | pci_disable_device(pdev);
|
| 2917 | pci_ignore_hotplug(pdev);
|
| 2918 | pci_set_power_state(pdev, PCI_D3cold);
|
| 2919 | drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
|
| 2920 | } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) {
|
| 2921 |
|
| 2922 | } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) ||
|
| 2923 | (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) {
|
| 2924 | amdgpu_device_baco_enter(adev);
|
| 2925 | }
|
| 2926 |
|
| 2927 | dev_dbg(&pdev->dev, "asic/device is runtime suspended\n");
|
| 2928 |
|
| 2929 | return 0;
|
| 2930 | }
|
| 2931 |
|
| 2932 | static void amdgpu_restore_umd_profile_pstate_after_runpm(struct amdgpu_device *adev)
|
| 2933 | {
|
| 2934 | enum amd_dpm_forced_level level;
|
| 2935 | uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
|
| 2936 | AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
|
| 2937 | AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
|
| 2938 | AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
|
| 2939 |
|
| 2940 | level = amdgpu_dpm_get_performance_level(adev);
|
| 2941 | if (level & profile_mode_mask)
|
| 2942 | amdgpu_asic_update_umd_stable_pstate(adev, true);
|
| 2943 | }
|
| 2944 |
|
| 2945 | static int amdgpu_pmops_runtime_resume(struct device *dev)
|
| 2946 | {
|
| 2947 | struct pci_dev *pdev = to_pci_dev(dev);
|
| 2948 | struct drm_device *drm_dev = pci_get_drvdata(pdev);
|
| 2949 | struct amdgpu_device *adev = drm_to_adev(drm_dev);
|
| 2950 | int ret;
|
| 2951 |
|
| 2952 | if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE)
|
| 2953 | return -EINVAL;
|
| 2954 |
|
| 2955 |
|
| 2956 | if (!pci_device_is_present(adev->pdev))
|
| 2957 | adev->no_hw_access = true;
|
| 2958 |
|
| 2959 | if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) {
|
| 2960 | drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
|
| 2961 |
|
| 2962 | |
| 2963 | * PCI core handles it for _PR3.
|
| 2964 |
|
| 2965 | pci_set_power_state(pdev, PCI_D0);
|
| 2966 | amdgpu_device_load_pci_state(pdev);
|
| 2967 | ret = pci_enable_device(pdev);
|
| 2968 | if (ret)
|
| 2969 | return ret;
|
| 2970 | pci_set_master(pdev);
|
| 2971 | } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) {
|
| 2972 | |
| 2973 | * PCI core handles it for _PR3.
|
| 2974 |
|
| 2975 | pci_set_master(pdev);
|
| 2976 | } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) ||
|
| 2977 | (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) {
|
| 2978 | amdgpu_device_baco_exit(adev);
|
| 2979 | }
|
| 2980 | ret = amdgpu_device_resume(drm_dev, false);
|
| 2981 | if (ret) {
|
| 2982 | if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX)
|
| 2983 | pci_disable_device(pdev);
|
| 2984 | return ret;
|
| 2985 | }
|
| 2986 |
|
| 2987 | if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX)
|
| 2988 | drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
|
| 2989 |
|
| 2990 | amdgpu_restore_umd_profile_pstate_after_runpm(adev);
|
| 2991 | adev->in_runpm = false;
|
| 2992 | return 0;
|
| 2993 | }
|
| 2994 |
|
| 2995 | static int amdgpu_drm_release(struct inode *inode, struct file *filp)
|
| 2996 | {
|
| 2997 | struct drm_file *file_priv = filp->private_data;
|
| 2998 | struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
|
| 2999 | struct drm_device *dev = file_priv->minor->dev;
|
| 3000 | int idx;
|
| 3001 |
|
| 3002 | if (fpriv && drm_dev_enter(dev, &idx)) {
|
| 3003 | amdgpu_evf_mgr_shutdown(&fpriv->evf_mgr);
|
| 3004 | amdgpu_userq_mgr_cancel_resume(&fpriv->userq_mgr);
|
| 3005 | amdgpu_evf_mgr_flush_suspend(&fpriv->evf_mgr);
|
| 3006 | amdgpu_userq_mgr_fini(&fpriv->userq_mgr);
|
| 3007 | amdgpu_evf_mgr_fini(&fpriv->evf_mgr);
|
| 3008 | drm_dev_exit(idx);
|
| 3009 | }
|
| 3010 |
|
| 3011 | return drm_release(inode, filp);
|
| 3012 | }
|
| 3013 |
|
| 3014 | long amdgpu_drm_ioctl(struct file *filp,
|
| 3015 | unsigned int cmd, unsigned long arg)
|
| 3016 | {
|
| 3017 | struct drm_file *file_priv = filp->private_data;
|
| 3018 | struct drm_device *dev;
|
| 3019 | long ret;
|
| 3020 |
|
| 3021 | dev = file_priv->minor->dev;
|
| 3022 | ret = pm_runtime_get_sync(dev->dev);
|
| 3023 | if (ret < 0)
|
| 3024 | goto out;
|
| 3025 |
|
| 3026 | ret = drm_ioctl(filp, cmd, arg);
|
| 3027 |
|
| 3028 | out:
|
| 3029 | pm_runtime_put_autosuspend(dev->dev);
|
| 3030 | return ret;
|
| 3031 | }
|
| 3032 |
|
| 3033 | static const struct dev_pm_ops amdgpu_pm_ops = {
|
| 3034 | .prepare = pm_sleep_ptr(amdgpu_pmops_prepare),
|
| 3035 | .complete = pm_sleep_ptr(amdgpu_pmops_complete),
|
| 3036 | .suspend = pm_sleep_ptr(amdgpu_pmops_suspend),
|
| 3037 | .suspend_noirq = pm_sleep_ptr(amdgpu_pmops_suspend_noirq),
|
| 3038 | .resume = pm_sleep_ptr(amdgpu_pmops_resume),
|
| 3039 | .freeze = pm_sleep_ptr(amdgpu_pmops_freeze),
|
| 3040 | .thaw = pm_sleep_ptr(amdgpu_pmops_thaw),
|
| 3041 | .poweroff = pm_sleep_ptr(amdgpu_pmops_poweroff),
|
| 3042 | .restore = pm_sleep_ptr(amdgpu_pmops_restore),
|
| 3043 | .runtime_suspend = amdgpu_pmops_runtime_suspend,
|
| 3044 | .runtime_resume = amdgpu_pmops_runtime_resume,
|
| 3045 | .runtime_idle = amdgpu_pmops_runtime_idle,
|
| 3046 | };
|
| 3047 |
|
| 3048 | static int amdgpu_flush(struct file *f, fl_owner_t id)
|
| 3049 | {
|
| 3050 | struct drm_file *file_priv = f->private_data;
|
| 3051 | struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
|
| 3052 | long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY;
|
| 3053 |
|
| 3054 | timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout);
|
| 3055 | timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
|
| 3056 |
|
| 3057 | return timeout >= 0 ? 0 : timeout;
|
| 3058 | }
|
| 3059 |
|
| 3060 | static const struct file_operations amdgpu_driver_kms_fops = {
|
| 3061 | .owner = THIS_MODULE,
|
| 3062 | .open = drm_open,
|
| 3063 | .flush = amdgpu_flush,
|
| 3064 | .release = amdgpu_drm_release,
|
| 3065 | .unlocked_ioctl = amdgpu_drm_ioctl,
|
| 3066 | .mmap = drm_gem_mmap,
|
| 3067 | .poll = drm_poll,
|
| 3068 | .read = drm_read,
|
| 3069 | #ifdef CONFIG_COMPAT
|
| 3070 | .compat_ioctl = amdgpu_kms_compat_ioctl,
|
| 3071 | #endif
|
| 3072 | #ifdef CONFIG_PROC_FS
|
| 3073 | .show_fdinfo = drm_show_fdinfo,
|
| 3074 | #endif
|
| 3075 | .fop_flags = FOP_UNSIGNED_OFFSET,
|
| 3076 | };
|
| 3077 |
|
| 3078 | int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)
|
| 3079 | {
|
| 3080 | struct drm_file *file;
|
| 3081 |
|
| 3082 | if (!filp)
|
| 3083 | return -EINVAL;
|
| 3084 |
|
| 3085 | if (filp->f_op != &amdgpu_driver_kms_fops)
|
| 3086 | return -EINVAL;
|
| 3087 |
|
| 3088 | file = filp->private_data;
|
| 3089 | *fpriv = file->driver_priv;
|
| 3090 | return 0;
|
| 3091 | }
|
| 3092 |
|
| 3093 | const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
|
| 3094 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
| 3095 | DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
| 3096 | DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
| 3097 | DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
|
| 3098 | DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
| 3099 | DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
| 3100 |
|
| 3101 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
| 3102 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
| 3103 | DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
| 3104 | DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
| 3105 | DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
| 3106 | DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
| 3107 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
| 3108 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
| 3109 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
| 3110 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
| 3111 | DRM_IOCTL_DEF_DRV(AMDGPU_USERQ, amdgpu_userq_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
| 3112 | DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_SIGNAL, amdgpu_userq_signal_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
| 3113 | DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_WAIT, amdgpu_userq_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
| 3114 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_LIST_HANDLES, amdgpu_gem_list_handles_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
| 3115 | DRM_IOCTL_DEF_DRV(AMDGPU_PROC_OPTIONS, amdgpu_proc_options_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
| 3116 | };
|
| 3117 |
|
| 3118 | static const struct drm_driver amdgpu_kms_driver = {
|
| 3119 | .driver_features =
|
| 3120 | DRIVER_ATOMIC |
|
| 3121 | DRIVER_GEM |
|
| 3122 | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ |
|
| 3123 | DRIVER_SYNCOBJ_TIMELINE,
|
| 3124 | .open = amdgpu_driver_open_kms,
|
| 3125 | .postclose = amdgpu_driver_postclose_kms,
|
| 3126 | .ioctls = amdgpu_ioctls_kms,
|
| 3127 | .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),
|
| 3128 | .dumb_create = amdgpu_mode_dumb_create,
|
| 3129 | .dumb_map_offset = amdgpu_mode_dumb_mmap,
|
| 3130 | DRM_FBDEV_TTM_DRIVER_OPS,
|
| 3131 | .fops = &amdgpu_driver_kms_fops,
|
| 3132 | .release = &amdgpu_driver_release_kms,
|
| 3133 | #ifdef CONFIG_PROC_FS
|
| 3134 | .show_fdinfo = amdgpu_show_fdinfo,
|
| 3135 | #endif
|
| 3136 |
|
| 3137 | .gem_prime_import = amdgpu_gem_prime_import,
|
| 3138 |
|
| 3139 | .name = DRIVER_NAME,
|
| 3140 | .desc = DRIVER_DESC,
|
| 3141 | .major = KMS_DRIVER_MAJOR,
|
| 3142 | .minor = KMS_DRIVER_MINOR,
|
| 3143 | .patchlevel = KMS_DRIVER_PATCHLEVEL,
|
| 3144 | };
|
| 3145 |
|
| 3146 | const struct drm_driver amdgpu_partition_driver = {
|
| 3147 | .driver_features =
|
| 3148 | DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ |
|
| 3149 | DRIVER_SYNCOBJ_TIMELINE,
|
| 3150 | .open = amdgpu_driver_open_kms,
|
| 3151 | .postclose = amdgpu_driver_postclose_kms,
|
| 3152 | .ioctls = amdgpu_ioctls_kms,
|
| 3153 | .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),
|
| 3154 | .dumb_create = amdgpu_mode_dumb_create,
|
| 3155 | .dumb_map_offset = amdgpu_mode_dumb_mmap,
|
| 3156 | DRM_FBDEV_TTM_DRIVER_OPS,
|
| 3157 | .fops = &amdgpu_driver_kms_fops,
|
| 3158 | .release = &amdgpu_driver_release_kms,
|
| 3159 |
|
| 3160 | .gem_prime_import = amdgpu_gem_prime_import,
|
| 3161 |
|
| 3162 | .name = DRIVER_NAME,
|
| 3163 | .desc = DRIVER_DESC,
|
| 3164 | .major = KMS_DRIVER_MAJOR,
|
| 3165 | .minor = KMS_DRIVER_MINOR,
|
| 3166 | .patchlevel = KMS_DRIVER_PATCHLEVEL,
|
| 3167 | };
|
| 3168 |
|
| 3169 | static struct pci_error_handlers amdgpu_pci_err_handler = {
|
| 3170 | .error_detected = amdgpu_pci_error_detected,
|
| 3171 | .mmio_enabled = amdgpu_pci_mmio_enabled,
|
| 3172 | .slot_reset = amdgpu_pci_slot_reset,
|
| 3173 | .resume = amdgpu_pci_resume,
|
| 3174 | };
|
| 3175 |
|
| 3176 | static const struct attribute_group *amdgpu_sysfs_groups[] = {
|
| 3177 | &amdgpu_vram_mgr_attr_group,
|
| 3178 | &amdgpu_gtt_mgr_attr_group,
|
| 3179 | &amdgpu_flash_attr_group,
|
| 3180 | NULL,
|
| 3181 | };
|
| 3182 |
|
| 3183 | static struct pci_driver amdgpu_kms_pci_driver = {
|
| 3184 | .name = DRIVER_NAME,
|
| 3185 | .id_table = pciidlist,
|
| 3186 | .probe = amdgpu_pci_probe,
|
| 3187 | .remove = amdgpu_pci_remove,
|
| 3188 | .shutdown = amdgpu_pci_shutdown,
|
| 3189 | .driver.pm = pm_ptr(&amdgpu_pm_ops),
|
| 3190 | .err_handler = &amdgpu_pci_err_handler,
|
| 3191 | .dev_groups = amdgpu_sysfs_groups,
|
| 3192 | };
|
| 3193 |
|
| 3194 | static int __init amdgpu_init(void)
|
| 3195 | {
|
| 3196 | int r;
|
| 3197 |
|
| 3198 |
|
| 3199 | amdgpu_lockdep_init();
|
| 3200 |
|
| 3201 | r = amdgpu_sync_init();
|
| 3202 | if (r)
|
| 3203 | return r;
|
| 3204 |
|
| 3205 | amdgpu_register_atpx_handler();
|
| 3206 | amdgpu_acpi_detect();
|
| 3207 |
|
| 3208 |
|
| 3209 | r = amdgpu_amdkfd_init();
|
| 3210 | if (r && r != -ENOENT)
|
| 3211 | goto error_fini_sync;
|
| 3212 |
|
| 3213 | if (amdgpu_pp_feature_mask & PP_OVERDRIVE_MASK) {
|
| 3214 | add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
|
| 3215 | pr_crit("Overdrive is enabled, please disable it before "
|
| 3216 | "reporting any bugs unrelated to overdrive.\n");
|
| 3217 | }
|
| 3218 |
|
| 3219 |
|
| 3220 | return pci_register_driver(&amdgpu_kms_pci_driver);
|
| 3221 |
|
| 3222 | error_fini_sync:
|
| 3223 | amdgpu_sync_fini();
|
| 3224 | return r;
|
| 3225 | }
|
| 3226 |
|
| 3227 | static void __exit amdgpu_exit(void)
|
| 3228 | {
|
| 3229 | amdgpu_amdkfd_fini();
|
| 3230 | pci_unregister_driver(&amdgpu_kms_pci_driver);
|
| 3231 | amdgpu_unregister_atpx_handler();
|
| 3232 | amdgpu_acpi_release();
|
| 3233 | amdgpu_sync_fini();
|
| 3234 | mmu_notifier_synchronize();
|
| 3235 | amdgpu_xcp_drv_release();
|
| 3236 |
|
| 3237 | |
| 3238 | * Flush outstanding call_rcu() callbacks before the
|
| 3239 | * module text is freed. Otherwise a grace period elapsing after
|
| 3240 | * unload invokes a callback in already-freed module memory and
|
| 3241 | * faults in rcu_do_batch().
|
| 3242 |
|
| 3243 | rcu_barrier();
|
| 3244 | }
|
| 3245 |
|
| 3246 | module_init(amdgpu_init);
|
| 3247 | module_exit(amdgpu_exit);
|
| 3248 |
|
| 3249 | MODULE_AUTHOR(DRIVER_AUTHOR);
|
| 3250 | MODULE_DESCRIPTION(DRIVER_DESC);
|
| 3251 | MODULE_LICENSE("GPL and additional rights");
|