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| 2 | * Copyright 2021 Advanced Micro Devices, Inc.
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| 3 | *
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a
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| 5 | * copy of this software and associated documentation files (the "Software"),
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| 6 | * to deal in the Software without restriction, including without limitation
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the
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| 9 | * Software is furnished to do so, subject to the following conditions:
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| 10 | *
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| 11 | * The above copyright notice and this permission notice shall be included in
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| 12 | * all copies or substantial portions of the Software.
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| 13 | *
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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| 20 | * OTHER DEALINGS IN THE SOFTWARE.
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| 21 | *
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| 22 |
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| 23 |
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| 24 | #include "amdgpu_eeprom.h"
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| 25 | #include "amdgpu.h"
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| 26 |
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| 27 | |
| 28 |
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| 29 | #define EEPROM_PAGE_BITS 8
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| 30 | #define EEPROM_PAGE_SIZE (1U << EEPROM_PAGE_BITS)
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| 31 | #define EEPROM_PAGE_MASK (EEPROM_PAGE_SIZE - 1)
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| 32 |
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| 33 | #define EEPROM_OFFSET_SIZE 2
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| 34 |
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| 35 | |
| 36 | * be partitioned into 3, 8, 8 bits, for a total of 19.
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| 37 | * The upper 3 bits are sent as part of the 7-bit
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| 38 | * "Device Type Identifier"--an I2C concept, which for EEPROM devices
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| 39 | * is hard-coded as 1010b, indicating that it is an EEPROM
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| 40 | * device--this is the wire format, followed by the upper
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| 41 | * 3 bits of the 19-bit address, followed by the direction,
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| 42 | * followed by two bytes holding the rest of the 16-bits of
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| 43 | * the EEPROM memory address. The format on the wire for EEPROM
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| 44 | * devices is: 1010XYZD, A15:A8, A7:A0,
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| 45 | * Where D is the direction and sequenced out by the hardware.
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| 46 | * Bits XYZ are memory address bits 18, 17 and 16.
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| 47 | * These bits are compared to how pins 1-3 of the part are connected,
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| 48 | * depending on the size of the part, more on that later.
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| 49 | *
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| 50 | * Note that of this wire format, a client is in control
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| 51 | * of, and needs to specify only XYZ, A15:A8, A7:0, bits,
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| 52 | * which is exactly the EEPROM memory address, or offset,
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| 53 | * in order to address up to 8 EEPROM devices on the I2C bus.
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| 54 | *
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| 55 | * For instance, a 2-Mbit I2C EEPROM part, addresses all its bytes,
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| 56 | * using an 18-bit address, bit 17 to 0 and thus would use all but one bit of
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| 57 | * the 19 bits previously mentioned. The designer would then not connect
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| 58 | * pins 1 and 2, and pin 3 usually named "A_2" or "E2", would be connected to
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| 59 | * either Vcc or GND. This would allow for up to two 2-Mbit parts on
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| 60 | * the same bus, where one would be addressable with bit 18 as 1, and
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| 61 | * the other with bit 18 of the address as 0.
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| 62 | *
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| 63 | * For a 2-Mbit part, bit 18 is usually known as the "Chip Enable" or
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| 64 | * "Hardware Address Bit". This bit is compared to the load on pin 3
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| 65 | * of the device, described above, and if there is a match, then this
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| 66 | * device responds to the command. This way, you can connect two
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| 67 | * 2-Mbit EEPROM devices on the same bus, but see one contiguous
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| 68 | * memory from 0 to 7FFFFh, where address 0 to 3FFFF is in the device
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| 69 | * whose pin 3 is connected to GND, and address 40000 to 7FFFFh is in
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| 70 | * the 2nd device, whose pin 3 is connected to Vcc.
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| 71 | *
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| 72 | * This addressing you encode in the 32-bit "eeprom_addr" below,
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| 73 | * namely the 19-bits "XYZ,A15:A0", as a single 19-bit address. For
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| 74 | * instance, eeprom_addr = 0x6DA01, is 110_1101_1010_0000_0001, where
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| 75 | * XYZ=110b, and A15:A0=DA01h. The XYZ bits become part of the device
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| 76 | * address, and the rest of the address bits are sent as the memory
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| 77 | * address bytes.
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| 78 | *
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| 79 | * That is, for an I2C EEPROM driver everything is controlled by
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| 80 | * the "eeprom_addr".
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| 81 | *
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| 82 | * See also top of amdgpu_ras_eeprom.c.
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| 83 | *
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| 84 | * P.S. If you need to write, lock and read the Identification Page,
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| 85 | * (M24M02-DR device only, which we do not use), change the "7" to
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| 86 | * "0xF" in the macro below, and let the client set bit 20 to 1 in
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| 87 | * "eeprom_addr", and set A10 to 0 to write into it, and A10 and A1 to
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| 88 | * 1 to lock it permanently.
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| 89 |
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| 90 | #define MAKE_I2C_ADDR(_aa) ((0xA << 3) | (((_aa) >> 16) & 0xF))
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| 91 |
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| 92 | static int __amdgpu_eeprom_xfer(struct i2c_adapter *i2c_adap, u32 eeprom_addr,
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| 93 | u8 *eeprom_buf, u32 buf_size, bool read)
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| 94 | {
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| 95 | u8 eeprom_offset_buf[EEPROM_OFFSET_SIZE];
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| 96 | struct i2c_msg msgs[] = {
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| 97 | {
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| 98 | .flags = 0,
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| 99 | .len = EEPROM_OFFSET_SIZE,
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| 100 | .buf = eeprom_offset_buf,
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| 101 | },
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| 102 | {
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| 103 | .flags = read ? I2C_M_RD : 0,
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| 104 | },
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| 105 | };
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| 106 | const u8 *p = eeprom_buf;
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| 107 | int r;
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| 108 | u16 len;
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| 109 |
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| 110 | for (r = 0; buf_size > 0;
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| 111 | buf_size -= len, eeprom_addr += len, eeprom_buf += len) {
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| 112 | |
| 113 |
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| 114 | msgs[0].addr = MAKE_I2C_ADDR(eeprom_addr);
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| 115 | msgs[1].addr = msgs[0].addr;
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| 116 | msgs[0].buf[0] = (eeprom_addr >> 8) & 0xff;
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| 117 | msgs[0].buf[1] = eeprom_addr & 0xff;
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| 118 |
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| 119 | if (!read) {
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| 120 | |
| 121 | * crossing the device's page boundary, as per
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| 122 | * its spec. Partial page writes are allowed,
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| 123 | * starting at any location within the page,
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| 124 | * so long as the page boundary isn't crossed
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| 125 | * over (actually the page pointer rolls
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| 126 | * over).
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| 127 | *
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| 128 | * As per the AT24CM02 EEPROM spec, after
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| 129 | * writing into a page, the I2C driver should
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| 130 | * terminate the transfer, i.e. in
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| 131 | * "i2c_transfer()" below, with a STOP
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| 132 | * condition, so that the self-timed write
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| 133 | * cycle begins. This is implied for the
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| 134 | * "i2c_transfer()" abstraction.
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| 135 |
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| 136 | len = min(EEPROM_PAGE_SIZE - (eeprom_addr & EEPROM_PAGE_MASK),
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| 137 | buf_size);
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| 138 | } else {
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| 139 | |
| 140 | * on the number of bytes read from the EEPROM
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| 141 | * device--they are simply sequenced out.
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| 142 | * Keep in mind that i2c_msg.len is u16 type.
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| 143 |
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| 144 | len = min(U16_MAX, buf_size);
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| 145 | }
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| 146 | msgs[1].len = len;
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| 147 | msgs[1].buf = eeprom_buf;
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| 148 |
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| 149 | |
| 150 |
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| 151 | r = i2c_transfer(i2c_adap, msgs, ARRAY_SIZE(msgs));
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| 152 | if (r != ARRAY_SIZE(msgs))
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| 153 | break;
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| 154 |
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| 155 | if (!read) {
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| 156 | |
| 157 | * self-writing cycle, tWR (tW), is 10 ms.
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| 158 | *
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| 159 | * TODO: Use polling on ACK, aka Acknowledge
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| 160 | * Polling, to minimize waiting for the
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| 161 | * internal write cycle to complete, as it is
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| 162 | * usually smaller than tWR (tW).
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| 163 |
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| 164 | msleep(10);
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| 165 | }
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| 166 | }
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| 167 |
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| 168 | return r < 0 ? r : eeprom_buf - p;
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| 169 | }
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| 170 |
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| 171 | |
| 172 | * amdgpu_eeprom_xfer -- Read/write from/to an I2C EEPROM device
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| 173 | * @i2c_adap: pointer to the I2C adapter to use
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| 174 | * @eeprom_addr: EEPROM address from which to read/write
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| 175 | * @eeprom_buf: pointer to data buffer to read into/write from
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| 176 | * @buf_size: the size of @eeprom_buf
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| 177 | * @read: True if reading from the EEPROM, false if writing
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| 178 | *
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| 179 | * Returns the number of bytes read/written; -errno on error.
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| 180 |
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| 181 | static int amdgpu_eeprom_xfer(struct i2c_adapter *i2c_adap, u32 eeprom_addr,
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| 182 | u8 *eeprom_buf, u32 buf_size, bool read)
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| 183 | {
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| 184 | const struct i2c_adapter_quirks *quirks = i2c_adap->quirks;
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| 185 | u16 limit;
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| 186 | u16 ps;
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| 187 | int res = 0, r;
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| 188 |
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| 189 | if (!quirks)
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| 190 | limit = 0;
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| 191 | else if (read)
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| 192 | limit = quirks->max_read_len;
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| 193 | else
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| 194 | limit = quirks->max_write_len;
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| 195 |
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| 196 | if (limit == 0) {
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| 197 | return __amdgpu_eeprom_xfer(i2c_adap, eeprom_addr,
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| 198 | eeprom_buf, buf_size, read);
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| 199 | } else if (limit <= EEPROM_OFFSET_SIZE) {
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| 200 | dev_err_ratelimited(&i2c_adap->dev,
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| 201 | "maddr:0x%04X size:0x%02X:quirk max_%s_len must be > %d",
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| 202 | eeprom_addr, buf_size,
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| 203 | str_read_write(read), EEPROM_OFFSET_SIZE);
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| 204 | return -EINVAL;
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| 205 | }
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| 206 |
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| 207 | |
| 208 | * which would include the EEPROM_OFFSET_SIZE bytes.
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| 209 | * Account for them here.
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| 210 |
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| 211 | limit -= EEPROM_OFFSET_SIZE;
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| 212 | for ( ; buf_size > 0;
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| 213 | buf_size -= ps, eeprom_addr += ps, eeprom_buf += ps) {
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| 214 | ps = min(limit, buf_size);
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| 215 |
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| 216 | r = __amdgpu_eeprom_xfer(i2c_adap, eeprom_addr,
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| 217 | eeprom_buf, ps, read);
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| 218 | if (r < 0)
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| 219 | return r;
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| 220 | res += r;
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| 221 | }
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| 222 |
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| 223 | return res;
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| 224 | }
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| 225 |
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| 226 | int amdgpu_eeprom_read(struct i2c_adapter *i2c_adap,
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| 227 | u32 eeprom_addr, u8 *eeprom_buf,
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| 228 | u32 bytes)
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| 229 | {
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| 230 | return amdgpu_eeprom_xfer(i2c_adap, eeprom_addr, eeprom_buf, bytes,
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| 231 | true);
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| 232 | }
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| 233 |
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| 234 | int amdgpu_eeprom_write(struct i2c_adapter *i2c_adap,
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| 235 | u32 eeprom_addr, u8 *eeprom_buf,
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| 236 | u32 bytes)
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| 237 | {
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| 238 | return amdgpu_eeprom_xfer(i2c_adap, eeprom_addr, eeprom_buf, bytes,
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| 239 | false);
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| 240 | }
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