| 1 | |
| 2 | * Copyright 2018 Advanced Micro Devices, Inc.
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| 3 | *
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a
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| 5 | * copy of this software and associated documentation files (the "Software"),
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| 6 | * to deal in the Software without restriction, including without limitation
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the
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| 9 | * Software is furnished to do so, subject to the following conditions:
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| 10 | *
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| 11 | * The above copyright notice and this permission notice shall be included in
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| 12 | * all copies or substantial portions of the Software.
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| 13 | *
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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| 20 | * OTHER DEALINGS IN THE SOFTWARE.
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| 21 | *
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| 22 |
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| 23 | #ifndef __AMDGPU_GEM_H__
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| 24 | #define __AMDGPU_GEM_H__
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| 25 |
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| 26 | #include <drm/amdgpu_drm.h>
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| 27 | #include <drm/drm_gem.h>
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| 28 |
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| 29 | |
| 30 | * GEM.
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| 31 |
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| 32 |
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| 33 | #define AMDGPU_GEM_DOMAIN_MAX 0x3
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| 34 | #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, tbo.base)
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| 35 |
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| 36 | extern const struct drm_gem_object_funcs amdgpu_gem_object_funcs;
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| 37 |
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| 38 | unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
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| 39 |
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| 40 | |
| 41 | * GEM objects.
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| 42 |
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| 43 | void amdgpu_gem_force_release(struct amdgpu_device *adev);
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| 44 | int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
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| 45 | int alignment, u32 initial_domain,
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| 46 | u64 flags, enum ttm_bo_type type,
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| 47 | struct dma_resv *resv,
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| 48 | struct drm_gem_object **obj, int8_t xcp_id_plus1);
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| 49 | int amdgpu_mode_dumb_create(struct drm_file *file_priv,
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| 50 | struct drm_device *dev,
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| 51 | struct drm_mode_create_dumb *args);
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| 52 | int amdgpu_mode_dumb_mmap(struct drm_file *filp,
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| 53 | struct drm_device *dev,
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| 54 | uint32_t handle, uint64_t *offset_p);
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| 55 |
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| 56 | int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
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| 57 | struct drm_file *filp);
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| 58 | int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
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| 59 | struct drm_file *filp);
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| 60 | int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
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| 61 | struct drm_file *filp);
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| 62 | int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
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| 63 | struct drm_file *filp);
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| 64 | int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
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| 65 | struct drm_file *filp);
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| 66 | int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
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| 67 | struct drm_file *filp);
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| 68 | int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
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| 69 | struct drm_file *filp);
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| 70 | int amdgpu_gem_list_handles_ioctl(struct drm_device *dev, void *data,
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| 71 | struct drm_file *filp);
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| 72 |
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| 73 | int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
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| 74 | struct drm_file *filp);
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| 75 |
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| 76 | #define AMDGPU_GEM_CREATE_SETTABLE_MASK (AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | \
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| 77 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS | \
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| 78 | AMDGPU_GEM_CREATE_CPU_GTT_USWC | \
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| 79 | AMDGPU_GEM_CREATE_VRAM_CLEARED | \
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| 80 | AMDGPU_GEM_CREATE_VM_ALWAYS_VALID | \
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| 81 | AMDGPU_GEM_CREATE_EXPLICIT_SYNC | \
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| 82 | AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE | \
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| 83 | AMDGPU_GEM_CREATE_ENCRYPTED | \
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| 84 | AMDGPU_GEM_CREATE_GFX12_DCC | \
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| 85 | AMDGPU_GEM_CREATE_DISCARDABLE | \
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| 86 | AMDGPU_GEM_CREATE_COHERENT | \
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| 87 | AMDGPU_GEM_CREATE_UNCACHED | \
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| 88 | AMDGPU_GEM_CREATE_EXT_COHERENT)
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| 89 |
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| 90 | #endif
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