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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 * Christian König
28 */
29#include <linux/seq_file.h>
30#include <linux/slab.h>
31
32#include <drm/amdgpu_drm.h>
33
34#include "amdgpu.h"
35#include "atom.h"
36#include "amdgpu_trace.h"
37
38#define AMDGPU_IB_TEST_TIMEOUT msecs_to_jiffies(1000)
39#define AMDGPU_IB_TEST_GFX_XGMI_TIMEOUT msecs_to_jiffies(2000)
40
41/*
42 * IB
43 * IBs (Indirect Buffers) and areas of GPU accessible memory where
44 * commands are stored. You can put a pointer to the IB in the
45 * command ring and the hw will fetch the commands from the IB
46 * and execute them. Generally userspace acceleration drivers
47 * produce command buffers which are send to the kernel and
48 * put in IBs for execution by the requested ring.
49 */
50
51/**
52 * amdgpu_ib_get - request an IB (Indirect Buffer)
53 *
54 * @adev: amdgpu_device pointer
55 * @vm: amdgpu_vm pointer
56 * @size: requested IB size
57 * @pool_type: IB pool type (delayed, immediate, direct)
58 * @ib: IB object returned
59 *
60 * Request an IB (all asics). IBs are allocated using the
61 * suballocator.
62 * Returns 0 on success, error on failure.
63 */
64int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
65 unsigned int size, enum amdgpu_ib_pool_type pool_type,
66 struct amdgpu_ib *ib)
67{
68 int r;
69
70 if (size) {
71 r = amdgpu_sa_bo_new(&adev->ib_pools[pool_type],
72 &ib->sa_bo, size);
73 if (r) {
74 dev_err(adev->dev, "failed to get a new IB (%d)\n", r);
75 return r;
76 }
77
78 ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo);
79 /* flush the cache before commit the IB */
80 ib->flags = AMDGPU_IB_FLAG_EMIT_MEM_SYNC;
81
82 if (!vm)
83 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
84 }
85
86 return 0;
87}
88
89/**
90 * amdgpu_ib_free - free an IB (Indirect Buffer)
91 *
92 * @ib: IB object to free
93 * @f: the fence SA bo need wait on for the ib alloation
94 *
95 * Free an IB (all asics).
96 */
97void amdgpu_ib_free(struct amdgpu_ib *ib, struct dma_fence *f)
98{
99 amdgpu_sa_bo_free(&ib->sa_bo, f);
100}
101
102/**
103 * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring
104 *
105 * @ring: ring index the IB is associated with
106 * @num_ibs: number of IBs to schedule
107 * @ibs: IB objects to schedule
108 * @job: job to schedule
109 * @f: fence created during this submission
110 *
111 * Schedule an IB on the associated ring (all asics).
112 * Returns 0 on success, error on failure.
113 *
114 * On SI, there are two parallel engines fed from the primary ring,
115 * the CE (Constant Engine) and the DE (Drawing Engine). Since
116 * resource descriptors have moved to memory, the CE allows you to
117 * prime the caches while the DE is updating register state so that
118 * the resource descriptors will be already in cache when the draw is
119 * processed. To accomplish this, the userspace driver submits two
120 * IBs, one for the CE and one for the DE. If there is a CE IB (called
121 * a CONST_IB), it will be put on the ring prior to the DE IB. Prior
122 * to SI there was just a DE IB.
123 */
124int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,
125 struct amdgpu_ib *ibs, struct amdgpu_job *job,
126 struct dma_fence **f)
127{
128 struct amdgpu_device *adev = ring->adev;
129 struct amdgpu_ib *ib = &ibs[0];
130 struct dma_fence *tmp = NULL;
131 struct amdgpu_fence *af;
132 struct amdgpu_fence *vm_af;
133 bool need_ctx_switch;
134 bool emit_spm_needed = false;
135 bool emit_gds_needed = false;
136 struct amdgpu_vm *vm;
137 uint64_t fence_ctx;
138 uint32_t status = 0, alloc_size;
139 unsigned int fence_flags = 0;
140 bool secure, init_shadow;
141 u64 shadow_va, csa_va, gds_va;
142 int vmid = AMDGPU_JOB_GET_VMID(job);
143 bool need_pipe_sync = false;
144 unsigned int cond_exec;
145 unsigned int i;
146 int r = 0;
147
148 if (num_ibs == 0)
149 return -EINVAL;
150
151 /* ring tests don't use a job */
152 if (job) {
153 vm = job->vm;
154 fence_ctx = job->base.s_fence ?
155 job->base.s_fence->finished.context : 0;
156 shadow_va = job->shadow_va;
157 csa_va = job->csa_va;
158 gds_va = job->gds_va;
159 init_shadow = job->init_shadow;
160 af = job->hw_fence;
161 /* Save the context of the job for reset handling.
162 * The driver needs this so it can skip the ring
163 * contents for guilty contexts.
164 */
165 af->context = fence_ctx;
166 /* the vm fence is also part of the job's context */
167 job->hw_vm_fence->context = fence_ctx;
168 } else {
169 vm = NULL;
170 fence_ctx = 0;
171 shadow_va = 0;
172 csa_va = 0;
173 gds_va = 0;
174 init_shadow = false;
175 af = kzalloc_obj(*af, GFP_ATOMIC);
176 if (!af)
177 return -ENOMEM;
178 }
179
180 if (!ring->sched.ready) {
181 dev_err(adev->dev, "couldn't schedule ib on ring <%s>\n", ring->name);
182 r = -EINVAL;
183 goto free_fence;
184 }
185
186 if (vm && !job->vmid) {
187 dev_err(adev->dev, "VM IB without ID\n");
188 r = -EINVAL;
189 goto free_fence;
190 }
191
192 if ((ib->flags & AMDGPU_IB_FLAGS_SECURE) &&
193 (!ring->funcs->secure_submission_supported)) {
194 dev_err(adev->dev, "secure submissions not supported on ring <%s>\n", ring->name);
195 r = -EINVAL;
196 goto free_fence;
197 }
198
199 alloc_size = ring->funcs->emit_frame_size + num_ibs *
200 ring->funcs->emit_ib_size;
201
202 r = amdgpu_ring_alloc(ring, alloc_size);
203 if (r) {
204 dev_err(adev->dev, "scheduling IB failed (%d).\n", r);
205 goto free_fence;
206 }
207
208 need_ctx_switch = ring->current_ctx != fence_ctx;
209 if (ring->funcs->emit_pipeline_sync && job &&
210 ((tmp = amdgpu_sync_get_fence(&job->explicit_sync)) ||
211 need_ctx_switch || amdgpu_vm_need_pipeline_sync(ring, job))) {
212
213 need_pipe_sync = true;
214
215 if (tmp)
216 trace_amdgpu_ib_pipe_sync(job, tmp);
217
218 dma_fence_put(tmp);
219 }
220
221 if (job) {
222 vm_af = job->hw_vm_fence;
223 /* VM sequence */
224 vm_af->ib_wptr = ring->wptr;
225 amdgpu_vm_flush(ring, job, &need_pipe_sync, &emit_spm_needed,
226 &emit_gds_needed);
227 vm_af->ib_dw_size =
228 amdgpu_ring_get_dw_distance(ring, vm_af->ib_wptr, ring->wptr);
229 }
230
231 /* IB sequence */
232 af->ib_wptr = ring->wptr;
233 amdgpu_ring_ib_begin(ring);
234
235 if (ring->funcs->insert_start)
236 ring->funcs->insert_start(ring);
237
238 /* this may have been handled by amdgpu_vm_flush */
239 if (need_pipe_sync)
240 amdgpu_ring_emit_pipeline_sync(ring);
241
242 if (emit_spm_needed)
243 adev->gfx.rlc.funcs->update_spm_vmid(adev, ring->xcc_id, ring, job->vmid);
244
245 if (emit_gds_needed)
246 amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
247 job->gds_size, job->gws_base,
248 job->gws_size, job->oa_base,
249 job->oa_size);
250
251 if ((ib->flags & AMDGPU_IB_FLAG_EMIT_MEM_SYNC) && ring->funcs->emit_mem_sync)
252 ring->funcs->emit_mem_sync(ring);
253
254 if (ring->funcs->emit_wave_limit &&
255 ring->hw_prio == AMDGPU_GFX_PIPE_PRIO_HIGH)
256 ring->funcs->emit_wave_limit(ring, true);
257
258 if (ring->funcs->emit_gfx_shadow && adev->gfx.cp_gfx_shadow)
259 amdgpu_ring_emit_gfx_shadow(ring, shadow_va, csa_va, gds_va,
260 init_shadow, vmid);
261
262 if (ring->funcs->init_cond_exec)
263 cond_exec = amdgpu_ring_init_cond_exec(ring,
264 ring->cond_exe_gpu_addr);
265
266 /* Skip the IB for guilty contexts */
267 af->skip_ib_dw_start_offset =
268 amdgpu_ring_get_dw_distance(ring, af->ib_wptr, ring->wptr);
269 amdgpu_device_flush_hdp(adev, ring);
270
271 if (need_ctx_switch)
272 status |= AMDGPU_HAVE_CTX_SWITCH;
273
274 if (job && ring->funcs->emit_cntxcntl) {
275 status |= job->preamble_status;
276 status |= job->preemption_status;
277 amdgpu_ring_emit_cntxcntl(ring, status);
278 }
279
280 /* Setup initial TMZiness and send it off.
281 */
282 secure = false;
283 if (job && ring->funcs->emit_frame_cntl) {
284 secure = ib->flags & AMDGPU_IB_FLAGS_SECURE;
285 amdgpu_ring_emit_frame_cntl(ring, true, secure);
286 }
287
288 for (i = 0; i < num_ibs; ++i) {
289 ib = &ibs[i];
290
291 if (job && ring->funcs->emit_frame_cntl) {
292 if (secure != !!(ib->flags & AMDGPU_IB_FLAGS_SECURE)) {
293 amdgpu_ring_emit_frame_cntl(ring, false, secure);
294 secure = !secure;
295 amdgpu_ring_emit_frame_cntl(ring, true, secure);
296 }
297 }
298
299 amdgpu_ring_emit_ib(ring, job, ib, status);
300 status &= ~AMDGPU_HAVE_CTX_SWITCH;
301 }
302
303 if (job && ring->funcs->emit_frame_cntl)
304 amdgpu_ring_emit_frame_cntl(ring, false, secure);
305
306 amdgpu_device_invalidate_hdp(adev, ring);
307 /* Skip the IB for guilty contexts */
308 af->skip_ib_dw_end_offset =
309 amdgpu_ring_get_dw_distance(ring, af->ib_wptr, ring->wptr);
310
311 if (ib->flags & AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE)
312 fence_flags |= AMDGPU_FENCE_FLAG_TC_WB_ONLY;
313
314 /* wrap the last IB with fence */
315 if (job && job->uf_addr) {
316 amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence,
317 fence_flags | AMDGPU_FENCE_FLAG_64BIT);
318 }
319
320 if (ring->funcs->emit_gfx_shadow && ring->funcs->init_cond_exec &&
321 adev->gfx.cp_gfx_shadow) {
322 amdgpu_ring_emit_gfx_shadow(ring, 0, 0, 0, false, 0);
323 amdgpu_ring_init_cond_exec(ring, ring->cond_exe_gpu_addr);
324 }
325
326 amdgpu_fence_emit(ring, af, fence_flags);
327 *f = &af->base;
328 /* get a ref for the job */
329 if (job)
330 dma_fence_get(*f);
331
332 if (ring->funcs->insert_end)
333 ring->funcs->insert_end(ring);
334
335 amdgpu_ring_patch_cond_exec(ring, cond_exec);
336
337 ring->current_ctx = fence_ctx;
338 if (job && ring->funcs->emit_switch_buffer)
339 amdgpu_ring_emit_switch_buffer(ring);
340
341 if (ring->funcs->emit_wave_limit &&
342 ring->hw_prio == AMDGPU_GFX_PIPE_PRIO_HIGH)
343 ring->funcs->emit_wave_limit(ring, false);
344
345 amdgpu_ring_ib_end(ring);
346
347 af->ib_dw_size = amdgpu_ring_get_dw_distance(ring, af->ib_wptr, ring->wptr);
348
349 amdgpu_ring_commit(ring);
350
351 return 0;
352
353free_fence:
354 if (!job)
355 kfree(af);
356 return r;
357}
358
359/**
360 * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool
361 *
362 * @adev: amdgpu_device pointer
363 *
364 * Initialize the suballocator to manage a pool of memory
365 * for use as IBs (all asics).
366 * Returns 0 on success, error on failure.
367 */
368int amdgpu_ib_pool_init(struct amdgpu_device *adev)
369{
370 const int sizes[AMDGPU_IB_POOL_MAX] = {
371 [AMDGPU_IB_POOL_DELAYED] = SZ_1M,
372 [AMDGPU_IB_POOL_IMMEDIATE] = SZ_128K,
373 [AMDGPU_IB_POOL_DIRECT] = SZ_512K
374 };
375 const gfp_t gfp_flags[AMDGPU_IB_POOL_MAX] = {
376 /*
377 * For normal page table updates and recoverable retry faults
378 * (for SVM), further restricted by the VM eviction lock to not
379 * wait for memory reclaim.
380 */
381 [AMDGPU_IB_POOL_DELAYED] = GFP_KERNEL,
382 /*
383 * For redirecting unrecoverable retry faults to the dummy page
384 * or set the PRT bits. dma_fence submissions might depend on
385 * that so we need the emmergency reserves.
386 */
387 [AMDGPU_IB_POOL_IMMEDIATE] = GFP_ATOMIC,
388 /*
389 * For IB tests during GPU resets. Only very small and temporary
390 * allocation to allow dma_fences to signal.
391 */
392 [AMDGPU_IB_POOL_DIRECT] = GFP_ATOMIC
393 };
394 int r, i;
395
396 if (adev->ib_pool_ready)
397 return 0;
398
399 for (i = 0; i < AMDGPU_IB_POOL_MAX; i++) {
400 r = amdgpu_sa_bo_manager_init(adev, &adev->ib_pools[i],
401 sizes[i], gfp_flags[i]);
402 if (r)
403 goto error;
404 }
405 adev->ib_pool_ready = true;
406
407 return 0;
408
409error:
410 while (i--)
411 amdgpu_sa_bo_manager_fini(adev, &adev->ib_pools[i]);
412 return r;
413}
414
415/**
416 * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool
417 *
418 * @adev: amdgpu_device pointer
419 *
420 * Tear down the suballocator managing the pool of memory
421 * for use as IBs (all asics).
422 */
423void amdgpu_ib_pool_fini(struct amdgpu_device *adev)
424{
425 int i;
426
427 if (!adev->ib_pool_ready)
428 return;
429
430 for (i = 0; i < AMDGPU_IB_POOL_MAX; i++)
431 amdgpu_sa_bo_manager_fini(adev, &adev->ib_pools[i]);
432 adev->ib_pool_ready = false;
433}
434
435/**
436 * amdgpu_ib_pool_gfp_flags - Returns the gfp flags to use for each pool
437 * @adev: amdgpu device pointer
438 * @type: the IB pool type
439 */
440gfp_t amdgpu_ib_pool_gfp_flags(struct amdgpu_device *adev,
441 enum amdgpu_ib_pool_type type)
442{
443 return adev->ib_pools[type].gfp_flags;
444}
445
446/**
447 * amdgpu_ib_ring_tests - test IBs on the rings
448 *
449 * @adev: amdgpu_device pointer
450 *
451 * Test an IB (Indirect Buffer) on each ring.
452 * If the test fails, disable the ring.
453 * Returns 0 on success, error if the primary GFX ring
454 * IB test fails.
455 */
456int amdgpu_ib_ring_tests(struct amdgpu_device *adev)
457{
458 long tmo_gfx, tmo_mm;
459 int r, ret = 0;
460 unsigned int i;
461
462 tmo_mm = tmo_gfx = AMDGPU_IB_TEST_TIMEOUT;
463 if (amdgpu_sriov_vf(adev)) {
464 /* for MM engines in hypervisor side they are not scheduled together
465 * with CP and SDMA engines, so even in exclusive mode MM engine could
466 * still running on other VF thus the IB TEST TIMEOUT for MM engines
467 * under SR-IOV should be set to a long time. 8 sec should be enough
468 * for the MM comes back to this VF.
469 */
470 tmo_mm = 8 * AMDGPU_IB_TEST_TIMEOUT;
471 }
472
473 if (amdgpu_sriov_runtime(adev)) {
474 /* for CP & SDMA engines since they are scheduled together so
475 * need to make the timeout width enough to cover the time
476 * cost waiting for it coming back under RUNTIME only
477 */
478 tmo_gfx = 8 * AMDGPU_IB_TEST_TIMEOUT;
479 } else if (adev->gmc.xgmi.hive_id) {
480 tmo_gfx = AMDGPU_IB_TEST_GFX_XGMI_TIMEOUT;
481 }
482
483 for (i = 0; i < adev->num_rings; ++i) {
484 struct amdgpu_ring *ring = adev->rings[i];
485 long tmo;
486
487 /* KIQ rings don't have an IB test because we never submit IBs
488 * to them and they have no interrupt support.
489 */
490 if (!ring->sched.ready || !ring->funcs->test_ib)
491 continue;
492
493 if (adev->enable_mes &&
494 ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
495 continue;
496
497 /* MM engine need more time */
498 if (ring->funcs->type == AMDGPU_RING_TYPE_UVD ||
499 ring->funcs->type == AMDGPU_RING_TYPE_VCE ||
500 ring->funcs->type == AMDGPU_RING_TYPE_UVD_ENC ||
501 ring->funcs->type == AMDGPU_RING_TYPE_VCN_DEC ||
502 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC ||
503 ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG)
504 tmo = tmo_mm;
505 else
506 tmo = tmo_gfx;
507
508 r = amdgpu_ring_test_ib(ring, tmo);
509 if (!r) {
510 DRM_DEV_DEBUG(adev->dev, "ib test on %s succeeded\n",
511 ring->name);
512 continue;
513 }
514
515 ring->sched.ready = false;
516 DRM_DEV_ERROR(adev->dev, "IB test failed on %s (%d).\n",
517 ring->name, r);
518
519 if (ring == &adev->gfx.gfx_ring[0]) {
520 /* oh, oh, that's really bad */
521 adev->accel_working = false;
522 return r;
523
524 } else {
525 ret = r;
526 }
527 }
528 return ret;
529}
530
531/*
532 * Debugfs info
533 */
534#if defined(CONFIG_DEBUG_FS)
535
536static int amdgpu_debugfs_sa_info_show(struct seq_file *m, void *unused)
537{
538 struct amdgpu_device *adev = m->private;
539
540 seq_puts(m, "--------------------- DELAYED ---------------------\n");
541 amdgpu_sa_bo_dump_debug_info(&adev->ib_pools[AMDGPU_IB_POOL_DELAYED],
542 m);
543 seq_puts(m, "-------------------- IMMEDIATE --------------------\n");
544 amdgpu_sa_bo_dump_debug_info(&adev->ib_pools[AMDGPU_IB_POOL_IMMEDIATE],
545 m);
546 seq_puts(m, "--------------------- DIRECT ----------------------\n");
547 amdgpu_sa_bo_dump_debug_info(&adev->ib_pools[AMDGPU_IB_POOL_DIRECT], m);
548
549 return 0;
550}
551
552DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_sa_info);
553
554#endif
555
556void amdgpu_debugfs_sa_init(struct amdgpu_device *adev)
557{
558#if defined(CONFIG_DEBUG_FS)
559 struct drm_minor *minor = adev_to_drm(adev)->primary;
560 struct dentry *root = minor->debugfs_root;
561
562 debugfs_create_file("amdgpu_sa_info", 0444, root, adev,
563 &amdgpu_debugfs_sa_info_fops);
564
565#endif
566}