| 1 | |
| 2 | * Copyright 2021 Advanced Micro Devices, Inc.
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| 3 | *
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a
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| 5 | * copy of this software and associated documentation files (the "Software"),
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| 6 | * to deal in the Software without restriction, including without limitation
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the
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| 9 | * Software is furnished to do so, subject to the following conditions:
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| 10 | *
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| 11 | * The above copyright notice and this permission notice shall be included in
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| 12 | * all copies or substantial portions of the Software.
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| 13 | *
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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| 20 | * OTHER DEALINGS IN THE SOFTWARE.
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| 21 | *
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| 22 |
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| 23 |
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| 24 | #ifndef __AMDGPU_IMU_H__
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| 25 | #define __AMDGPU_IMU_H__
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| 26 |
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| 27 | enum imu_work_mode {
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| 28 | DEBUG_MODE,
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| 29 | MISSION_MODE
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| 30 | };
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| 31 |
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| 32 | struct amdgpu_imu_funcs {
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| 33 | int (*init_microcode)(struct amdgpu_device *adev);
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| 34 | int (*load_microcode)(struct amdgpu_device *adev);
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| 35 | void (*setup_imu)(struct amdgpu_device *adev);
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| 36 | int (*start_imu)(struct amdgpu_device *adev);
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| 37 | void (*program_rlc_ram)(struct amdgpu_device *adev);
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| 38 | int (*wait_for_reset_status)(struct amdgpu_device *adev);
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| 39 | int (*switch_compute_partition)(struct amdgpu_device *adev,
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| 40 | int num_xccs_per_xcp,
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| 41 | int compute_partition_mode);
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| 42 | };
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| 43 |
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| 44 | struct imu_rlc_ram_golden {
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| 45 | u32 hwip;
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| 46 | u32 instance;
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| 47 | u32 segment;
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| 48 | u32 reg;
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| 49 | u32 data;
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| 50 | u32 addr_mask;
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| 51 | };
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| 52 |
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| 53 | #define IMU_RLC_RAM_GOLDEN_VALUE(ip, inst, reg, data, addr_mask) \
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| 54 | { ip##_HWIP, inst, reg##_BASE_IDX, reg, data, addr_mask }
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| 55 |
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| 56 | struct amdgpu_imu {
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| 57 | const struct amdgpu_imu_funcs *funcs;
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| 58 | enum imu_work_mode mode;
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| 59 | };
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| 60 |
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| 61 | #endif
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