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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __AMDGPU_IRQ_H__
25#define __AMDGPU_IRQ_H__
26
27#include <linux/irqdomain.h>
28#include "soc15_ih_clientid.h"
29#include "soc_v1_0_ih_clientid.h"
30#include "amdgpu_ih.h"
31
32#define AMDGPU_MAX_IRQ_SRC_ID 0x100
33#define AMDGPU_MAX_IRQ_CLIENT_ID 0x100
34
35#define AMDGPU_IRQ_CLIENTID_LEGACY 0
36#define AMDGPU_IRQ_CLIENTID_MAX SOC15_IH_CLIENTID_MAX
37
38#define AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW 4
39
40struct amdgpu_device;
41
42enum amdgpu_interrupt_state {
43 AMDGPU_IRQ_STATE_DISABLE,
44 AMDGPU_IRQ_STATE_ENABLE,
45};
46
47struct amdgpu_iv_entry {
48 struct amdgpu_ih_ring *ih;
49 unsigned client_id;
50 unsigned src_id;
51 unsigned ring_id;
52 unsigned vmid;
53 unsigned vmid_src;
54 uint64_t timestamp;
55 unsigned timestamp_src;
56 unsigned pasid;
57 unsigned node_id;
58 unsigned src_data[AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW];
59 const uint32_t *iv_entry;
60};
61
62struct amdgpu_irq_src {
63 unsigned num_types;
64 atomic_t *enabled_types;
65 const struct amdgpu_irq_src_funcs *funcs;
66};
67
68struct amdgpu_irq_client {
69 struct amdgpu_irq_src **sources;
70};
71
72/* provided by interrupt generating IP blocks */
73struct amdgpu_irq_src_funcs {
74 int (*set)(struct amdgpu_device *adev, struct amdgpu_irq_src *source,
75 unsigned type, enum amdgpu_interrupt_state state);
76
77 int (*process)(struct amdgpu_device *adev,
78 struct amdgpu_irq_src *source,
79 struct amdgpu_iv_entry *entry);
80};
81
82struct amdgpu_irq {
83 bool installed;
84 unsigned int irq;
85 spinlock_t lock;
86 /* interrupt sources */
87 struct amdgpu_irq_client client[AMDGPU_IRQ_CLIENTID_MAX];
88
89 /* status, etc. */
90 bool msi_enabled; /* msi enabled */
91
92 /* interrupt rings */
93 struct amdgpu_ih_ring ih, ih1, ih2, ih_soft;
94 const struct amdgpu_ih_funcs *ih_funcs;
95 struct work_struct ih1_work, ih2_work, ih_soft_work;
96 struct amdgpu_irq_src self_irq;
97
98 /* gen irq stuff */
99 struct irq_domain *domain; /* GPU irq controller domain */
100 unsigned virq[AMDGPU_MAX_IRQ_SRC_ID];
101 uint32_t srbm_soft_reset;
102 u32 retry_cam_doorbell_index;
103 bool retry_cam_enabled;
104};
105
106enum interrupt_node_id_per_aid {
107 AID0_NODEID = 0,
108 XCD0_NODEID = 1,
109 XCD1_NODEID = 2,
110 AID1_NODEID = 4,
111 XCD2_NODEID = 5,
112 XCD3_NODEID = 6,
113 AID2_NODEID = 8,
114 XCD4_NODEID = 9,
115 XCD5_NODEID = 10,
116 AID3_NODEID = 12,
117 XCD6_NODEID = 13,
118 XCD7_NODEID = 14,
119 NODEID_MAX,
120};
121
122extern const int node_id_to_phys_map[NODEID_MAX];
123
124void amdgpu_irq_disable_all(struct amdgpu_device *adev);
125
126int amdgpu_irq_init(struct amdgpu_device *adev);
127void amdgpu_irq_fini_sw(struct amdgpu_device *adev);
128void amdgpu_irq_fini_hw(struct amdgpu_device *adev);
129int amdgpu_irq_add_id(struct amdgpu_device *adev,
130 unsigned client_id, unsigned src_id,
131 struct amdgpu_irq_src *source);
132void amdgpu_irq_dispatch(struct amdgpu_device *adev,
133 struct amdgpu_ih_ring *ih);
134void amdgpu_irq_delegate(struct amdgpu_device *adev,
135 struct amdgpu_iv_entry *entry,
136 unsigned int num_dw);
137int amdgpu_irq_update(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
138 unsigned type);
139int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
140 unsigned type);
141int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
142 unsigned type);
143bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
144 unsigned type);
145void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev);
146
147int amdgpu_irq_add_domain(struct amdgpu_device *adev);
148void amdgpu_irq_remove_domain(struct amdgpu_device *adev);
149unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id);
150void amdgpu_restore_msix(struct amdgpu_device *adev);
151
152#endif