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1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef __AMDGPU_JOB_H__
24#define __AMDGPU_JOB_H__
25
26#include <drm/gpu_scheduler.h>
27#include "amdgpu_sync.h"
28#include "amdgpu_ring.h"
29
30/* bit set means command submit involves a preamble IB */
31#define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0)
32/* bit set means preamble IB is first presented in belonging context */
33#define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1)
34/* bit set means context switch occured */
35#define AMDGPU_HAVE_CTX_SWITCH (1 << 2)
36/* bit set means IB is preempted */
37#define AMDGPU_IB_PREEMPTED (1 << 3)
38
39#define to_amdgpu_job(sched_job) \
40 container_of((sched_job), struct amdgpu_job, base)
41
42#define AMDGPU_JOB_GET_VMID(job) ((job) ? (job)->vmid : 0)
43
44struct amdgpu_fence;
45enum amdgpu_ib_pool_type;
46
47/* Internal kernel job ids. (decreasing values, starting from U64_MAX). */
48#define AMDGPU_KERNEL_JOB_ID_VM_UPDATE (18446744073709551615ULL)
49#define AMDGPU_KERNEL_JOB_ID_VM_UPDATE_PDES (18446744073709551614ULL)
50#define AMDGPU_KERNEL_JOB_ID_VM_UPDATE_RANGE (18446744073709551613ULL)
51#define AMDGPU_KERNEL_JOB_ID_VM_PT_CLEAR (18446744073709551612ULL)
52#define AMDGPU_KERNEL_JOB_ID_TTM_MAP_BUFFER (18446744073709551611ULL)
53#define AMDGPU_KERNEL_JOB_ID_TTM_ACCESS_MEMORY_SDMA (18446744073709551610ULL)
54#define AMDGPU_KERNEL_JOB_ID_TTM_COPY_BUFFER (18446744073709551609ULL)
55#define AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE (18446744073709551608ULL)
56#define AMDGPU_KERNEL_JOB_ID_MOVE_BLIT (18446744073709551607ULL)
57#define AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER (18446744073709551606ULL)
58#define AMDGPU_KERNEL_JOB_ID_CLEANER_SHADER (18446744073709551605ULL)
59#define AMDGPU_KERNEL_JOB_ID_FLUSH_GPU_TLB (18446744073709551604ULL)
60#define AMDGPU_KERNEL_JOB_ID_KFD_GART_MAP (18446744073709551603ULL)
61#define AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST (18446744073709551602ULL)
62#define AMDGPU_KERNEL_JOB_ID_GFX_RING_TEST (18446744073709551601ULL)
63#define AMDGPU_KERNEL_JOB_ID_SDMA_RING_TEST (18446744073709551600ULL)
64#define AMDGPU_KERNEL_JOB_ID_VPE_RING_TEST (18446744073709551599ULL)
65#define AMDGPU_KERNEL_JOB_ID_RUN_SHADER (18446744073709551598ULL)
66
67struct amdgpu_job {
68 struct drm_sched_job base;
69 struct amdgpu_vm *vm;
70 struct amdgpu_sync explicit_sync;
71 struct amdgpu_fence *hw_fence;
72 struct amdgpu_fence *hw_vm_fence;
73 struct dma_fence *gang_submit;
74 uint32_t preamble_status;
75 uint32_t preemption_status;
76 bool vm_needs_flush;
77 bool gds_switch_needed;
78 bool spm_update_needed;
79 uint64_t vm_pd_addr;
80 unsigned vmid;
81 unsigned pasid;
82 uint32_t gds_base, gds_size;
83 uint32_t gws_base, gws_size;
84 uint32_t oa_base, oa_size;
85 uint64_t generation;
86
87 /* user fence handling */
88 uint64_t uf_addr;
89 uint64_t uf_sequence;
90
91 /* virtual addresses for shadow/GDS/CSA */
92 uint64_t shadow_va;
93 uint64_t csa_va;
94 uint64_t gds_va;
95 bool init_shadow;
96
97 /* job_run_counter >= 1 means a resubmit job */
98 uint32_t job_run_counter;
99
100 /* enforce isolation */
101 bool enforce_isolation;
102 bool run_cleaner_shader;
103
104 uint32_t num_ibs;
105 struct amdgpu_ib ibs[];
106};
107
108static inline struct amdgpu_ring *amdgpu_job_ring(struct amdgpu_job *job)
109{
110 return to_amdgpu_ring(job->base.entity->rq->sched);
111}
112
113int amdgpu_job_alloc(struct amdgpu_device *adev, struct amdgpu_vm *vm,
114 struct drm_sched_entity *entity, void *owner,
115 unsigned int num_ibs, u64 drm_client_id,
116 gfp_t gfp_flags, struct amdgpu_job **job);
117int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev,
118 struct drm_sched_entity *entity, void *owner,
119 size_t size, enum amdgpu_ib_pool_type pool_type,
120 u64 k_job_id,
121 struct amdgpu_job **job);
122void amdgpu_job_set_resources(struct amdgpu_job *job, struct amdgpu_bo *gds,
123 struct amdgpu_bo *gws, struct amdgpu_bo *oa);
124void amdgpu_job_free_resources(struct amdgpu_job *job);
125void amdgpu_job_set_gang_leader(struct amdgpu_job *job,
126 struct amdgpu_job *leader);
127void amdgpu_job_free(struct amdgpu_job *job);
128struct dma_fence *amdgpu_job_submit(struct amdgpu_job *job);
129int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring,
130 struct dma_fence **fence);
131
132void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched);
133
134#endif