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1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26
27#include "amdgpu.h"
28#include "amdgpu_jpeg.h"
29#include "amdgpu_pm.h"
30#include "soc15d.h"
31#include "soc15_common.h"
32
33#define JPEG_IDLE_TIMEOUT msecs_to_jiffies(1000)
34
35static void amdgpu_jpeg_idle_work_handler(struct work_struct *work);
36static void amdgpu_jpeg_reg_dump_fini(struct amdgpu_device *adev);
37
38int amdgpu_jpeg_sw_init(struct amdgpu_device *adev)
39{
40 int i, r;
41
42 INIT_DELAYED_WORK(&adev->jpeg.idle_work, amdgpu_jpeg_idle_work_handler);
43 mutex_init(&adev->jpeg.jpeg_pg_lock);
44 atomic_set(&adev->jpeg.total_submission_cnt, 0);
45
46 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
47 (adev->pg_flags & AMD_PG_SUPPORT_JPEG_DPG))
48 adev->jpeg.indirect_sram = true;
49
50 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
51 if (adev->jpeg.harvest_config & (1U << i))
52 continue;
53
54 if (adev->jpeg.indirect_sram) {
55 r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE,
56 AMDGPU_GEM_DOMAIN_VRAM |
57 AMDGPU_GEM_DOMAIN_GTT,
58 &adev->jpeg.inst[i].dpg_sram_bo,
59 &adev->jpeg.inst[i].dpg_sram_gpu_addr,
60 &adev->jpeg.inst[i].dpg_sram_cpu_addr);
61 if (r) {
62 dev_err(adev->dev,
63 "JPEG %d (%d) failed to allocate DPG bo\n", i, r);
64 return r;
65 }
66 }
67 }
68
69 return 0;
70}
71
72int amdgpu_jpeg_sw_fini(struct amdgpu_device *adev)
73{
74 int i, j;
75
76 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
77 if (adev->jpeg.harvest_config & (1U << i))
78 continue;
79
80 amdgpu_bo_free_kernel(
81 &adev->jpeg.inst[i].dpg_sram_bo,
82 &adev->jpeg.inst[i].dpg_sram_gpu_addr,
83 (void **)&adev->jpeg.inst[i].dpg_sram_cpu_addr);
84
85 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j)
86 amdgpu_ring_fini(&adev->jpeg.inst[i].ring_dec[j]);
87 }
88
89 if (adev->jpeg.reg_list)
90 amdgpu_jpeg_reg_dump_fini(adev);
91
92 mutex_destroy(&adev->jpeg.jpeg_pg_lock);
93
94 return 0;
95}
96
97int amdgpu_jpeg_suspend(struct amdgpu_device *adev)
98{
99 cancel_delayed_work_sync(&adev->jpeg.idle_work);
100
101 return 0;
102}
103
104int amdgpu_jpeg_resume(struct amdgpu_device *adev)
105{
106 return 0;
107}
108
109static void amdgpu_jpeg_idle_work_handler(struct work_struct *work)
110{
111 struct amdgpu_device *adev =
112 container_of(work, struct amdgpu_device, jpeg.idle_work.work);
113 unsigned int fences = 0;
114 unsigned int i, j;
115
116 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
117 if (adev->jpeg.harvest_config & (1U << i))
118 continue;
119
120 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j)
121 fences += amdgpu_fence_count_emitted(&adev->jpeg.inst[i].ring_dec[j]);
122 }
123
124 if (!fences && !atomic_read(&adev->jpeg.total_submission_cnt)) {
125 mutex_lock(&adev->jpeg.jpeg_pg_lock);
126 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG,
127 AMD_PG_STATE_GATE);
128 mutex_unlock(&adev->jpeg.jpeg_pg_lock);
129 } else
130 schedule_delayed_work(&adev->jpeg.idle_work, JPEG_IDLE_TIMEOUT);
131}
132
133void amdgpu_jpeg_ring_begin_use(struct amdgpu_ring *ring)
134{
135 struct amdgpu_device *adev = ring->adev;
136
137 if (!atomic_fetch_inc(&adev->jpeg.total_submission_cnt))
138 cancel_delayed_work_sync(&adev->jpeg.idle_work);
139
140 mutex_lock(&adev->jpeg.jpeg_pg_lock);
141 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG,
142 AMD_PG_STATE_UNGATE);
143 mutex_unlock(&adev->jpeg.jpeg_pg_lock);
144}
145
146void amdgpu_jpeg_ring_end_use(struct amdgpu_ring *ring)
147{
148 if (atomic_dec_and_test(&ring->adev->jpeg.total_submission_cnt))
149 schedule_delayed_work(&ring->adev->jpeg.idle_work,
150 JPEG_IDLE_TIMEOUT);
151}
152
153int amdgpu_jpeg_dec_ring_test_ring(struct amdgpu_ring *ring)
154{
155 struct amdgpu_device *adev = ring->adev;
156 uint32_t tmp = 0;
157 unsigned i;
158 int r;
159
160 /* JPEG in SRIOV does not support direct register read/write */
161 if (amdgpu_sriov_vf(adev))
162 return 0;
163
164 r = amdgpu_ring_alloc(ring, 3);
165 if (r)
166 return r;
167
168 WREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe], 0xCAFEDEAD);
169 /* Add a read register to make sure the write register is executed. */
170 RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);
171
172 amdgpu_ring_write(ring, PACKET0(adev->jpeg.internal.jpeg_pitch[ring->pipe], 0));
173 amdgpu_ring_write(ring, 0xABADCAFE);
174 amdgpu_ring_commit(ring);
175
176 for (i = 0; i < adev->usec_timeout; i++) {
177 tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);
178 if (tmp == 0xABADCAFE)
179 break;
180 udelay(1);
181 }
182
183 if (i >= adev->usec_timeout)
184 r = -ETIMEDOUT;
185
186 return r;
187}
188
189static int amdgpu_jpeg_dec_set_reg(struct amdgpu_ring *ring, uint32_t handle,
190 struct dma_fence **fence)
191{
192 struct amdgpu_device *adev = ring->adev;
193 struct amdgpu_job *job;
194 struct amdgpu_ib *ib;
195 struct dma_fence *f = NULL;
196 const unsigned ib_size_dw = 16;
197 int i, r;
198
199 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4,
200 AMDGPU_IB_POOL_DIRECT,
201 AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST,
202 &job);
203 if (r)
204 return r;
205
206 ib = &job->ibs[0];
207
208 ib->ptr[0] = PACKETJ(adev->jpeg.internal.jpeg_pitch[ring->pipe], 0, 0, PACKETJ_TYPE0);
209 ib->ptr[1] = 0xDEADBEEF;
210 for (i = 2; i < 16; i += 2) {
211 ib->ptr[i] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
212 ib->ptr[i+1] = 0;
213 }
214 ib->length_dw = 16;
215
216 r = amdgpu_job_submit_direct(job, ring, &f);
217 if (r)
218 goto err;
219
220 if (fence)
221 *fence = dma_fence_get(f);
222 dma_fence_put(f);
223
224 return 0;
225
226err:
227 amdgpu_job_free(job);
228 return r;
229}
230
231int amdgpu_jpeg_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
232{
233 struct amdgpu_device *adev = ring->adev;
234 uint32_t tmp = 0;
235 unsigned i;
236 struct dma_fence *fence = NULL;
237 long r = 0;
238
239 r = amdgpu_jpeg_dec_set_reg(ring, 1, &fence);
240 if (r)
241 goto error;
242
243 r = dma_fence_wait_timeout(fence, false, timeout);
244 if (r == 0) {
245 r = -ETIMEDOUT;
246 goto error;
247 } else if (r < 0) {
248 goto error;
249 } else {
250 r = 0;
251 }
252
253 if (!amdgpu_sriov_vf(adev)) {
254 for (i = 0; i < adev->usec_timeout; i++) {
255 tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);
256 if (tmp == 0xDEADBEEF)
257 break;
258 udelay(1);
259 if (amdgpu_emu_mode == 1)
260 udelay(10);
261 }
262
263 if (i >= adev->usec_timeout)
264 r = -ETIMEDOUT;
265 }
266
267 dma_fence_put(fence);
268error:
269 return r;
270}
271
272int amdgpu_jpeg_process_poison_irq(struct amdgpu_device *adev,
273 struct amdgpu_irq_src *source,
274 struct amdgpu_iv_entry *entry)
275{
276 struct ras_common_if *ras_if = adev->jpeg.ras_if;
277 struct ras_dispatch_if ih_data = {
278 .entry = entry,
279 };
280
281 if (!ras_if)
282 return 0;
283
284 ih_data.head = *ras_if;
285 amdgpu_ras_interrupt_dispatch(adev, &ih_data);
286
287 return 0;
288}
289
290int amdgpu_jpeg_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
291{
292 int r, i;
293
294 r = amdgpu_ras_block_late_init(adev, ras_block);
295 if (r)
296 return r;
297
298 if (amdgpu_ras_is_supported(adev, ras_block->block)) {
299 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
300 if (adev->jpeg.harvest_config & (1 << i) ||
301 !adev->jpeg.inst[i].ras_poison_irq.funcs)
302 continue;
303
304 r = amdgpu_irq_get(adev, &adev->jpeg.inst[i].ras_poison_irq, 0);
305 if (r)
306 goto late_fini;
307 }
308 }
309 return 0;
310
311late_fini:
312 amdgpu_ras_block_late_fini(adev, ras_block);
313 return r;
314}
315
316int amdgpu_jpeg_ras_sw_init(struct amdgpu_device *adev)
317{
318 int err;
319 struct amdgpu_jpeg_ras *ras;
320
321 if (!adev->jpeg.ras)
322 return 0;
323
324 ras = adev->jpeg.ras;
325 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
326 if (err) {
327 dev_err(adev->dev, "Failed to register jpeg ras block!\n");
328 return err;
329 }
330
331 strcpy(ras->ras_block.ras_comm.name, "jpeg");
332 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__JPEG;
333 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON;
334 adev->jpeg.ras_if = &ras->ras_block.ras_comm;
335
336 if (!ras->ras_block.ras_late_init)
337 ras->ras_block.ras_late_init = amdgpu_jpeg_ras_late_init;
338
339 return 0;
340}
341
342int amdgpu_jpeg_psp_update_sram(struct amdgpu_device *adev, int inst_idx,
343 enum AMDGPU_UCODE_ID ucode_id)
344{
345 struct amdgpu_firmware_info ucode = {
346 .ucode_id = AMDGPU_UCODE_ID_JPEG_RAM,
347 .mc_addr = adev->jpeg.inst[inst_idx].dpg_sram_gpu_addr,
348 .ucode_size = ((uintptr_t)adev->jpeg.inst[inst_idx].dpg_sram_curr_addr -
349 (uintptr_t)adev->jpeg.inst[inst_idx].dpg_sram_cpu_addr),
350 };
351
352 return psp_execute_ip_fw_load(&adev->psp, &ucode);
353}
354
355/*
356 * debugfs for to enable/disable jpeg job submission to specific core.
357 */
358#if defined(CONFIG_DEBUG_FS)
359static int amdgpu_debugfs_jpeg_sched_mask_set(void *data, u64 val)
360{
361 struct amdgpu_device *adev = (struct amdgpu_device *)data;
362 u32 i, j;
363 u64 mask = 0;
364 struct amdgpu_ring *ring;
365
366 if (!adev)
367 return -ENODEV;
368
369 mask = (1ULL << (adev->jpeg.num_jpeg_inst * adev->jpeg.num_jpeg_rings)) - 1;
370 if ((val & mask) == 0)
371 return -EINVAL;
372
373 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
374 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
375 ring = &adev->jpeg.inst[i].ring_dec[j];
376 if (val & (BIT_ULL((i * adev->jpeg.num_jpeg_rings) + j)))
377 ring->sched.ready = true;
378 else
379 ring->sched.ready = false;
380 }
381 }
382 /* publish sched.ready flag update effective immediately across smp */
383 smp_rmb();
384 return 0;
385}
386
387static int amdgpu_debugfs_jpeg_sched_mask_get(void *data, u64 *val)
388{
389 struct amdgpu_device *adev = (struct amdgpu_device *)data;
390 u32 i, j;
391 u64 mask = 0;
392 struct amdgpu_ring *ring;
393
394 if (!adev)
395 return -ENODEV;
396 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
397 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
398 ring = &adev->jpeg.inst[i].ring_dec[j];
399 if (ring->sched.ready)
400 mask |= 1ULL << ((i * adev->jpeg.num_jpeg_rings) + j);
401 }
402 }
403 *val = mask;
404 return 0;
405}
406
407DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_jpeg_sched_mask_fops,
408 amdgpu_debugfs_jpeg_sched_mask_get,
409 amdgpu_debugfs_jpeg_sched_mask_set, "%llx\n");
410
411#endif
412
413void amdgpu_debugfs_jpeg_sched_mask_init(struct amdgpu_device *adev)
414{
415#if defined(CONFIG_DEBUG_FS)
416 struct drm_minor *minor = adev_to_drm(adev)->primary;
417 struct dentry *root = minor->debugfs_root;
418 char name[32];
419
420 if (!(adev->jpeg.num_jpeg_inst > 1) && !(adev->jpeg.num_jpeg_rings > 1))
421 return;
422 sprintf(name, "amdgpu_jpeg_sched_mask");
423 debugfs_create_file(name, 0600, root, adev,
424 &amdgpu_debugfs_jpeg_sched_mask_fops);
425#endif
426}
427
428static ssize_t amdgpu_get_jpeg_reset_mask(struct device *dev,
429 struct device_attribute *attr,
430 char *buf)
431{
432 struct drm_device *ddev = dev_get_drvdata(dev);
433 struct amdgpu_device *adev = drm_to_adev(ddev);
434
435 if (!adev)
436 return -ENODEV;
437
438 return amdgpu_show_reset_mask(buf, adev->jpeg.supported_reset);
439}
440
441static DEVICE_ATTR(jpeg_reset_mask, 0444,
442 amdgpu_get_jpeg_reset_mask, NULL);
443
444int amdgpu_jpeg_sysfs_reset_mask_init(struct amdgpu_device *adev)
445{
446 int r = 0;
447
448 if (adev->jpeg.num_jpeg_inst) {
449 r = device_create_file(adev->dev, &dev_attr_jpeg_reset_mask);
450 if (r)
451 return r;
452 }
453
454 return r;
455}
456
457void amdgpu_jpeg_sysfs_reset_mask_fini(struct amdgpu_device *adev)
458{
459 if (adev->dev->kobj.sd) {
460 if (adev->jpeg.num_jpeg_inst)
461 device_remove_file(adev->dev, &dev_attr_jpeg_reset_mask);
462 }
463}
464
465int amdgpu_jpeg_reg_dump_init(struct amdgpu_device *adev,
466 const struct amdgpu_hwip_reg_entry *reg, u32 count)
467{
468 adev->jpeg.ip_dump = kcalloc(adev->jpeg.num_jpeg_inst * count,
469 sizeof(uint32_t), GFP_KERNEL);
470 if (!adev->jpeg.ip_dump) {
471 dev_err(adev->dev,
472 "Failed to allocate memory for JPEG IP Dump\n");
473 return -ENOMEM;
474 }
475 adev->jpeg.reg_list = reg;
476 adev->jpeg.reg_count = count;
477
478 return 0;
479}
480
481static void amdgpu_jpeg_reg_dump_fini(struct amdgpu_device *adev)
482{
483 kfree(adev->jpeg.ip_dump);
484 adev->jpeg.reg_list = NULL;
485 adev->jpeg.reg_count = 0;
486}
487
488void amdgpu_jpeg_dump_ip_state(struct amdgpu_ip_block *ip_block)
489{
490 struct amdgpu_device *adev = ip_block->adev;
491 u32 inst_off, inst_id, is_powered;
492 int i, j;
493
494 if (!adev->jpeg.ip_dump)
495 return;
496
497 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
498 if (adev->jpeg.harvest_config & (1 << i))
499 continue;
500
501 inst_id = GET_INST(JPEG, i);
502 inst_off = i * adev->jpeg.reg_count;
503 /* check power status from UVD_JPEG_POWER_STATUS */
504 adev->jpeg.ip_dump[inst_off] =
505 RREG32(SOC15_REG_ENTRY_OFFSET_INST(adev->jpeg.reg_list[0],
506 inst_id));
507 is_powered = ((adev->jpeg.ip_dump[inst_off] & 0x1) != 1);
508
509 if (is_powered)
510 for (j = 1; j < adev->jpeg.reg_count; j++)
511 adev->jpeg.ip_dump[inst_off + j] =
512 RREG32(SOC15_REG_ENTRY_OFFSET_INST(adev->jpeg.reg_list[j],
513 inst_id));
514 }
515}
516
517void amdgpu_jpeg_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
518{
519 struct amdgpu_device *adev = ip_block->adev;
520 u32 inst_off, is_powered;
521 int i, j;
522
523 if (!adev->jpeg.ip_dump)
524 return;
525
526 drm_printf(p, "num_instances:%d\n", adev->jpeg.num_jpeg_inst);
527 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
528 if (adev->jpeg.harvest_config & (1 << i)) {
529 drm_printf(p, "\nHarvested Instance:JPEG%d Skipping dump\n", i);
530 continue;
531 }
532
533 inst_off = i * adev->jpeg.reg_count;
534 is_powered = ((adev->jpeg.ip_dump[inst_off] & 0x1) != 1);
535
536 if (is_powered) {
537 drm_printf(p, "Active Instance:JPEG%d\n", i);
538 for (j = 0; j < adev->jpeg.reg_count; j++)
539 drm_printf(p, "%-50s \t 0x%08x\n", adev->jpeg.reg_list[j].reg_name,
540 adev->jpeg.ip_dump[inst_off + j]);
541 } else
542 drm_printf(p, "\nInactive Instance:JPEG%d\n", i);
543 }
544}
545
546static inline bool amdgpu_jpeg_reg_valid(u32 reg)
547{
548 if (reg < JPEG_REG_RANGE_START || reg > JPEG_REG_RANGE_END ||
549 (reg >= JPEG_ATOMIC_RANGE_START && reg <= JPEG_ATOMIC_RANGE_END))
550 return false;
551 else
552 return true;
553}
554
555/**
556 * amdgpu_jpeg_dec_parse_cs - command submission parser
557 *
558 * @parser: Command submission parser context
559 * @job: the job to parse
560 * @ib: the IB to parse
561 *
562 * Parse the command stream, return -EINVAL for invalid packet,
563 * 0 otherwise
564 */
565
566int amdgpu_jpeg_dec_parse_cs(struct amdgpu_cs_parser *parser,
567 struct amdgpu_job *job,
568 struct amdgpu_ib *ib)
569{
570 u32 i, reg, res, cond, type;
571 struct amdgpu_device *adev = parser->adev;
572
573 for (i = 0; i < ib->length_dw ; i += 2) {
574 reg = CP_PACKETJ_GET_REG(ib->ptr[i]);
575 res = CP_PACKETJ_GET_RES(ib->ptr[i]);
576 cond = CP_PACKETJ_GET_COND(ib->ptr[i]);
577 type = CP_PACKETJ_GET_TYPE(ib->ptr[i]);
578
579 if (res) /* only support 0 at the moment */
580 return -EINVAL;
581
582 switch (type) {
583 case PACKETJ_TYPE0:
584 if (cond != PACKETJ_CONDITION_CHECK0 ||
585 !amdgpu_jpeg_reg_valid(reg)) {
586 dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
587 return -EINVAL;
588 }
589 break;
590 case PACKETJ_TYPE3:
591 if (cond != PACKETJ_CONDITION_CHECK3 ||
592 !amdgpu_jpeg_reg_valid(reg)) {
593 dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
594 return -EINVAL;
595 }
596 break;
597 case PACKETJ_TYPE6:
598 if (ib->ptr[i] == CP_PACKETJ_NOP)
599 continue;
600 dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
601 return -EINVAL;
602 default:
603 dev_err(adev->dev, "Unknown packet type %d !\n", type);
604 return -EINVAL;
605 }
606 }
607
608 return 0;
609}