| 1 | |
| 2 | * Copyright (C) 2021 Advanced Micro Devices, Inc.
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| 3 | *
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a
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| 5 | * copy of this software and associated documentation files (the "Software"),
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| 6 | * to deal in the Software without restriction, including without limitation
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the
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| 9 | * Software is furnished to do so, subject to the following conditions:
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| 10 | *
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| 11 | * The above copyright notice and this permission notice shall be included
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| 12 | * in all copies or substantial portions of the Software.
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| 13 | *
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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| 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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| 17 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
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| 18 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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| 19 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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| 20 |
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| 21 | #ifndef __AMDGPU_MCA_H__
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| 22 | #define __AMDGPU_MCA_H__
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| 23 |
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| 24 | #include "amdgpu_ras.h"
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| 25 |
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| 26 | enum amdgpu_mca_error_type {
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| 27 | AMDGPU_MCA_ERROR_TYPE_UE = 0,
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| 28 | AMDGPU_MCA_ERROR_TYPE_CE,
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| 29 | };
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| 30 |
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| 31 | struct amdgpu_mca_ras_block {
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| 32 | struct amdgpu_ras_block_object ras_block;
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| 33 | };
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| 34 |
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| 35 | struct amdgpu_mca_ras {
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| 36 | struct ras_common_if *ras_if;
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| 37 | struct amdgpu_mca_ras_block *ras;
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| 38 | };
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| 39 |
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| 40 | struct amdgpu_mca {
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| 41 | struct amdgpu_mca_ras mp0;
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| 42 | struct amdgpu_mca_ras mp1;
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| 43 | struct amdgpu_mca_ras mpio;
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| 44 | };
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| 45 |
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| 46 | void amdgpu_mca_query_correctable_error_count(struct amdgpu_device *adev,
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| 47 | uint64_t mc_status_addr,
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| 48 | unsigned long *error_count);
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| 49 | void amdgpu_mca_query_uncorrectable_error_count(struct amdgpu_device *adev,
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| 50 | uint64_t mc_status_addr,
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| 51 | unsigned long *error_count);
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| 52 | void amdgpu_mca_reset_error_count(struct amdgpu_device *adev,
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| 53 | uint64_t mc_status_addr);
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| 54 | void amdgpu_mca_query_ras_error_count(struct amdgpu_device *adev,
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| 55 | uint64_t mc_status_addr,
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| 56 | void *ras_error_status);
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| 57 | int amdgpu_mca_mp0_ras_sw_init(struct amdgpu_device *adev);
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| 58 | int amdgpu_mca_mp1_ras_sw_init(struct amdgpu_device *adev);
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| 59 | int amdgpu_mca_mpio_ras_sw_init(struct amdgpu_device *adev);
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| 60 |
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| 61 | #endif
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