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1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Author: Huang Rui
23 *
24 */
25
26#include <linux/firmware.h>
27#include <drm/drm_drv.h>
28
29#include "amdgpu.h"
30#include "amdgpu_psp.h"
31#include "amdgpu_ucode.h"
32#include "amdgpu_xgmi.h"
33#include "soc15_common.h"
34#include "psp_v3_1.h"
35#include "psp_v10_0.h"
36#include "psp_v11_0.h"
37#include "psp_v11_0_8.h"
38#include "psp_v12_0.h"
39#include "psp_v13_0.h"
40#include "psp_v13_0_4.h"
41#include "psp_v14_0.h"
42#include "psp_v15_0.h"
43#include "psp_v15_0_8.h"
44
45#include "amdgpu_ras.h"
46#include "amdgpu_securedisplay.h"
47#include "amdgpu_atomfirmware.h"
48
49#define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*16)
50
51static int psp_load_smu_fw(struct psp_context *psp);
52static int psp_rap_terminate(struct psp_context *psp);
53static int psp_securedisplay_terminate(struct psp_context *psp);
54
55static const char * const amdgpu_ptl_fmt_str[] = {
56 [AMDGPU_PTL_FMT_I8] = "I8",
57 [AMDGPU_PTL_FMT_F16] = "F16",
58 [AMDGPU_PTL_FMT_BF16] = "BF16",
59 [AMDGPU_PTL_FMT_F32] = "F32",
60 [AMDGPU_PTL_FMT_F64] = "F64",
61 [AMDGPU_PTL_FMT_F8] = "F8",
62 [AMDGPU_PTL_FMT_VECTOR] = "VECTOR",
63 [AMDGPU_PTL_FMT_INVALID] = "INVALID",
64};
65
66static int psp_ring_init(struct psp_context *psp,
67 enum psp_ring_type ring_type)
68{
69 int ret = 0;
70 struct psp_ring *ring;
71 struct amdgpu_device *adev = psp->adev;
72
73 ring = &psp->km_ring;
74
75 ring->ring_type = ring_type;
76
77 /* allocate 4k Page of Local Frame Buffer memory for ring */
78 ring->ring_size = 0x1000;
79 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
80 AMDGPU_GEM_DOMAIN_VRAM |
81 AMDGPU_GEM_DOMAIN_GTT,
82 &adev->firmware.rbuf,
83 &ring->ring_mem_mc_addr,
84 (void **)&ring->ring_mem);
85 if (ret) {
86 ring->ring_size = 0;
87 return ret;
88 }
89
90 return 0;
91}
92
93/*
94 * Due to DF Cstate management centralized to PMFW, the firmware
95 * loading sequence will be updated as below:
96 * - Load KDB
97 * - Load SYS_DRV
98 * - Load tOS
99 * - Load PMFW
100 * - Setup TMR
101 * - Load other non-psp fw
102 * - Load ASD
103 * - Load XGMI/RAS/HDCP/DTM TA if any
104 *
105 * This new sequence is required for
106 * - Arcturus and onwards
107 */
108static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp)
109{
110 struct amdgpu_device *adev = psp->adev;
111
112 if (amdgpu_sriov_vf(adev)) {
113 psp->pmfw_centralized_cstate_management = false;
114 return;
115 }
116
117 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
118 case IP_VERSION(11, 0, 0):
119 case IP_VERSION(11, 0, 4):
120 case IP_VERSION(11, 0, 5):
121 case IP_VERSION(11, 0, 7):
122 case IP_VERSION(11, 0, 9):
123 case IP_VERSION(11, 0, 11):
124 case IP_VERSION(11, 0, 12):
125 case IP_VERSION(11, 0, 13):
126 case IP_VERSION(13, 0, 0):
127 case IP_VERSION(13, 0, 2):
128 case IP_VERSION(13, 0, 7):
129 psp->pmfw_centralized_cstate_management = true;
130 break;
131 default:
132 psp->pmfw_centralized_cstate_management = false;
133 break;
134 }
135}
136
137static int psp_init_sriov_microcode(struct psp_context *psp)
138{
139 struct amdgpu_device *adev = psp->adev;
140 char ucode_prefix[30];
141 int ret = 0;
142
143 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
144
145 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
146 case IP_VERSION(9, 0, 0):
147 case IP_VERSION(11, 0, 7):
148 case IP_VERSION(11, 0, 9):
149 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
150 ret = psp_init_cap_microcode(psp, ucode_prefix);
151 break;
152 case IP_VERSION(13, 0, 2):
153 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
154 ret = psp_init_cap_microcode(psp, ucode_prefix);
155 ret &= psp_init_ta_microcode(psp, ucode_prefix);
156 break;
157 case IP_VERSION(13, 0, 0):
158 adev->virt.autoload_ucode_id = 0;
159 break;
160 case IP_VERSION(13, 0, 6):
161 case IP_VERSION(13, 0, 14):
162 case IP_VERSION(13, 0, 15):
163 ret = psp_init_cap_microcode(psp, ucode_prefix);
164 ret &= psp_init_ta_microcode(psp, ucode_prefix);
165 break;
166 case IP_VERSION(13, 0, 10):
167 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA;
168 ret = psp_init_cap_microcode(psp, ucode_prefix);
169 break;
170 case IP_VERSION(13, 0, 12):
171 ret = psp_init_ta_microcode(psp, ucode_prefix);
172 break;
173 default:
174 return -EINVAL;
175 }
176 return ret;
177}
178
179static int psp_early_init(struct amdgpu_ip_block *ip_block)
180{
181 struct amdgpu_device *adev = ip_block->adev;
182 struct psp_context *psp = &adev->psp;
183
184 psp->autoload_supported = true;
185 psp->boot_time_tmr = true;
186
187 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
188 case IP_VERSION(9, 0, 0):
189 psp_v3_1_set_psp_funcs(psp);
190 psp->autoload_supported = false;
191 psp->boot_time_tmr = false;
192 break;
193 case IP_VERSION(10, 0, 0):
194 case IP_VERSION(10, 0, 1):
195 psp_v10_0_set_psp_funcs(psp);
196 psp->autoload_supported = false;
197 psp->boot_time_tmr = false;
198 break;
199 case IP_VERSION(11, 0, 2):
200 case IP_VERSION(11, 0, 4):
201 psp_v11_0_set_psp_funcs(psp);
202 psp->autoload_supported = false;
203 psp->boot_time_tmr = false;
204 break;
205 case IP_VERSION(11, 0, 0):
206 case IP_VERSION(11, 0, 7):
207 adev->psp.sup_pd_fw_up = !amdgpu_sriov_vf(adev);
208 fallthrough;
209 case IP_VERSION(11, 0, 5):
210 case IP_VERSION(11, 0, 9):
211 case IP_VERSION(11, 0, 11):
212 case IP_VERSION(11, 5, 0):
213 case IP_VERSION(11, 5, 2):
214 case IP_VERSION(11, 0, 12):
215 case IP_VERSION(11, 0, 13):
216 psp_v11_0_set_psp_funcs(psp);
217 psp->boot_time_tmr = false;
218 break;
219 case IP_VERSION(11, 0, 3):
220 case IP_VERSION(12, 0, 1):
221 psp_v12_0_set_psp_funcs(psp);
222 psp->autoload_supported = false;
223 psp->boot_time_tmr = false;
224 break;
225 case IP_VERSION(13, 0, 2):
226 psp->boot_time_tmr = false;
227 fallthrough;
228 case IP_VERSION(13, 0, 6):
229 case IP_VERSION(13, 0, 14):
230 psp_v13_0_set_psp_funcs(psp);
231 psp->autoload_supported = false;
232 break;
233 case IP_VERSION(13, 0, 12):
234 case IP_VERSION(13, 0, 15):
235 psp_v13_0_set_psp_funcs(psp);
236 psp->autoload_supported = false;
237 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev);
238 break;
239 case IP_VERSION(13, 0, 1):
240 case IP_VERSION(13, 0, 3):
241 case IP_VERSION(13, 0, 5):
242 case IP_VERSION(13, 0, 8):
243 case IP_VERSION(13, 0, 11):
244 case IP_VERSION(14, 0, 0):
245 case IP_VERSION(14, 0, 1):
246 case IP_VERSION(14, 0, 4):
247 psp_v13_0_set_psp_funcs(psp);
248 psp->boot_time_tmr = false;
249 break;
250 case IP_VERSION(11, 0, 8):
251 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) {
252 psp_v11_0_8_set_psp_funcs(psp);
253 }
254 psp->autoload_supported = false;
255 psp->boot_time_tmr = false;
256 break;
257 case IP_VERSION(13, 0, 0):
258 case IP_VERSION(13, 0, 7):
259 case IP_VERSION(13, 0, 10):
260 psp_v13_0_set_psp_funcs(psp);
261 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev);
262 psp->boot_time_tmr = false;
263 break;
264 case IP_VERSION(13, 0, 4):
265 psp_v13_0_4_set_psp_funcs(psp);
266 psp->boot_time_tmr = false;
267 break;
268 case IP_VERSION(14, 0, 2):
269 case IP_VERSION(14, 0, 3):
270 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev);
271 psp_v14_0_set_psp_funcs(psp);
272 break;
273 case IP_VERSION(14, 0, 5):
274 psp_v14_0_set_psp_funcs(psp);
275 psp->boot_time_tmr = false;
276 break;
277 case IP_VERSION(15, 0, 0):
278 case IP_VERSION(15, 0, 5):
279 case IP_VERSION(15, 0, 9):
280 psp_v15_0_0_set_psp_funcs(psp);
281 psp->boot_time_tmr = false;
282 break;
283 case IP_VERSION(15, 0, 8):
284 psp_v15_0_8_set_psp_funcs(psp);
285 break;
286 default:
287 return -EINVAL;
288 }
289
290 psp->adev = adev;
291
292 adev->psp_timeout = 20000;
293
294 psp_check_pmfw_centralized_cstate_management(psp);
295
296 if (amdgpu_sriov_vf(adev))
297 return psp_init_sriov_microcode(psp);
298 else
299 return psp_init_microcode(psp);
300}
301
302void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx)
303{
304 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr,
305 &mem_ctx->shared_buf);
306 mem_ctx->shared_bo = NULL;
307}
308
309static void psp_free_shared_bufs(struct psp_context *psp)
310{
311 void *tmr_buf;
312 void **pptr;
313
314 /* free TMR memory buffer */
315 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
316 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
317 psp->tmr_bo = NULL;
318
319 /* free xgmi shared memory */
320 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context);
321
322 /* free ras shared memory */
323 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context);
324
325 /* free hdcp shared memory */
326 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context);
327
328 /* free dtm shared memory */
329 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context);
330
331 /* free rap shared memory */
332 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
333
334 /* free securedisplay shared memory */
335 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
336
337
338}
339
340static void psp_memory_training_fini(struct psp_context *psp)
341{
342 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
343
344 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
345 kfree(ctx->sys_cache);
346 ctx->sys_cache = NULL;
347}
348
349static int psp_memory_training_init(struct psp_context *psp)
350{
351 int ret;
352 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
353
354 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
355 dev_dbg(psp->adev->dev, "memory training is not supported!\n");
356 return 0;
357 }
358
359 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
360 if (ctx->sys_cache == NULL) {
361 dev_err(psp->adev->dev, "alloc mem_train_ctx.sys_cache failed!\n");
362 ret = -ENOMEM;
363 goto Err_out;
364 }
365
366 dev_dbg(psp->adev->dev,
367 "train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
368 ctx->train_data_size,
369 ctx->p2c_train_data_offset,
370 ctx->c2p_train_data_offset);
371 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
372 return 0;
373
374Err_out:
375 psp_memory_training_fini(psp);
376 return ret;
377}
378
379/*
380 * Helper funciton to query psp runtime database entry
381 *
382 * @adev: amdgpu_device pointer
383 * @entry_type: the type of psp runtime database entry
384 * @db_entry: runtime database entry pointer
385 *
386 * Return false if runtime database doesn't exit or entry is invalid
387 * or true if the specific database entry is found, and copy to @db_entry
388 */
389static bool psp_get_runtime_db_entry(struct amdgpu_device *adev,
390 enum psp_runtime_entry_type entry_type,
391 void *db_entry)
392{
393 uint64_t db_header_pos, db_dir_pos;
394 struct psp_runtime_data_header db_header = {0};
395 struct psp_runtime_data_directory db_dir = {0};
396 bool ret = false;
397 int i;
398
399 /*
400 * Runtime DB is for dGPUs only.
401 */
402 if (adev->flags & AMD_IS_APU)
403 return false;
404
405 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||
406 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) ||
407 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) ||
408 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15))
409 return false;
410
411 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET;
412 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header);
413
414 /* read runtime db header from vram */
415 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header,
416 sizeof(struct psp_runtime_data_header), false);
417
418 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) {
419 /* runtime db doesn't exist, exit */
420 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n");
421 return false;
422 }
423
424 /* read runtime database entry from vram */
425 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir,
426 sizeof(struct psp_runtime_data_directory), false);
427
428 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) {
429 /* invalid db entry count, exit */
430 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n");
431 return false;
432 }
433
434 /* look up for requested entry type */
435 for (i = 0; i < db_dir.entry_count && !ret; i++) {
436 if (db_dir.entry_list[i].entry_type == entry_type) {
437 switch (entry_type) {
438 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG:
439 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) {
440 /* invalid db entry size */
441 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n");
442 return false;
443 }
444 /* read runtime database entry */
445 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
446 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false);
447 ret = true;
448 break;
449 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS:
450 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) {
451 /* invalid db entry size */
452 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n");
453 return false;
454 }
455 /* read runtime database entry */
456 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
457 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false);
458 ret = true;
459 break;
460 default:
461 ret = false;
462 break;
463 }
464 }
465 }
466
467 return ret;
468}
469
470static int psp_sw_init(struct amdgpu_ip_block *ip_block)
471{
472 struct amdgpu_device *adev = ip_block->adev;
473 struct psp_context *psp = &adev->psp;
474 int ret;
475 struct psp_runtime_boot_cfg_entry boot_cfg_entry;
476 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx;
477 struct psp_runtime_scpm_entry scpm_entry;
478
479 psp->cmd = kzalloc_obj(struct psp_gfx_cmd_resp);
480 if (!psp->cmd) {
481 dev_err(adev->dev, "Failed to allocate memory to command buffer!\n");
482 return -ENOMEM;
483 }
484
485 adev->psp.xgmi_context.supports_extended_data =
486 !adev->gmc.xgmi.connected_to_cpu &&
487 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2);
488
489 memset(&scpm_entry, 0, sizeof(scpm_entry));
490 if ((psp_get_runtime_db_entry(adev,
491 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS,
492 &scpm_entry)) &&
493 (scpm_entry.scpm_status != SCPM_DISABLE)) {
494 adev->scpm_enabled = true;
495 adev->scpm_status = scpm_entry.scpm_status;
496 } else {
497 adev->scpm_enabled = false;
498 adev->scpm_status = SCPM_DISABLE;
499 }
500
501 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */
502
503 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry));
504 if (psp_get_runtime_db_entry(adev,
505 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG,
506 &boot_cfg_entry)) {
507 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask;
508 if ((psp->boot_cfg_bitmask) &
509 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) {
510 /* If psp runtime database exists, then
511 * only enable two stage memory training
512 * when TWO_STAGE_DRAM_TRAINING bit is set
513 * in runtime database
514 */
515 mem_training_ctx->enable_mem_training = true;
516 }
517
518 } else {
519 /* If psp runtime database doesn't exist or is
520 * invalid, force enable two stage memory training
521 */
522 mem_training_ctx->enable_mem_training = true;
523 }
524
525 if (mem_training_ctx->enable_mem_training) {
526 ret = psp_memory_training_init(psp);
527 if (ret) {
528 dev_err(adev->dev, "Failed to initialize memory training!\n");
529 return ret;
530 }
531
532 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
533 if (ret) {
534 dev_err(adev->dev, "Failed to process memory training!\n");
535 return ret;
536 }
537 }
538
539 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
540 (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf || adev->gmc.xgmi.connected_to_cpu) ?
541 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
542 &psp->fw_pri_bo,
543 &psp->fw_pri_mc_addr,
544 &psp->fw_pri_buf);
545 if (ret)
546 return ret;
547
548 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
549 AMDGPU_GEM_DOMAIN_VRAM |
550 AMDGPU_GEM_DOMAIN_GTT,
551 &psp->fence_buf_bo,
552 &psp->fence_buf_mc_addr,
553 &psp->fence_buf);
554 if (ret)
555 goto failed1;
556
557 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
558 AMDGPU_GEM_DOMAIN_VRAM |
559 AMDGPU_GEM_DOMAIN_GTT,
560 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
561 (void **)&psp->cmd_buf_mem);
562 if (ret)
563 goto failed2;
564
565 return 0;
566
567failed2:
568 amdgpu_bo_free_kernel(&psp->fence_buf_bo,
569 &psp->fence_buf_mc_addr, &psp->fence_buf);
570failed1:
571 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
572 &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
573 return ret;
574}
575
576static int psp_sw_fini(struct amdgpu_ip_block *ip_block)
577{
578 struct amdgpu_device *adev = ip_block->adev;
579 struct psp_context *psp = &adev->psp;
580
581 psp_memory_training_fini(psp);
582
583 amdgpu_ucode_release(&psp->sos_fw);
584 amdgpu_ucode_release(&psp->asd_fw);
585 amdgpu_ucode_release(&psp->ta_fw);
586 amdgpu_ucode_release(&psp->cap_fw);
587 amdgpu_ucode_release(&psp->toc_fw);
588
589 kfree(psp->cmd);
590 psp->cmd = NULL;
591
592 psp_free_shared_bufs(psp);
593
594 if (psp->km_ring.ring_mem)
595 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
596 &psp->km_ring.ring_mem_mc_addr,
597 (void **)&psp->km_ring.ring_mem);
598
599 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
600 &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
601 amdgpu_bo_free_kernel(&psp->fence_buf_bo,
602 &psp->fence_buf_mc_addr, &psp->fence_buf);
603 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
604 (void **)&psp->cmd_buf_mem);
605
606 return 0;
607}
608
609int psp_wait_for(struct psp_context *psp, uint32_t reg_index, uint32_t reg_val,
610 uint32_t mask, uint32_t flags)
611{
612 bool check_changed = flags & PSP_WAITREG_CHANGED;
613 bool verbose = !(flags & PSP_WAITREG_NOVERBOSE);
614 uint32_t val;
615 int i;
616 struct amdgpu_device *adev = psp->adev;
617
618 if (psp->adev->no_hw_access)
619 return 0;
620
621 for (i = 0; i < adev->usec_timeout; i++) {
622 val = RREG32(reg_index);
623 if (check_changed) {
624 if (val != reg_val)
625 return 0;
626 } else {
627 if ((val & mask) == reg_val)
628 return 0;
629 }
630 udelay(1);
631 }
632
633 if (verbose)
634 dev_err(adev->dev,
635 "psp reg (0x%x) wait timed out, mask: %x, read: %x exp: %x",
636 reg_index, mask, val, reg_val);
637
638 return -ETIME;
639}
640
641int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index,
642 uint32_t reg_val, uint32_t mask, uint32_t msec_timeout)
643{
644 uint32_t val;
645 int i;
646 struct amdgpu_device *adev = psp->adev;
647
648 if (psp->adev->no_hw_access)
649 return 0;
650
651 for (i = 0; i < msec_timeout; i++) {
652 val = RREG32(reg_index);
653 if ((val & mask) == reg_val)
654 return 0;
655 msleep(1);
656 }
657
658 return -ETIME;
659}
660
661static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id)
662{
663 switch (cmd_id) {
664 case GFX_CMD_ID_LOAD_TA:
665 return "LOAD_TA";
666 case GFX_CMD_ID_UNLOAD_TA:
667 return "UNLOAD_TA";
668 case GFX_CMD_ID_INVOKE_CMD:
669 return "INVOKE_CMD";
670 case GFX_CMD_ID_LOAD_ASD:
671 return "LOAD_ASD";
672 case GFX_CMD_ID_SETUP_TMR:
673 return "SETUP_TMR";
674 case GFX_CMD_ID_LOAD_IP_FW:
675 return "LOAD_IP_FW";
676 case GFX_CMD_ID_DESTROY_TMR:
677 return "DESTROY_TMR";
678 case GFX_CMD_ID_SAVE_RESTORE:
679 return "SAVE_RESTORE_IP_FW";
680 case GFX_CMD_ID_SETUP_VMR:
681 return "SETUP_VMR";
682 case GFX_CMD_ID_DESTROY_VMR:
683 return "DESTROY_VMR";
684 case GFX_CMD_ID_PROG_REG:
685 return "PROG_REG";
686 case GFX_CMD_ID_GET_FW_ATTESTATION:
687 return "GET_FW_ATTESTATION";
688 case GFX_CMD_ID_LOAD_TOC:
689 return "ID_LOAD_TOC";
690 case GFX_CMD_ID_AUTOLOAD_RLC:
691 return "AUTOLOAD_RLC";
692 case GFX_CMD_ID_BOOT_CFG:
693 return "BOOT_CFG";
694 case GFX_CMD_ID_CONFIG_SQ_PERFMON:
695 return "CONFIG_SQ_PERFMON";
696 case GFX_CMD_ID_FB_FW_RESERV_ADDR:
697 return "FB_FW_RESERV_ADDR";
698 case GFX_CMD_ID_FB_FW_RESERV_EXT_ADDR:
699 return "FB_FW_RESERV_EXT_ADDR";
700 case GFX_CMD_ID_SRIOV_SPATIAL_PART:
701 return "SPATIAL_PARTITION";
702 case GFX_CMD_ID_FB_NPS_MODE:
703 return "NPS_MODE_CHANGE";
704 case GFX_CMD_ID_PERF_HW:
705 return "PERF MONITORING HW";
706 default:
707 return "UNKNOWN CMD";
708 }
709}
710
711static bool psp_err_warn(struct psp_context *psp)
712{
713 struct psp_gfx_cmd_resp *cmd = psp->cmd_buf_mem;
714
715 /* This response indicates reg list is already loaded */
716 if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) &&
717 cmd->cmd_id == GFX_CMD_ID_LOAD_IP_FW &&
718 cmd->cmd.cmd_load_ip_fw.fw_type == GFX_FW_TYPE_REG_LIST &&
719 cmd->resp.status == TEE_ERROR_CANCEL)
720 return false;
721
722 return true;
723}
724
725static int
726psp_cmd_submit_buf(struct psp_context *psp,
727 struct amdgpu_firmware_info *ucode,
728 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
729{
730 int ret;
731 int index;
732 int timeout = psp->adev->psp_timeout;
733 bool ras_intr = false;
734 bool skip_unsupport = false;
735
736 if (psp->adev->no_hw_access)
737 return 0;
738
739 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
740
741 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
742
743 index = atomic_inc_return(&psp->fence_value);
744 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
745 if (ret) {
746 atomic_dec(&psp->fence_value);
747 goto exit;
748 }
749
750 amdgpu_device_invalidate_hdp(psp->adev, NULL);
751 while (*((unsigned int *)psp->fence_buf) != index) {
752 if (--timeout == 0)
753 break;
754 /*
755 * Shouldn't wait for timeout when err_event_athub occurs,
756 * because gpu reset thread triggered and lock resource should
757 * be released for psp resume sequence.
758 */
759 ras_intr = amdgpu_ras_intr_triggered();
760 if (ras_intr)
761 break;
762 usleep_range(60, 100);
763 amdgpu_device_invalidate_hdp(psp->adev, NULL);
764 }
765
766 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
767 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED ||
768 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev);
769
770 memcpy(&cmd->resp, &psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp));
771
772 /* In some cases, psp response status is not 0 even there is no
773 * problem while the command is submitted. Some version of PSP FW
774 * doesn't write 0 to that field.
775 * So here we would like to only print a warning instead of an error
776 * during psp initialization to avoid breaking hw_init and it doesn't
777 * return -EINVAL.
778 */
779 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
780 if (ucode)
781 dev_warn(psp->adev->dev,
782 "failed to load ucode %s(0x%X) ",
783 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id);
784 if (psp_err_warn(psp))
785 dev_warn(
786 psp->adev->dev,
787 "psp gfx command %s(0x%X) failed and response status is (0x%X)\n",
788 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id),
789 psp->cmd_buf_mem->cmd_id,
790 psp->cmd_buf_mem->resp.status);
791 /* If any firmware (including CAP) load fails under SRIOV, it should
792 * return failure to stop the VF from initializing.
793 * Also return failure in case of timeout
794 */
795 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) {
796 ret = -EINVAL;
797 goto exit;
798 }
799 }
800
801 if (ucode) {
802 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
803 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
804 }
805
806exit:
807 return ret;
808}
809
810static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp)
811{
812 struct psp_gfx_cmd_resp *cmd = psp->cmd;
813
814 mutex_lock(&psp->mutex);
815
816 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
817
818 return cmd;
819}
820
821static void release_psp_cmd_buf(struct psp_context *psp)
822{
823 mutex_unlock(&psp->mutex);
824}
825
826static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
827 struct psp_gfx_cmd_resp *cmd,
828 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo)
829{
830 struct amdgpu_device *adev = psp->adev;
831 uint32_t size = 0;
832 uint64_t tmr_pa = 0;
833
834 if (tmr_bo) {
835 size = amdgpu_bo_size(tmr_bo);
836 tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo);
837 }
838
839 if (amdgpu_sriov_vf(psp->adev))
840 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
841 else
842 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
843 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
844 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
845 cmd->cmd.cmd_setup_tmr.buf_size = size;
846 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1;
847 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa);
848 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa);
849}
850
851static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
852 uint64_t pri_buf_mc, uint32_t size)
853{
854 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
855 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
856 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
857 cmd->cmd.cmd_load_toc.toc_size = size;
858}
859
860/* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
861static int psp_load_toc(struct psp_context *psp,
862 uint32_t *tmr_size)
863{
864 int ret;
865 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
866
867 /* Copy toc to psp firmware private buffer */
868 ret = psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes);
869 if (ret) {
870 release_psp_cmd_buf(psp);
871 return ret;
872 }
873
874 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes);
875
876 ret = psp_cmd_submit_buf(psp, NULL, cmd,
877 psp->fence_buf_mc_addr);
878 if (!ret)
879 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
880
881 release_psp_cmd_buf(psp);
882
883 return ret;
884}
885
886/* Set up Trusted Memory Region */
887static int psp_tmr_init(struct psp_context *psp)
888{
889 int ret = 0;
890 int tmr_size;
891 void *tmr_buf;
892 void **pptr;
893
894 /*
895 * According to HW engineer, they prefer the TMR address be "naturally
896 * aligned" , e.g. the start address be an integer divide of TMR size.
897 *
898 * Note: this memory need be reserved till the driver
899 * uninitializes.
900 */
901 tmr_size = PSP_TMR_SIZE(psp->adev);
902
903 /* For ASICs support RLC autoload, psp will parse the toc
904 * and calculate the total size of TMR needed
905 */
906 if (!amdgpu_sriov_vf(psp->adev) &&
907 psp->toc.start_addr &&
908 psp->toc.size_bytes &&
909 psp->fw_pri_buf) {
910 ret = psp_load_toc(psp, &tmr_size);
911 if (ret) {
912 dev_err(psp->adev->dev, "Failed to load toc\n");
913 return ret;
914 }
915 }
916
917 if (!psp->tmr_bo && !psp->boot_time_tmr) {
918 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
919 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size,
920 PSP_TMR_ALIGNMENT,
921 AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM,
922 &psp->tmr_bo, &psp->tmr_mc_addr,
923 pptr);
924 }
925 if (amdgpu_virt_xgmi_migrate_enabled(psp->adev) && psp->tmr_bo)
926 psp->tmr_mc_addr = amdgpu_bo_fb_aper_addr(psp->tmr_bo);
927
928 return ret;
929}
930
931static bool psp_skip_tmr(struct psp_context *psp)
932{
933 u32 ip_version = amdgpu_ip_version(psp->adev, MP0_HWIP, 0);
934
935 if (amdgpu_sriov_vf(psp->adev))
936 return (ip_version >= IP_VERSION(11, 0, 7)) ? true : false;
937 else
938 return (!psp->boot_time_tmr || !psp->autoload_supported) ? false : true;
939}
940
941static int psp_tmr_load(struct psp_context *psp)
942{
943 int ret;
944 struct psp_gfx_cmd_resp *cmd;
945
946 if (psp_skip_tmr(psp))
947 return 0;
948
949 cmd = acquire_psp_cmd_buf(psp);
950
951 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo);
952 if (psp->tmr_bo)
953 dev_info(psp->adev->dev, "reserve 0x%lx from 0x%llx for PSP TMR\n",
954 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
955
956 ret = psp_cmd_submit_buf(psp, NULL, cmd,
957 psp->fence_buf_mc_addr);
958
959 release_psp_cmd_buf(psp);
960
961 return ret;
962}
963
964static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp,
965 struct psp_gfx_cmd_resp *cmd)
966{
967 if (amdgpu_sriov_vf(psp->adev))
968 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR;
969 else
970 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR;
971}
972
973static int psp_tmr_unload(struct psp_context *psp)
974{
975 int ret;
976 struct psp_gfx_cmd_resp *cmd;
977
978 if (psp_skip_tmr(psp))
979 return 0;
980
981 cmd = acquire_psp_cmd_buf(psp);
982
983 psp_prep_tmr_unload_cmd_buf(psp, cmd);
984 dev_dbg(psp->adev->dev, "free PSP TMR buffer\n");
985
986 ret = psp_cmd_submit_buf(psp, NULL, cmd,
987 psp->fence_buf_mc_addr);
988
989 release_psp_cmd_buf(psp);
990
991 return ret;
992}
993
994static int psp_tmr_terminate(struct psp_context *psp)
995{
996 return psp_tmr_unload(psp);
997}
998
999int psp_get_fw_attestation_records_addr(struct psp_context *psp,
1000 uint64_t *output_ptr)
1001{
1002 int ret;
1003 struct psp_gfx_cmd_resp *cmd;
1004
1005 if (!output_ptr)
1006 return -EINVAL;
1007
1008 if (amdgpu_sriov_vf(psp->adev))
1009 return 0;
1010
1011 cmd = acquire_psp_cmd_buf(psp);
1012
1013 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION;
1014
1015 ret = psp_cmd_submit_buf(psp, NULL, cmd,
1016 psp->fence_buf_mc_addr);
1017
1018 if (!ret) {
1019 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) +
1020 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32);
1021 }
1022
1023 release_psp_cmd_buf(psp);
1024
1025 return ret;
1026}
1027
1028static int psp_get_fw_reservation_info(struct psp_context *psp,
1029 uint32_t cmd_id,
1030 uint64_t *addr,
1031 uint32_t *size)
1032{
1033 int ret;
1034 uint32_t status;
1035 struct psp_gfx_cmd_resp *cmd;
1036
1037 cmd = acquire_psp_cmd_buf(psp);
1038
1039 cmd->cmd_id = cmd_id;
1040
1041 ret = psp_cmd_submit_buf(psp, NULL, cmd,
1042 psp->fence_buf_mc_addr);
1043 if (ret) {
1044 release_psp_cmd_buf(psp);
1045 return ret;
1046 }
1047
1048 status = cmd->resp.status;
1049 if (status == PSP_ERR_UNKNOWN_COMMAND) {
1050 release_psp_cmd_buf(psp);
1051 *addr = 0;
1052 *size = 0;
1053 return 0;
1054 }
1055
1056 *addr = (uint64_t)cmd->resp.uresp.fw_reserve_info.reserve_base_address_hi << 32 |
1057 cmd->resp.uresp.fw_reserve_info.reserve_base_address_lo;
1058 *size = cmd->resp.uresp.fw_reserve_info.reserve_size;
1059
1060 release_psp_cmd_buf(psp);
1061
1062 return 0;
1063}
1064
1065int psp_update_fw_reservation(struct psp_context *psp)
1066{
1067 int ret;
1068 uint64_t reserv_addr, reserv_addr_ext;
1069 uint32_t reserv_size, reserv_size_ext, mp0_ip_ver;
1070 struct amdgpu_device *adev = psp->adev;
1071
1072 mp0_ip_ver = amdgpu_ip_version(adev, MP0_HWIP, 0);
1073
1074 if (amdgpu_sriov_vf(psp->adev))
1075 return 0;
1076
1077 switch (mp0_ip_ver) {
1078 case IP_VERSION(14, 0, 2):
1079 if (adev->psp.sos.fw_version < 0x3b0e0d)
1080 return 0;
1081 break;
1082
1083 case IP_VERSION(14, 0, 3):
1084 if (adev->psp.sos.fw_version < 0x3a0e14)
1085 return 0;
1086 break;
1087
1088 default:
1089 return 0;
1090 }
1091
1092 ret = psp_get_fw_reservation_info(psp, GFX_CMD_ID_FB_FW_RESERV_ADDR, &reserv_addr, &reserv_size);
1093 if (ret)
1094 return ret;
1095 ret = psp_get_fw_reservation_info(psp, GFX_CMD_ID_FB_FW_RESERV_EXT_ADDR, &reserv_addr_ext, &reserv_size_ext);
1096 if (ret)
1097 return ret;
1098
1099 if (reserv_addr != adev->gmc.real_vram_size - reserv_size) {
1100 dev_warn(adev->dev, "reserve fw region is not valid!\n");
1101 return 0;
1102 }
1103
1104 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_FW);
1105
1106 reserv_size = roundup(reserv_size, SZ_1M);
1107
1108 amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW,
1109 reserv_addr, reserv_size, false);
1110 ret = amdgpu_ttm_mark_vram_reserved(adev, AMDGPU_RESV_FW);
1111 if (ret) {
1112 dev_err(adev->dev, "reserve fw region failed(%d)!\n", ret);
1113 return ret;
1114 }
1115
1116 reserv_size_ext = roundup(reserv_size_ext, SZ_1M);
1117
1118 amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW_EXTEND,
1119 reserv_addr_ext, reserv_size_ext, false);
1120 ret = amdgpu_ttm_mark_vram_reserved(adev, AMDGPU_RESV_FW_EXTEND);
1121 if (ret) {
1122 dev_err(adev->dev, "reserve extend fw region failed(%d)!\n", ret);
1123 return ret;
1124 }
1125
1126 return 0;
1127}
1128
1129static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg)
1130{
1131 struct psp_context *psp = &adev->psp;
1132 struct psp_gfx_cmd_resp *cmd;
1133 int ret;
1134
1135 if (amdgpu_sriov_vf(adev))
1136 return 0;
1137
1138 cmd = acquire_psp_cmd_buf(psp);
1139
1140 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
1141 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET;
1142
1143 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1144 if (!ret) {
1145 *boot_cfg =
1146 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0;
1147 }
1148
1149 release_psp_cmd_buf(psp);
1150
1151 return ret;
1152}
1153
1154static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg)
1155{
1156 int ret;
1157 struct psp_context *psp = &adev->psp;
1158 struct psp_gfx_cmd_resp *cmd;
1159
1160 if (amdgpu_sriov_vf(adev))
1161 return 0;
1162
1163 cmd = acquire_psp_cmd_buf(psp);
1164
1165 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
1166 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET;
1167 cmd->cmd.boot_cfg.boot_config = boot_cfg;
1168 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg;
1169
1170 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1171
1172 release_psp_cmd_buf(psp);
1173
1174 return ret;
1175}
1176
1177static int psp_rl_load(struct amdgpu_device *adev)
1178{
1179 int ret;
1180 struct psp_context *psp = &adev->psp;
1181 struct psp_gfx_cmd_resp *cmd;
1182
1183 if (!is_psp_fw_valid(psp->rl))
1184 return 0;
1185
1186 cmd = acquire_psp_cmd_buf(psp);
1187
1188 ret = psp_copy_fw(psp, psp->rl.start_addr, psp->rl.size_bytes);
1189 if (ret) {
1190 release_psp_cmd_buf(psp);
1191 return ret;
1192 }
1193
1194 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
1195 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr);
1196 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr);
1197 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes;
1198 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST;
1199
1200 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1201
1202 release_psp_cmd_buf(psp);
1203
1204 return ret;
1205}
1206
1207int psp_memory_partition(struct psp_context *psp, int mode)
1208{
1209 struct psp_gfx_cmd_resp *cmd;
1210 int ret;
1211
1212 if (amdgpu_sriov_vf(psp->adev))
1213 return 0;
1214
1215 cmd = acquire_psp_cmd_buf(psp);
1216
1217 cmd->cmd_id = GFX_CMD_ID_FB_NPS_MODE;
1218 cmd->cmd.cmd_memory_part.mode = mode;
1219
1220 dev_info(psp->adev->dev,
1221 "Requesting %d memory partition change through PSP", mode);
1222 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1223 if (ret)
1224 dev_err(psp->adev->dev,
1225 "PSP request failed to change to NPS%d mode\n", mode);
1226
1227 release_psp_cmd_buf(psp);
1228
1229 return ret;
1230}
1231
1232int psp_set_mmhub_eco_sec_level(struct amdgpu_device *adev)
1233{
1234 int ret;
1235 struct psp_context *psp = &adev->psp;
1236 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1237
1238 cmd->cmd_id = GFX_CMD_ID_SET_MMHUB_ECO_SEC_LEVEL;
1239
1240 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1241 if (ret) {
1242 dev_err(psp->adev->dev,
1243 "PSP request failed to set mmuhub eco sec level with ret=%d\n", ret);
1244 release_psp_cmd_buf(psp);
1245 return ret;
1246 }
1247
1248 if (cmd->resp.status) {
1249 dev_err(psp->adev->dev,
1250 "MMHUB ECO SEC LEVEL command 0x%x failed, PSP response status: 0x%X\n",
1251 cmd->cmd_id, cmd->resp.status);
1252 ret = -EIO;
1253 }
1254 release_psp_cmd_buf(psp);
1255
1256 return ret;
1257}
1258
1259static int psp_ptl_fmt_verify(struct psp_context *psp, enum amdgpu_ptl_fmt fmt,
1260 uint32_t *ptl_fmt)
1261{
1262 struct amdgpu_device *adev = psp->adev;
1263
1264 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4))
1265 return -EINVAL;
1266
1267 switch (fmt) {
1268 case AMDGPU_PTL_FMT_I8:
1269 *ptl_fmt = GFX_FTYPE_I8;
1270 break;
1271 case AMDGPU_PTL_FMT_F16:
1272 *ptl_fmt = GFX_FTYPE_F16;
1273 break;
1274 case AMDGPU_PTL_FMT_BF16:
1275 *ptl_fmt = GFX_FTYPE_BF16;
1276 break;
1277 case AMDGPU_PTL_FMT_F32:
1278 *ptl_fmt = GFX_FTYPE_F32;
1279 break;
1280 case AMDGPU_PTL_FMT_F64:
1281 *ptl_fmt = GFX_FTYPE_F64;
1282 break;
1283 case AMDGPU_PTL_FMT_F8:
1284 *ptl_fmt = GFX_FTYPE_F8;
1285 break;
1286 case AMDGPU_PTL_FMT_VECTOR:
1287 *ptl_fmt = GFX_FTYPE_VECTOR;
1288 break;
1289 default:
1290 return -EINVAL;
1291 }
1292
1293 return 0;
1294}
1295
1296static int psp_ptl_invoke(struct psp_context *psp, u32 req_code,
1297 uint32_t *ptl_state, uint32_t *fmt1, uint32_t *fmt2)
1298{
1299 struct psp_gfx_cmd_resp *cmd;
1300 struct amdgpu_ptl *ptl = &psp->ptl;
1301 struct amdgpu_device *adev = psp->adev;
1302 int ret;
1303
1304 if (amdgpu_sriov_vf(adev)) {
1305 ret = amdgpu_virt_ptl_request(adev, req_code, ptl_state, fmt1, fmt2);
1306 if (!ret) {
1307 ptl->enabled = *ptl_state;
1308 ptl->fmt1 = *fmt1;
1309 ptl->fmt2 = *fmt2;
1310 }
1311 return ret;
1312 }
1313
1314 cmd = acquire_psp_cmd_buf(psp);
1315
1316 cmd->cmd_id = GFX_CMD_ID_PERF_HW;
1317 cmd->cmd.cmd_req_perf_hw.req = req_code;
1318 cmd->cmd.cmd_req_perf_hw.ptl_state = *ptl_state;
1319 cmd->cmd.cmd_req_perf_hw.pref_format1 = *fmt1;
1320 cmd->cmd.cmd_req_perf_hw.pref_format2 = *fmt2;
1321
1322 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1323 if (ret)
1324 goto out;
1325
1326 /*
1327 * Check response status explicitly to avoid
1328 * updating cached PTL state with invalid data.
1329 */
1330 if (cmd->resp.status) {
1331 dev_err(psp->adev->dev,
1332 "PTL command 0x%x failed, PSP response status: 0x%X fw resp=0x%X\n",
1333 req_code, cmd->resp.status,
1334 cmd->resp.uresp.perf_hw_info.resp);
1335 ret = -EIO;
1336 goto out;
1337 }
1338
1339 /* Parse response */
1340 switch (req_code) {
1341 case PSP_PTL_PERF_MON_QUERY:
1342 *ptl_state = cmd->resp.uresp.perf_hw_info.ptl_state;
1343 *fmt1 = cmd->resp.uresp.perf_hw_info.pref_format1;
1344 *fmt2 = cmd->resp.uresp.perf_hw_info.pref_format2;
1345 dev_dbg(psp->adev->dev, "PTL query: state=%d, fmt1=%d, fmt2=%d\n",
1346 *ptl_state, *fmt1, *fmt2);
1347 break;
1348 case PSP_PTL_PERF_MON_SET:
1349 /* Update cached state only on success */
1350 ptl->enabled = *ptl_state;
1351 ptl->fmt1 = *fmt1;
1352 ptl->fmt2 = *fmt2;
1353 dev_dbg(psp->adev->dev, "PTL set: state=%d, fmt1=%d, fmt2=%d\n",
1354 *ptl_state, *fmt1, *fmt2);
1355 break;
1356 }
1357
1358out:
1359 release_psp_cmd_buf(psp);
1360 return ret;
1361}
1362
1363int amdgpu_ptl_perf_monitor_ctrl(struct amdgpu_device *adev, u32 req_code,
1364 uint32_t *ptl_state,
1365 enum amdgpu_ptl_fmt *fmt1,
1366 enum amdgpu_ptl_fmt *fmt2)
1367{
1368 uint32_t ptl_fmt1, ptl_fmt2;
1369 struct psp_context *psp;
1370 struct amdgpu_ptl *ptl;
1371 int ret;
1372
1373 if (!adev || !ptl_state || !fmt1 || !fmt2)
1374 return -EINVAL;
1375
1376 psp = &adev->psp;
1377 ptl = &psp->ptl;
1378
1379 if (ptl->permanently_disabled && *ptl_state == 1)
1380 return 0;
1381
1382 if (amdgpu_sriov_vf(adev)) {
1383 ptl_fmt1 = *fmt1;
1384 ptl_fmt2 = *fmt2;
1385 return psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2);
1386 }
1387
1388 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4) ||
1389 psp->sos.fw_version < 0x0036081a)
1390 return -EOPNOTSUPP;
1391
1392 /* Verify formats */
1393 if (psp_ptl_fmt_verify(psp, *fmt1, &ptl_fmt1) ||
1394 psp_ptl_fmt_verify(psp, *fmt2, &ptl_fmt2))
1395 return -EINVAL;
1396
1397 /*
1398 * Add check to skip if state and formats are identical to current ones
1399 */
1400 if (req_code == PSP_PTL_PERF_MON_SET &&
1401 ptl->enabled == *ptl_state &&
1402 ptl->fmt1 == ptl_fmt1 &&
1403 ptl->fmt2 == ptl_fmt2)
1404 return 0;
1405
1406 /* If enabling PTL, check disable bitmap */
1407 if (req_code == PSP_PTL_PERF_MON_SET && *ptl_state == 1) {
1408 if (!bitmap_empty(ptl->disable_bitmap,
1409 AMDGPU_PTL_DISABLE_MAX)) {
1410 dev_dbg(adev->dev,
1411 "PTL enable blocked: SYSFS=%d, PROFILER=%d (ref=%d)\n",
1412 test_bit(AMDGPU_PTL_DISABLE_SYSFS,
1413 ptl->disable_bitmap),
1414 test_bit(AMDGPU_PTL_DISABLE_PROFILER,
1415 ptl->disable_bitmap),
1416 atomic_read(&ptl->disable_ref));
1417 return 0;
1418 }
1419 }
1420
1421 if (req_code == PSP_PTL_PERF_MON_SET) {
1422 amdgpu_amdkfd_stop_sched_all(adev);
1423 /* Wait for GFX engine idle before PTL state transition */
1424 ret = amdgpu_device_ip_wait_for_idle(adev,
1425 AMD_IP_BLOCK_TYPE_GFX);
1426 if (ret) {
1427 amdgpu_amdkfd_start_sched_all(adev);
1428 dev_err(adev->dev, "GFX not idle before PTL operation (%d)\n", ret);
1429 return ret;
1430 }
1431 ret = psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2);
1432 amdgpu_amdkfd_start_sched_all(adev);
1433 } else {
1434 ret = psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2);
1435 }
1436
1437 return ret;
1438}
1439
1440static enum amdgpu_ptl_fmt str_to_ptl_fmt(const char *str)
1441{
1442 int i;
1443
1444 for (i = 0; i < AMDGPU_PTL_FMT_INVALID; ++i) {
1445 if (!strcmp(str, amdgpu_ptl_fmt_str[i]))
1446 return (enum amdgpu_ptl_fmt)i;
1447 }
1448
1449 return AMDGPU_PTL_FMT_INVALID;
1450}
1451
1452static ssize_t ptl_supported_formats_show(struct device *dev,
1453 struct device_attribute *attr, char *buf)
1454{
1455 ssize_t len = 0;
1456
1457 for (int i = 0; i < AMDGPU_PTL_FMT_INVALID; ++i) {
1458 const char *fmt = amdgpu_ptl_fmt_str[i];
1459
1460 len += sysfs_emit_at(buf, len, "%s%s",
1461 fmt ? fmt : "UNKNOWN",
1462 (i < AMDGPU_PTL_FMT_INVALID - 1) ? "," : "\n");
1463 }
1464
1465 return len;
1466}
1467
1468static ssize_t ptl_enable_store(struct device *dev,
1469 struct device_attribute *attr,
1470 const char *buf, size_t count)
1471{
1472 struct drm_device *ddev = dev_get_drvdata(dev);
1473 struct amdgpu_device *adev = drm_to_adev(ddev);
1474 struct amdgpu_ptl *ptl = &adev->psp.ptl;
1475 uint32_t ptl_state, fmt1, fmt2;
1476 int ret;
1477 bool enable;
1478 bool bit_changed = false;
1479
1480 mutex_lock(&ptl->mutex);
1481 if (sysfs_streq(buf, "enabled") || sysfs_streq(buf, "1")) {
1482 enable = true;
1483 } else if (sysfs_streq(buf, "disabled") || sysfs_streq(buf, "0")) {
1484 enable = false;
1485 } else {
1486 mutex_unlock(&ptl->mutex);
1487 return -EINVAL;
1488 }
1489
1490 /* Block enable when permanently disabled */
1491 if (ptl->permanently_disabled) {
1492 mutex_unlock(&ptl->mutex);
1493 return -EPERM;
1494 }
1495
1496 fmt1 = ptl->fmt1;
1497 fmt2 = ptl->fmt2;
1498 ptl_state = enable ? 1 : 0;
1499
1500 if (enable)
1501 bit_changed = test_and_clear_bit(AMDGPU_PTL_DISABLE_SYSFS,
1502 ptl->disable_bitmap);
1503
1504 ret = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, &fmt1, &fmt2);
1505 if (ret) {
1506 dev_err(adev->dev, "Failed to set PTL err = %d\n", ret);
1507 if (enable && bit_changed)
1508 set_bit(AMDGPU_PTL_DISABLE_SYSFS, ptl->disable_bitmap);
1509 mutex_unlock(&ptl->mutex);
1510 return ret;
1511 }
1512
1513 if (!enable)
1514 set_bit(AMDGPU_PTL_DISABLE_SYSFS, ptl->disable_bitmap);
1515
1516 mutex_unlock(&ptl->mutex);
1517
1518 return count;
1519}
1520
1521static ssize_t ptl_enable_show(struct device *dev, struct device_attribute *attr, char *buf)
1522{
1523 struct drm_device *ddev = dev_get_drvdata(dev);
1524 struct amdgpu_device *adev = drm_to_adev(ddev);
1525 struct amdgpu_ptl *ptl = &adev->psp.ptl;
1526 uint32_t ptl_state, fmt1, fmt2;
1527 int ret;
1528
1529 if (amdgpu_sriov_vf(adev)) {
1530 ptl_state = ptl->enabled;
1531 fmt1 = ptl->fmt1;
1532 fmt2 = ptl->fmt2;
1533 ret = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_QUERY,
1534 &ptl_state, &fmt1, &fmt2);
1535 if (ret)
1536 return ret;
1537 }
1538
1539 if (ptl->permanently_disabled)
1540 return sysfs_emit(buf, "permanently disabled\n");
1541
1542 return sysfs_emit(buf, "%s\n", ptl->enabled ? "enabled" : "disabled");
1543}
1544
1545static ssize_t ptl_format_store(struct device *dev,
1546 struct device_attribute *attr,
1547 const char *buf, size_t count)
1548{
1549 struct drm_device *ddev = dev_get_drvdata(dev);
1550 struct amdgpu_device *adev = drm_to_adev(ddev);
1551 char fmt1_str[8], fmt2_str[8];
1552 enum amdgpu_ptl_fmt fmt1_enum, fmt2_enum;
1553 struct amdgpu_ptl *ptl = &adev->psp.ptl;
1554 uint32_t ptl_state, fmt1, fmt2;
1555 int ret;
1556
1557 /* Only allow format update when PTL is enabled */
1558 if (!ptl->enabled)
1559 return -EPERM;
1560
1561 mutex_lock(&ptl->mutex);
1562 /* Parse input, expecting "FMT1,FMT2" */
1563 if (sscanf(buf, "%7[^,],%7s", fmt1_str, fmt2_str) != 2) {
1564 mutex_unlock(&ptl->mutex);
1565 return -EINVAL;
1566 }
1567
1568 fmt1_enum = str_to_ptl_fmt(fmt1_str);
1569 fmt2_enum = str_to_ptl_fmt(fmt2_str);
1570
1571 if (fmt1_enum >= AMDGPU_PTL_FMT_INVALID ||
1572 fmt2_enum >= AMDGPU_PTL_FMT_INVALID ||
1573 fmt1_enum == fmt2_enum) {
1574 mutex_unlock(&ptl->mutex);
1575 return -EINVAL;
1576 }
1577
1578 ptl_state = ptl->enabled;
1579 fmt1 = fmt1_enum;
1580 fmt2 = fmt2_enum;
1581 ret = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, &fmt1, &fmt2);
1582 if (ret) {
1583 dev_err(adev->dev, "Failed to update PTL err = %d\n", ret);
1584 mutex_unlock(&ptl->mutex);
1585 return ret;
1586 }
1587 mutex_unlock(&ptl->mutex);
1588
1589 return count;
1590}
1591
1592static ssize_t ptl_format_show(struct device *dev, struct device_attribute *attr, char *buf)
1593{
1594 struct drm_device *ddev = dev_get_drvdata(dev);
1595 struct amdgpu_device *adev = drm_to_adev(ddev);
1596 struct amdgpu_ptl *ptl = &adev->psp.ptl;
1597 uint32_t ptl_state, fmt1, fmt2;
1598 int ret;
1599
1600 if (amdgpu_sriov_vf(adev)) {
1601 ptl_state = ptl->enabled;
1602 fmt1 = ptl->fmt1;
1603 fmt2 = ptl->fmt2;
1604 ret = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_QUERY,
1605 &ptl_state, &fmt1, &fmt2);
1606 if (ret)
1607 return ret;
1608 }
1609
1610 return sysfs_emit(buf, "%s,%s\n",
1611 amdgpu_ptl_fmt_str[ptl->fmt1],
1612 amdgpu_ptl_fmt_str[ptl->fmt2]);
1613}
1614
1615static umode_t amdgpu_ptl_is_visible(struct kobject *kobj, struct attribute *attr, int idx)
1616{
1617 struct device *dev = kobj_to_dev(kobj);
1618 struct drm_device *ddev = dev_get_drvdata(dev);
1619 struct amdgpu_device *adev = drm_to_adev(ddev);
1620
1621 /* Only show PTL sysfs files if PTL hardware is supported */
1622 if (adev->psp.ptl.hw_supported_state != AMDGPU_PTL_HW_SUPPORTED)
1623 return 0;
1624
1625 return attr->mode;
1626}
1627
1628int amdgpu_ptl_sysfs_init(struct amdgpu_device *adev)
1629{
1630 struct amdgpu_ptl *ptl = &adev->psp.ptl;
1631 int ret;
1632
1633 if (ptl->hw_supported_state != AMDGPU_PTL_HW_SUPPORTED)
1634 return 0;
1635
1636 if (ptl->ptl_sysfs_created)
1637 return 0;
1638
1639 ret = sysfs_create_group(&adev->dev->kobj, &amdgpu_ptl_attr_group);
1640 if (!ret)
1641 ptl->ptl_sysfs_created = true;
1642
1643 return ret;
1644}
1645
1646void amdgpu_ptl_sysfs_fini(struct amdgpu_device *adev)
1647{
1648 struct amdgpu_ptl *ptl = &adev->psp.ptl;
1649
1650 if (ptl->hw_supported_state != AMDGPU_PTL_HW_SUPPORTED)
1651 return;
1652
1653 if (!ptl->ptl_sysfs_created)
1654 return;
1655
1656 sysfs_remove_group(&adev->dev->kobj, &amdgpu_ptl_attr_group);
1657 ptl->ptl_sysfs_created = false;
1658}
1659
1660int psp_spatial_partition(struct psp_context *psp, int mode)
1661{
1662 struct psp_gfx_cmd_resp *cmd;
1663 int ret;
1664
1665 if (amdgpu_sriov_vf(psp->adev))
1666 return 0;
1667
1668 cmd = acquire_psp_cmd_buf(psp);
1669
1670 cmd->cmd_id = GFX_CMD_ID_SRIOV_SPATIAL_PART;
1671 cmd->cmd.cmd_spatial_part.mode = mode;
1672
1673 dev_info(psp->adev->dev, "Requesting %d partitions through PSP", mode);
1674 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1675
1676 release_psp_cmd_buf(psp);
1677
1678 return ret;
1679}
1680
1681static int psp_asd_initialize(struct psp_context *psp)
1682{
1683 int ret;
1684
1685 /* If PSP version doesn't match ASD version, asd loading will be failed.
1686 * add workaround to bypass it for sriov now.
1687 * TODO: add version check to make it common
1688 */
1689 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes)
1690 return 0;
1691
1692 /* bypass asd if display hardware is not available */
1693 if (!amdgpu_device_has_display_hardware(psp->adev) &&
1694 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= IP_VERSION(13, 0, 10))
1695 return 0;
1696
1697 psp->asd_context.mem_context.shared_mc_addr = 0;
1698 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE;
1699 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD;
1700
1701 ret = psp_ta_load(psp, &psp->asd_context);
1702 if (!ret)
1703 psp->asd_context.initialized = true;
1704
1705 return ret;
1706}
1707
1708static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1709 uint32_t session_id)
1710{
1711 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
1712 cmd->cmd.cmd_unload_ta.session_id = session_id;
1713}
1714
1715int psp_ta_unload(struct psp_context *psp, struct ta_context *context)
1716{
1717 int ret;
1718 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1719
1720 psp_prep_ta_unload_cmd_buf(cmd, context->session_id);
1721
1722 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1723
1724 context->resp_status = cmd->resp.status;
1725
1726 release_psp_cmd_buf(psp);
1727
1728 return ret;
1729}
1730
1731static int psp_asd_terminate(struct psp_context *psp)
1732{
1733 int ret;
1734
1735 if (amdgpu_sriov_vf(psp->adev))
1736 return 0;
1737
1738 if (!psp->asd_context.initialized)
1739 return 0;
1740
1741 ret = psp_ta_unload(psp, &psp->asd_context);
1742 if (!ret)
1743 psp->asd_context.initialized = false;
1744
1745 return ret;
1746}
1747
1748static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1749 uint32_t id, uint32_t value)
1750{
1751 cmd->cmd_id = GFX_CMD_ID_PROG_REG;
1752 cmd->cmd.cmd_setup_reg_prog.reg_value = value;
1753 cmd->cmd.cmd_setup_reg_prog.reg_id = id;
1754}
1755
1756int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
1757 uint32_t value)
1758{
1759 struct psp_gfx_cmd_resp *cmd;
1760 int ret = 0;
1761
1762 if (reg >= PSP_REG_LAST)
1763 return -EINVAL;
1764
1765 cmd = acquire_psp_cmd_buf(psp);
1766
1767 psp_prep_reg_prog_cmd_buf(cmd, reg, value);
1768 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1769 if (ret)
1770 dev_err(psp->adev->dev, "PSP failed to program reg id %d\n", reg);
1771
1772 release_psp_cmd_buf(psp);
1773
1774 return ret;
1775}
1776
1777static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1778 uint64_t ta_bin_mc,
1779 struct ta_context *context)
1780{
1781 cmd->cmd_id = context->ta_load_type;
1782 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc);
1783 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc);
1784 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes;
1785
1786 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo =
1787 lower_32_bits(context->mem_context.shared_mc_addr);
1788 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi =
1789 upper_32_bits(context->mem_context.shared_mc_addr);
1790 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size;
1791}
1792
1793int psp_ta_init_shared_buf(struct psp_context *psp,
1794 struct ta_mem_context *mem_ctx)
1795{
1796 /*
1797 * Allocate 16k memory aligned to 4k from Frame Buffer (local
1798 * physical) for ta to host memory
1799 */
1800 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size,
1801 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM |
1802 AMDGPU_GEM_DOMAIN_GTT,
1803 &mem_ctx->shared_bo,
1804 &mem_ctx->shared_mc_addr,
1805 &mem_ctx->shared_buf);
1806}
1807
1808static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1809 uint32_t ta_cmd_id,
1810 uint32_t session_id)
1811{
1812 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
1813 cmd->cmd.cmd_invoke_cmd.session_id = session_id;
1814 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
1815}
1816
1817int psp_ta_invoke(struct psp_context *psp,
1818 uint32_t ta_cmd_id,
1819 struct ta_context *context)
1820{
1821 int ret;
1822 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1823
1824 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id);
1825
1826 ret = psp_cmd_submit_buf(psp, NULL, cmd,
1827 psp->fence_buf_mc_addr);
1828
1829 context->resp_status = cmd->resp.status;
1830
1831 release_psp_cmd_buf(psp);
1832
1833 return ret;
1834}
1835
1836int psp_ta_load(struct psp_context *psp, struct ta_context *context)
1837{
1838 int ret;
1839 struct psp_gfx_cmd_resp *cmd;
1840
1841 cmd = acquire_psp_cmd_buf(psp);
1842
1843 ret = psp_copy_fw(psp, context->bin_desc.start_addr,
1844 context->bin_desc.size_bytes);
1845 if (ret) {
1846 release_psp_cmd_buf(psp);
1847 return ret;
1848 }
1849
1850 if (amdgpu_virt_xgmi_migrate_enabled(psp->adev) &&
1851 context->mem_context.shared_bo)
1852 context->mem_context.shared_mc_addr =
1853 amdgpu_bo_fb_aper_addr(context->mem_context.shared_bo);
1854
1855 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context);
1856
1857 ret = psp_cmd_submit_buf(psp, NULL, cmd,
1858 psp->fence_buf_mc_addr);
1859
1860 context->resp_status = cmd->resp.status;
1861
1862 if (!ret)
1863 context->session_id = cmd->resp.session_id;
1864
1865 release_psp_cmd_buf(psp);
1866
1867 return ret;
1868}
1869
1870int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1871{
1872 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context);
1873}
1874
1875int psp_xgmi_terminate(struct psp_context *psp)
1876{
1877 int ret;
1878 struct amdgpu_device *adev = psp->adev;
1879
1880 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
1881 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) ||
1882 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) &&
1883 adev->gmc.xgmi.connected_to_cpu))
1884 return 0;
1885
1886 if (!psp->xgmi_context.context.initialized)
1887 return 0;
1888
1889 ret = psp_ta_unload(psp, &psp->xgmi_context.context);
1890
1891 psp->xgmi_context.context.initialized = false;
1892
1893 return ret;
1894}
1895
1896int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta)
1897{
1898 struct ta_xgmi_shared_memory *xgmi_cmd;
1899 int ret;
1900
1901 if (!psp->ta_fw ||
1902 !psp->xgmi_context.context.bin_desc.size_bytes ||
1903 !psp->xgmi_context.context.bin_desc.start_addr)
1904 return -ENOENT;
1905
1906 if (!load_ta)
1907 goto invoke;
1908
1909 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE;
1910 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1911
1912 if (!psp->xgmi_context.context.mem_context.shared_buf) {
1913 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context);
1914 if (ret)
1915 return ret;
1916 }
1917
1918 /* Load XGMI TA */
1919 ret = psp_ta_load(psp, &psp->xgmi_context.context);
1920 if (!ret)
1921 psp->xgmi_context.context.initialized = true;
1922 else
1923 return ret;
1924
1925invoke:
1926 /* Initialize XGMI session */
1927 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf);
1928 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1929 xgmi_cmd->flag_extend_link_record = set_extended_data;
1930 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
1931
1932 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1933 /* note down the capbility flag for XGMI TA */
1934 psp->xgmi_context.xgmi_ta_caps = xgmi_cmd->caps_flag;
1935
1936 if (!amdgpu_sriov_vf(psp->adev))
1937 psp->xgmi_context.supports_ext_link_info = psp->xgmi_context.xgmi_ta_caps &
1938 EXTEND_PEER_LINK_INFO_CMD_FLAG;
1939 else
1940 psp->xgmi_context.supports_ext_link_info = amdgpu_sriov_xgmi_ta_ext_peer_link_en(psp->adev);
1941
1942 return ret;
1943}
1944
1945int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
1946{
1947 struct ta_xgmi_shared_memory *xgmi_cmd;
1948 int ret;
1949
1950 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1951 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1952
1953 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
1954
1955 /* Invoke xgmi ta to get hive id */
1956 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1957 if (ret)
1958 return ret;
1959
1960 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
1961
1962 return 0;
1963}
1964
1965int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
1966{
1967 struct ta_xgmi_shared_memory *xgmi_cmd;
1968 int ret;
1969
1970 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1971 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1972
1973 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
1974
1975 /* Invoke xgmi ta to get the node id */
1976 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1977 if (ret)
1978 return ret;
1979
1980 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
1981
1982 return 0;
1983}
1984
1985static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp)
1986{
1987 return (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) ==
1988 IP_VERSION(13, 0, 2) &&
1989 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b) ||
1990 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >=
1991 IP_VERSION(13, 0, 6);
1992}
1993
1994/*
1995 * Chips that support extended topology information require the driver to
1996 * reflect topology information in the opposite direction. This is
1997 * because the TA has already exceeded its link record limit and if the
1998 * TA holds bi-directional information, the driver would have to do
1999 * multiple fetches instead of just two.
2000 */
2001static void psp_xgmi_reflect_topology_info(struct psp_context *psp,
2002 struct psp_xgmi_node_info node_info)
2003{
2004 struct amdgpu_device *mirror_adev;
2005 struct amdgpu_hive_info *hive;
2006 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id;
2007 uint64_t dst_node_id = node_info.node_id;
2008 uint8_t dst_num_hops = node_info.num_hops;
2009 uint8_t dst_is_sharing_enabled = node_info.is_sharing_enabled;
2010 uint8_t dst_num_links = node_info.num_links;
2011
2012 hive = amdgpu_get_xgmi_hive(psp->adev);
2013 if (WARN_ON(!hive))
2014 return;
2015
2016 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) {
2017 struct psp_xgmi_topology_info *mirror_top_info;
2018 int j;
2019
2020 if (mirror_adev->gmc.xgmi.node_id != dst_node_id)
2021 continue;
2022
2023 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info;
2024 for (j = 0; j < mirror_top_info->num_nodes; j++) {
2025 if (mirror_top_info->nodes[j].node_id != src_node_id)
2026 continue;
2027
2028 mirror_top_info->nodes[j].num_hops = dst_num_hops;
2029 mirror_top_info->nodes[j].is_sharing_enabled = dst_is_sharing_enabled;
2030 /* prevent 0 num_links value re-reflection since reflection
2031 * criteria is based on num_hops (direct or indirect).
2032 */
2033 if (dst_num_links) {
2034 mirror_top_info->nodes[j].num_links = dst_num_links;
2035 /* swap src and dst due to frame of reference */
2036 for (int k = 0; k < dst_num_links; k++) {
2037 mirror_top_info->nodes[j].port_num[k].src_xgmi_port_num =
2038 node_info.port_num[k].dst_xgmi_port_num;
2039 mirror_top_info->nodes[j].port_num[k].dst_xgmi_port_num =
2040 node_info.port_num[k].src_xgmi_port_num;
2041 }
2042 }
2043
2044 break;
2045 }
2046
2047 break;
2048 }
2049
2050 amdgpu_put_xgmi_hive(hive);
2051}
2052
2053int psp_xgmi_get_topology_info(struct psp_context *psp,
2054 int number_devices,
2055 struct psp_xgmi_topology_info *topology,
2056 bool get_extended_data)
2057{
2058 struct ta_xgmi_shared_memory *xgmi_cmd;
2059 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
2060 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
2061 int i;
2062 int ret;
2063
2064 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
2065 return -EINVAL;
2066
2067 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
2068 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
2069 xgmi_cmd->flag_extend_link_record = get_extended_data;
2070
2071 /* Fill in the shared memory with topology information as input */
2072 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
2073 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_TOPOLOGY_INFO;
2074 topology_info_input->num_nodes = number_devices;
2075
2076 for (i = 0; i < topology_info_input->num_nodes; i++) {
2077 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
2078 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
2079 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
2080 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
2081 }
2082
2083 /* Invoke xgmi ta to get the topology information */
2084 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_TOPOLOGY_INFO);
2085 if (ret)
2086 return ret;
2087
2088 /* Read the output topology information from the shared memory */
2089 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
2090 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
2091 for (i = 0; i < topology->num_nodes; i++) {
2092 /* extended data will either be 0 or equal to non-extended data */
2093 if (topology_info_output->nodes[i].num_hops)
2094 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
2095
2096 /* non-extended data gets everything here so no need to update */
2097 if (!get_extended_data) {
2098 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
2099 topology->nodes[i].is_sharing_enabled =
2100 topology_info_output->nodes[i].is_sharing_enabled;
2101 topology->nodes[i].sdma_engine =
2102 topology_info_output->nodes[i].sdma_engine;
2103 }
2104
2105 }
2106
2107 /* Invoke xgmi ta again to get the link information */
2108 if (psp_xgmi_peer_link_info_supported(psp)) {
2109 struct ta_xgmi_cmd_get_peer_link_info *link_info_output;
2110 struct ta_xgmi_cmd_get_extend_peer_link_info *link_extend_info_output;
2111 bool requires_reflection =
2112 (psp->xgmi_context.supports_extended_data &&
2113 get_extended_data) ||
2114 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) ==
2115 IP_VERSION(13, 0, 6) ||
2116 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) ==
2117 IP_VERSION(13, 0, 14) ||
2118 amdgpu_sriov_vf(psp->adev);
2119
2120 /* popluate the shared output buffer rather than the cmd input buffer
2121 * with node_ids as the input for GET_PEER_LINKS command execution.
2122 * This is required for GET_PEER_LINKS per xgmi ta implementation.
2123 * The same requirement for GET_EXTEND_PEER_LINKS command.
2124 */
2125 if (psp->xgmi_context.supports_ext_link_info) {
2126 link_extend_info_output = &xgmi_cmd->xgmi_out_message.get_extend_link_info;
2127
2128 for (i = 0; i < topology->num_nodes; i++)
2129 link_extend_info_output->nodes[i].node_id = topology->nodes[i].node_id;
2130
2131 link_extend_info_output->num_nodes = topology->num_nodes;
2132 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_EXTEND_PEER_LINKS;
2133 } else {
2134 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info;
2135
2136 for (i = 0; i < topology->num_nodes; i++)
2137 link_info_output->nodes[i].node_id = topology->nodes[i].node_id;
2138
2139 link_info_output->num_nodes = topology->num_nodes;
2140 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS;
2141 }
2142
2143 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
2144 if (ret)
2145 return ret;
2146
2147 for (i = 0; i < topology->num_nodes; i++) {
2148 uint8_t node_num_links = psp->xgmi_context.supports_ext_link_info ?
2149 link_extend_info_output->nodes[i].num_links : link_info_output->nodes[i].num_links;
2150 /* accumulate num_links on extended data */
2151 if (get_extended_data) {
2152 topology->nodes[i].num_links = topology->nodes[i].num_links + node_num_links;
2153 } else {
2154 topology->nodes[i].num_links = (requires_reflection && topology->nodes[i].num_links) ?
2155 topology->nodes[i].num_links : node_num_links;
2156 }
2157 /* popluate the connected port num info if supported and available */
2158 if (psp->xgmi_context.supports_ext_link_info && topology->nodes[i].num_links) {
2159 memcpy(topology->nodes[i].port_num, link_extend_info_output->nodes[i].port_num,
2160 sizeof(struct xgmi_connected_port_num) * TA_XGMI__MAX_PORT_NUM);
2161 }
2162
2163 /* reflect the topology information for bi-directionality */
2164 if (requires_reflection && topology->nodes[i].num_hops)
2165 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]);
2166 }
2167 }
2168
2169 return 0;
2170}
2171
2172int psp_xgmi_set_topology_info(struct psp_context *psp,
2173 int number_devices,
2174 struct psp_xgmi_topology_info *topology)
2175{
2176 struct ta_xgmi_shared_memory *xgmi_cmd;
2177 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
2178 int i;
2179
2180 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
2181 return -EINVAL;
2182
2183 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
2184 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
2185
2186 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
2187 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
2188 topology_info_input->num_nodes = number_devices;
2189
2190 for (i = 0; i < topology_info_input->num_nodes; i++) {
2191 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
2192 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
2193 topology_info_input->nodes[i].is_sharing_enabled = 1;
2194 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
2195 }
2196
2197 /* Invoke xgmi ta to set topology information */
2198 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
2199}
2200
2201// ras begin
2202static void psp_ras_ta_check_status(struct psp_context *psp)
2203{
2204 struct ta_ras_shared_memory *ras_cmd =
2205 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
2206
2207 switch (ras_cmd->ras_status) {
2208 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP:
2209 dev_warn(psp->adev->dev,
2210 "RAS WARNING: cmd failed due to unsupported ip\n");
2211 break;
2212 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ:
2213 dev_warn(psp->adev->dev,
2214 "RAS WARNING: cmd failed due to unsupported error injection\n");
2215 break;
2216 case TA_RAS_STATUS__SUCCESS:
2217 break;
2218 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED:
2219 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR)
2220 dev_warn(psp->adev->dev,
2221 "RAS WARNING: Inject error to critical region is not allowed\n");
2222 break;
2223 default:
2224 dev_warn(psp->adev->dev,
2225 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status);
2226 break;
2227 }
2228}
2229
2230static int psp_ras_send_cmd(struct psp_context *psp,
2231 enum ras_command cmd_id, void *in, void *out)
2232{
2233 struct ta_ras_shared_memory *ras_cmd;
2234 uint32_t cmd = cmd_id;
2235 int ret = 0;
2236
2237 if (!in)
2238 return -EINVAL;
2239
2240 mutex_lock(&psp->ras_context.mutex);
2241 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
2242 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
2243
2244 switch (cmd) {
2245 case TA_RAS_COMMAND__ENABLE_FEATURES:
2246 case TA_RAS_COMMAND__DISABLE_FEATURES:
2247 memcpy(&ras_cmd->ras_in_message,
2248 in, sizeof(ras_cmd->ras_in_message));
2249 break;
2250 case TA_RAS_COMMAND__TRIGGER_ERROR:
2251 memcpy(&ras_cmd->ras_in_message.trigger_error,
2252 in, sizeof(ras_cmd->ras_in_message.trigger_error));
2253 break;
2254 case TA_RAS_COMMAND__QUERY_ADDRESS:
2255 memcpy(&ras_cmd->ras_in_message.address,
2256 in, sizeof(ras_cmd->ras_in_message.address));
2257 break;
2258 default:
2259 dev_err(psp->adev->dev, "Invalid ras cmd id: %u\n", cmd);
2260 ret = -EINVAL;
2261 goto err_out;
2262 }
2263
2264 ras_cmd->cmd_id = cmd;
2265 ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
2266
2267 switch (cmd) {
2268 case TA_RAS_COMMAND__TRIGGER_ERROR:
2269 if (!ret && out)
2270 memcpy(out, &ras_cmd->ras_status, sizeof(ras_cmd->ras_status));
2271 break;
2272 case TA_RAS_COMMAND__QUERY_ADDRESS:
2273 if (ret || ras_cmd->ras_status || psp->cmd_buf_mem->resp.status)
2274 ret = -EINVAL;
2275 else if (out)
2276 memcpy(out,
2277 &ras_cmd->ras_out_message.address,
2278 sizeof(ras_cmd->ras_out_message.address));
2279 break;
2280 default:
2281 break;
2282 }
2283
2284err_out:
2285 mutex_unlock(&psp->ras_context.mutex);
2286
2287 return ret;
2288}
2289
2290int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
2291{
2292 struct ta_ras_shared_memory *ras_cmd;
2293 int ret;
2294
2295 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
2296
2297 /*
2298 * TODO: bypass the loading in sriov for now
2299 */
2300 if (amdgpu_sriov_vf(psp->adev))
2301 return 0;
2302
2303 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context);
2304
2305 if (amdgpu_ras_intr_triggered())
2306 return ret;
2307
2308 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) {
2309 dev_warn(psp->adev->dev, "RAS: Unsupported Interface\n");
2310 return -EINVAL;
2311 }
2312
2313 if (!ret) {
2314 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) {
2315 dev_warn(psp->adev->dev, "ECC switch disabled\n");
2316
2317 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE;
2318 } else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag)
2319 dev_warn(psp->adev->dev,
2320 "RAS internal register access blocked\n");
2321
2322 psp_ras_ta_check_status(psp);
2323 }
2324
2325 return ret;
2326}
2327
2328int psp_ras_enable_features(struct psp_context *psp,
2329 union ta_ras_cmd_input *info, bool enable)
2330{
2331 enum ras_command cmd_id;
2332 int ret;
2333
2334 if (!psp->ras_context.context.initialized || !info)
2335 return -EINVAL;
2336
2337 cmd_id = enable ?
2338 TA_RAS_COMMAND__ENABLE_FEATURES : TA_RAS_COMMAND__DISABLE_FEATURES;
2339 ret = psp_ras_send_cmd(psp, cmd_id, info, NULL);
2340 if (ret)
2341 return -EINVAL;
2342
2343 return 0;
2344}
2345
2346int psp_ras_terminate(struct psp_context *psp)
2347{
2348 int ret;
2349
2350 /*
2351 * TODO: bypass the terminate in sriov for now
2352 */
2353 if (amdgpu_sriov_vf(psp->adev))
2354 return 0;
2355
2356 if (!psp->ras_context.context.initialized)
2357 return 0;
2358
2359 ret = psp_ta_unload(psp, &psp->ras_context.context);
2360
2361 psp->ras_context.context.initialized = false;
2362
2363 mutex_destroy(&psp->ras_context.mutex);
2364
2365 return ret;
2366}
2367
2368int psp_ras_initialize(struct psp_context *psp)
2369{
2370 int ret;
2371 uint32_t boot_cfg = 0xFF;
2372 struct amdgpu_device *adev = psp->adev;
2373 struct ta_ras_shared_memory *ras_cmd;
2374
2375 /*
2376 * TODO: bypass the initialize in sriov for now
2377 */
2378 if (amdgpu_sriov_vf(adev))
2379 return 0;
2380
2381 if (!adev->psp.ras_context.context.bin_desc.size_bytes ||
2382 !adev->psp.ras_context.context.bin_desc.start_addr) {
2383 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n");
2384 return 0;
2385 }
2386
2387 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) {
2388 /* query GECC enablement status from boot config
2389 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled
2390 */
2391 ret = psp_boot_config_get(adev, &boot_cfg);
2392 if (ret)
2393 dev_warn(adev->dev, "PSP get boot config failed\n");
2394
2395 if (boot_cfg == 1 && !adev->ras_default_ecc_enabled &&
2396 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) {
2397 dev_warn(adev->dev, "GECC is currently enabled, which may affect performance\n");
2398 dev_warn(adev->dev,
2399 "To disable GECC, please reboot the system and load the amdgpu driver with the parameter amdgpu_ras_enable=0\n");
2400 } else {
2401 if ((adev->ras_default_ecc_enabled || amdgpu_ras_enable == 1) &&
2402 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) {
2403 if (boot_cfg == 1) {
2404 dev_info(adev->dev, "GECC is enabled\n");
2405 } else {
2406 /* enable GECC in next boot cycle if it is disabled
2407 * in boot config, or force enable GECC if failed to
2408 * get boot configuration
2409 */
2410 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC);
2411 if (ret)
2412 dev_warn(adev->dev, "PSP set boot config failed\n");
2413 else
2414 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n");
2415 }
2416 } else {
2417 if (!boot_cfg) {
2418 if (!adev->ras_default_ecc_enabled &&
2419 amdgpu_ras_enable != 1 &&
2420 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC))
2421 dev_warn(adev->dev, "GECC is disabled, set amdgpu_ras_enable=1 to enable GECC in next boot cycle if needed\n");
2422 else
2423 dev_info(adev->dev, "GECC is disabled\n");
2424 } else {
2425 /* disable GECC in next boot cycle if ras is
2426 * disabled by module parameter amdgpu_ras_enable
2427 * and/or amdgpu_ras_mask, or boot_config_get call
2428 * is failed
2429 */
2430 ret = psp_boot_config_set(adev, 0);
2431 if (ret)
2432 dev_warn(adev->dev, "PSP set boot config failed\n");
2433 else
2434 dev_warn(adev->dev, "GECC will be disabled in next boot cycle if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n");
2435 }
2436 }
2437 }
2438 }
2439
2440 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE;
2441 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
2442
2443 if (!psp->ras_context.context.mem_context.shared_buf) {
2444 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context);
2445 if (ret)
2446 return ret;
2447 }
2448
2449 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
2450 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
2451
2452 if (amdgpu_ras_is_poison_mode_supported(adev))
2453 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1;
2454 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu)
2455 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1;
2456 ras_cmd->ras_in_message.init_flags.xcc_mask =
2457 adev->gfx.xcc_mask;
2458 ras_cmd->ras_in_message.init_flags.channel_dis_num = hweight32(adev->gmc.m_half_use) * 2;
2459 if (adev->gmc.gmc_funcs->query_mem_partition_mode)
2460 ras_cmd->ras_in_message.init_flags.nps_mode =
2461 adev->gmc.gmc_funcs->query_mem_partition_mode(adev);
2462 ras_cmd->ras_in_message.init_flags.active_umc_mask = adev->umc.active_mask;
2463 ras_cmd->ras_in_message.init_flags.vram_type = (uint8_t)adev->gmc.vram_type;
2464
2465 ret = psp_ta_load(psp, &psp->ras_context.context);
2466
2467 if (!ret && !ras_cmd->ras_status) {
2468 psp->ras_context.context.initialized = true;
2469 mutex_init(&psp->ras_context.mutex);
2470 } else {
2471 if (ras_cmd->ras_status)
2472 dev_warn(adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status);
2473
2474 /* fail to load RAS TA */
2475 psp->ras_context.context.initialized = false;
2476 }
2477
2478 return ret;
2479}
2480
2481int psp_ras_trigger_error(struct psp_context *psp,
2482 struct ta_ras_trigger_error_input *info, uint32_t instance_mask)
2483{
2484 struct amdgpu_device *adev = psp->adev;
2485 int ret;
2486 uint32_t dev_mask;
2487 uint32_t ras_status = 0;
2488
2489 if (!psp->ras_context.context.initialized || !info)
2490 return -EINVAL;
2491
2492 switch (info->block_id) {
2493 case TA_RAS_BLOCK__GFX:
2494 dev_mask = GET_MASK(GC, instance_mask);
2495 break;
2496 case TA_RAS_BLOCK__SDMA:
2497 dev_mask = GET_MASK(SDMA0, instance_mask);
2498 break;
2499 case TA_RAS_BLOCK__VCN:
2500 case TA_RAS_BLOCK__JPEG:
2501 dev_mask = GET_MASK(VCN, instance_mask);
2502 break;
2503 default:
2504 dev_mask = instance_mask;
2505 break;
2506 }
2507
2508 /* reuse sub_block_index for backward compatibility */
2509 dev_mask <<= AMDGPU_RAS_INST_SHIFT;
2510 dev_mask &= AMDGPU_RAS_INST_MASK;
2511 info->sub_block_index |= dev_mask;
2512
2513 ret = psp_ras_send_cmd(psp,
2514 TA_RAS_COMMAND__TRIGGER_ERROR, info, &ras_status);
2515 if (ret)
2516 return -EINVAL;
2517
2518 /* If err_event_athub occurs error inject was successful, however
2519 * return status from TA is no long reliable
2520 */
2521 if (amdgpu_ras_intr_triggered())
2522 return 0;
2523
2524 if (ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED)
2525 return -EACCES;
2526 else if (ras_status)
2527 return -EINVAL;
2528
2529 return 0;
2530}
2531
2532int psp_ras_query_address(struct psp_context *psp,
2533 struct ta_ras_query_address_input *addr_in,
2534 struct ta_ras_query_address_output *addr_out)
2535{
2536 int ret;
2537
2538 if (!psp->ras_context.context.initialized ||
2539 !addr_in || !addr_out)
2540 return -EINVAL;
2541
2542 ret = psp_ras_send_cmd(psp,
2543 TA_RAS_COMMAND__QUERY_ADDRESS, addr_in, addr_out);
2544
2545 return ret;
2546}
2547// ras end
2548
2549// HDCP start
2550static int psp_hdcp_initialize(struct psp_context *psp)
2551{
2552 int ret;
2553
2554 /*
2555 * TODO: bypass the initialize in sriov for now
2556 */
2557 if (amdgpu_sriov_vf(psp->adev))
2558 return 0;
2559
2560 /* bypass hdcp initialization if dmu is harvested */
2561 if (!amdgpu_device_has_display_hardware(psp->adev))
2562 return 0;
2563
2564 if (!psp->hdcp_context.context.bin_desc.size_bytes ||
2565 !psp->hdcp_context.context.bin_desc.start_addr) {
2566 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");
2567 return 0;
2568 }
2569
2570 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE;
2571 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
2572
2573 if (!psp->hdcp_context.context.mem_context.shared_buf) {
2574 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context);
2575 if (ret)
2576 return ret;
2577 }
2578
2579 ret = psp_ta_load(psp, &psp->hdcp_context.context);
2580 if (!ret) {
2581 psp->hdcp_context.context.initialized = true;
2582 mutex_init(&psp->hdcp_context.mutex);
2583 }
2584
2585 return ret;
2586}
2587
2588int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
2589{
2590 /*
2591 * TODO: bypass the loading in sriov for now
2592 */
2593 if (amdgpu_sriov_vf(psp->adev))
2594 return 0;
2595
2596 if (!psp->hdcp_context.context.initialized)
2597 return 0;
2598
2599 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context);
2600}
2601
2602static int psp_hdcp_terminate(struct psp_context *psp)
2603{
2604 int ret;
2605
2606 /*
2607 * TODO: bypass the terminate in sriov for now
2608 */
2609 if (amdgpu_sriov_vf(psp->adev))
2610 return 0;
2611
2612 if (!psp->hdcp_context.context.initialized)
2613 return 0;
2614
2615 ret = psp_ta_unload(psp, &psp->hdcp_context.context);
2616
2617 psp->hdcp_context.context.initialized = false;
2618
2619 return ret;
2620}
2621// HDCP end
2622
2623// DTM start
2624static int psp_dtm_initialize(struct psp_context *psp)
2625{
2626 int ret;
2627
2628 /*
2629 * TODO: bypass the initialize in sriov for now
2630 */
2631 if (amdgpu_sriov_vf(psp->adev))
2632 return 0;
2633
2634 /* bypass dtm initialization if dmu is harvested */
2635 if (!amdgpu_device_has_display_hardware(psp->adev))
2636 return 0;
2637
2638 if (!psp->dtm_context.context.bin_desc.size_bytes ||
2639 !psp->dtm_context.context.bin_desc.start_addr) {
2640 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");
2641 return 0;
2642 }
2643
2644 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE;
2645 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
2646
2647 if (!psp->dtm_context.context.mem_context.shared_buf) {
2648 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context);
2649 if (ret)
2650 return ret;
2651 }
2652
2653 ret = psp_ta_load(psp, &psp->dtm_context.context);
2654 if (!ret) {
2655 psp->dtm_context.context.initialized = true;
2656 mutex_init(&psp->dtm_context.mutex);
2657 }
2658
2659 return ret;
2660}
2661
2662int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
2663{
2664 /*
2665 * TODO: bypass the loading in sriov for now
2666 */
2667 if (amdgpu_sriov_vf(psp->adev))
2668 return 0;
2669
2670 if (!psp->dtm_context.context.initialized)
2671 return 0;
2672
2673 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context);
2674}
2675
2676static int psp_dtm_terminate(struct psp_context *psp)
2677{
2678 int ret;
2679
2680 /*
2681 * TODO: bypass the terminate in sriov for now
2682 */
2683 if (amdgpu_sriov_vf(psp->adev))
2684 return 0;
2685
2686 if (!psp->dtm_context.context.initialized)
2687 return 0;
2688
2689 ret = psp_ta_unload(psp, &psp->dtm_context.context);
2690
2691 psp->dtm_context.context.initialized = false;
2692
2693 return ret;
2694}
2695// DTM end
2696
2697// RAP start
2698static int psp_rap_initialize(struct psp_context *psp)
2699{
2700 int ret;
2701 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS;
2702
2703 /*
2704 * TODO: bypass the initialize in sriov for now
2705 */
2706 if (amdgpu_sriov_vf(psp->adev))
2707 return 0;
2708
2709 if (!psp->rap_context.context.bin_desc.size_bytes ||
2710 !psp->rap_context.context.bin_desc.start_addr) {
2711 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n");
2712 return 0;
2713 }
2714
2715 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE;
2716 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
2717
2718 if (!psp->rap_context.context.mem_context.shared_buf) {
2719 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context);
2720 if (ret)
2721 return ret;
2722 }
2723
2724 ret = psp_ta_load(psp, &psp->rap_context.context);
2725 if (!ret) {
2726 psp->rap_context.context.initialized = true;
2727 mutex_init(&psp->rap_context.mutex);
2728 } else
2729 return ret;
2730
2731 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status);
2732 if (ret || status != TA_RAP_STATUS__SUCCESS) {
2733 psp_rap_terminate(psp);
2734 /* free rap shared memory */
2735 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
2736
2737 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n",
2738 ret, status);
2739
2740 return ret;
2741 }
2742
2743 return 0;
2744}
2745
2746static int psp_rap_terminate(struct psp_context *psp)
2747{
2748 int ret;
2749
2750 if (!psp->rap_context.context.initialized)
2751 return 0;
2752
2753 ret = psp_ta_unload(psp, &psp->rap_context.context);
2754
2755 psp->rap_context.context.initialized = false;
2756
2757 return ret;
2758}
2759
2760int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status)
2761{
2762 struct ta_rap_shared_memory *rap_cmd;
2763 int ret = 0;
2764
2765 if (!psp->rap_context.context.initialized)
2766 return 0;
2767
2768 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE &&
2769 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0)
2770 return -EINVAL;
2771
2772 mutex_lock(&psp->rap_context.mutex);
2773
2774 rap_cmd = (struct ta_rap_shared_memory *)
2775 psp->rap_context.context.mem_context.shared_buf;
2776 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory));
2777
2778 rap_cmd->cmd_id = ta_cmd_id;
2779 rap_cmd->validation_method_id = METHOD_A;
2780
2781 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context);
2782 if (ret)
2783 goto out_unlock;
2784
2785 if (status)
2786 *status = rap_cmd->rap_status;
2787
2788out_unlock:
2789 mutex_unlock(&psp->rap_context.mutex);
2790
2791 return ret;
2792}
2793// RAP end
2794
2795/* securedisplay start */
2796static int psp_securedisplay_initialize(struct psp_context *psp)
2797{
2798 int ret;
2799 struct ta_securedisplay_cmd *securedisplay_cmd;
2800
2801 /*
2802 * TODO: bypass the initialize in sriov for now
2803 */
2804 if (amdgpu_sriov_vf(psp->adev))
2805 return 0;
2806
2807 /* bypass securedisplay initialization if dmu is harvested */
2808 if (!amdgpu_device_has_display_hardware(psp->adev))
2809 return 0;
2810
2811 if (!psp->securedisplay_context.context.bin_desc.size_bytes ||
2812 !psp->securedisplay_context.context.bin_desc.start_addr) {
2813 dev_info(psp->adev->dev,
2814 "SECUREDISPLAY: optional securedisplay ta ucode is not available\n");
2815 return 0;
2816 }
2817
2818 psp->securedisplay_context.context.mem_context.shared_mem_size =
2819 PSP_SECUREDISPLAY_SHARED_MEM_SIZE;
2820 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
2821
2822 if (!psp->securedisplay_context.context.initialized) {
2823 ret = psp_ta_init_shared_buf(psp,
2824 &psp->securedisplay_context.context.mem_context);
2825 if (ret)
2826 return ret;
2827 }
2828
2829 ret = psp_ta_load(psp, &psp->securedisplay_context.context);
2830 if (!ret && !psp->securedisplay_context.context.resp_status) {
2831 psp->securedisplay_context.context.initialized = true;
2832 mutex_init(&psp->securedisplay_context.mutex);
2833 } else {
2834 /* don't try again */
2835 psp->securedisplay_context.context.bin_desc.size_bytes = 0;
2836 return ret;
2837 }
2838
2839 mutex_lock(&psp->securedisplay_context.mutex);
2840
2841 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
2842 TA_SECUREDISPLAY_COMMAND__QUERY_TA);
2843
2844 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA);
2845
2846 mutex_unlock(&psp->securedisplay_context.mutex);
2847
2848 if (ret) {
2849 psp_securedisplay_terminate(psp);
2850 /* free securedisplay shared memory */
2851 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
2852 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n");
2853 return -EINVAL;
2854 }
2855
2856 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) {
2857 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
2858 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n",
2859 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret);
2860 /* don't try again */
2861 psp->securedisplay_context.context.bin_desc.size_bytes = 0;
2862 }
2863
2864 return 0;
2865}
2866
2867static int psp_securedisplay_terminate(struct psp_context *psp)
2868{
2869 int ret;
2870
2871 /*
2872 * TODO:bypass the terminate in sriov for now
2873 */
2874 if (amdgpu_sriov_vf(psp->adev))
2875 return 0;
2876
2877 if (!psp->securedisplay_context.context.initialized)
2878 return 0;
2879
2880 ret = psp_ta_unload(psp, &psp->securedisplay_context.context);
2881
2882 psp->securedisplay_context.context.initialized = false;
2883
2884 return ret;
2885}
2886
2887int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
2888{
2889 int ret;
2890
2891 if (!psp->securedisplay_context.context.initialized)
2892 return -EINVAL;
2893
2894 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA &&
2895 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC &&
2896 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC_V2)
2897 return -EINVAL;
2898
2899 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context);
2900
2901 return ret;
2902}
2903/* SECUREDISPLAY end */
2904
2905int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev)
2906{
2907 struct psp_context *psp = &adev->psp;
2908 int ret = 0;
2909
2910 if (!amdgpu_sriov_vf(adev) && psp->funcs && psp->funcs->wait_for_bootloader != NULL)
2911 ret = psp->funcs->wait_for_bootloader(psp);
2912
2913 return ret;
2914}
2915
2916bool amdgpu_psp_get_ras_capability(struct psp_context *psp)
2917{
2918 if (psp->funcs &&
2919 psp->funcs->get_ras_capability) {
2920 return psp->funcs->get_ras_capability(psp);
2921 } else {
2922 return false;
2923 }
2924}
2925
2926bool amdgpu_psp_tos_reload_needed(struct amdgpu_device *adev)
2927{
2928 struct psp_context *psp = &adev->psp;
2929
2930 if (amdgpu_sriov_vf(adev) || (adev->flags & AMD_IS_APU))
2931 return false;
2932
2933 if (psp->funcs && psp->funcs->is_reload_needed)
2934 return psp->funcs->is_reload_needed(psp);
2935
2936 return false;
2937}
2938
2939static void psp_update_gpu_addresses(struct amdgpu_device *adev)
2940{
2941 struct psp_context *psp = &adev->psp;
2942
2943 if (psp->cmd_buf_bo && psp->cmd_buf_mem) {
2944 psp->fw_pri_mc_addr = amdgpu_bo_fb_aper_addr(psp->fw_pri_bo);
2945 psp->fence_buf_mc_addr = amdgpu_bo_fb_aper_addr(psp->fence_buf_bo);
2946 psp->cmd_buf_mc_addr = amdgpu_bo_fb_aper_addr(psp->cmd_buf_bo);
2947 }
2948 if (adev->firmware.rbuf && psp->km_ring.ring_mem)
2949 psp->km_ring.ring_mem_mc_addr = amdgpu_bo_fb_aper_addr(adev->firmware.rbuf);
2950}
2951
2952static int psp_hw_start(struct psp_context *psp)
2953{
2954 struct amdgpu_device *adev = psp->adev;
2955 int ret;
2956
2957 if (amdgpu_virt_xgmi_migrate_enabled(adev))
2958 psp_update_gpu_addresses(adev);
2959
2960 if (!amdgpu_sriov_vf(adev)) {
2961 if ((is_psp_fw_valid(psp->kdb)) &&
2962 (psp->funcs->bootloader_load_kdb != NULL)) {
2963 ret = psp_bootloader_load_kdb(psp);
2964 if (ret) {
2965 dev_err(adev->dev, "PSP load kdb failed!\n");
2966 return ret;
2967 }
2968 }
2969
2970 if ((is_psp_fw_valid(psp->spl)) &&
2971 (psp->funcs->bootloader_load_spl != NULL)) {
2972 ret = psp_bootloader_load_spl(psp);
2973 if (ret) {
2974 dev_err(adev->dev, "PSP load spl failed!\n");
2975 return ret;
2976 }
2977 }
2978
2979 if ((is_psp_fw_valid(psp->sys)) &&
2980 (psp->funcs->bootloader_load_sysdrv != NULL)) {
2981 ret = psp_bootloader_load_sysdrv(psp);
2982 if (ret) {
2983 dev_err(adev->dev, "PSP load sys drv failed!\n");
2984 return ret;
2985 }
2986 }
2987
2988 if ((is_psp_fw_valid(psp->soc_drv)) &&
2989 (psp->funcs->bootloader_load_soc_drv != NULL)) {
2990 ret = psp_bootloader_load_soc_drv(psp);
2991 if (ret) {
2992 dev_err(adev->dev, "PSP load soc drv failed!\n");
2993 return ret;
2994 }
2995 }
2996
2997 if ((is_psp_fw_valid(psp->intf_drv)) &&
2998 (psp->funcs->bootloader_load_intf_drv != NULL)) {
2999 ret = psp_bootloader_load_intf_drv(psp);
3000 if (ret) {
3001 dev_err(adev->dev, "PSP load intf drv failed!\n");
3002 return ret;
3003 }
3004 }
3005
3006 if ((is_psp_fw_valid(psp->dbg_drv)) &&
3007 (psp->funcs->bootloader_load_dbg_drv != NULL)) {
3008 ret = psp_bootloader_load_dbg_drv(psp);
3009 if (ret) {
3010 dev_err(adev->dev, "PSP load dbg drv failed!\n");
3011 return ret;
3012 }
3013 }
3014
3015 if ((is_psp_fw_valid(psp->ras_drv)) &&
3016 (psp->funcs->bootloader_load_ras_drv != NULL)) {
3017 ret = psp_bootloader_load_ras_drv(psp);
3018 if (ret) {
3019 dev_err(adev->dev, "PSP load ras_drv failed!\n");
3020 return ret;
3021 }
3022 }
3023
3024 if ((is_psp_fw_valid(psp->ipkeymgr_drv)) &&
3025 (psp->funcs->bootloader_load_ipkeymgr_drv != NULL)) {
3026 ret = psp_bootloader_load_ipkeymgr_drv(psp);
3027 if (ret) {
3028 dev_err(adev->dev, "PSP load ipkeymgr_drv failed!\n");
3029 return ret;
3030 }
3031 }
3032
3033 if ((is_psp_fw_valid(psp->spdm_drv)) &&
3034 (psp->funcs->bootloader_load_spdm_drv != NULL)) {
3035 ret = psp_bootloader_load_spdm_drv(psp);
3036 if (ret) {
3037 dev_err(adev->dev, "PSP load spdm_drv failed!\n");
3038 return ret;
3039 }
3040 }
3041
3042 if ((is_psp_fw_valid(psp->sos)) &&
3043 (psp->funcs->bootloader_load_sos != NULL)) {
3044 ret = psp_bootloader_load_sos(psp);
3045 if (ret) {
3046 dev_err(adev->dev, "PSP load sos failed!\n");
3047 return ret;
3048 }
3049 }
3050 }
3051
3052 ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
3053 if (ret) {
3054 dev_err(adev->dev, "PSP create ring failed!\n");
3055 return ret;
3056 }
3057
3058 if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
3059 ret = psp_update_fw_reservation(psp);
3060 if (ret) {
3061 dev_err(adev->dev, "update fw reservation failed!\n");
3062 return ret;
3063 }
3064 }
3065
3066 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
3067 goto skip_pin_bo;
3068
3069 if (!psp->boot_time_tmr || psp->autoload_supported) {
3070 ret = psp_tmr_init(psp);
3071 if (ret) {
3072 dev_err(adev->dev, "PSP tmr init failed!\n");
3073 return ret;
3074 }
3075 }
3076
3077skip_pin_bo:
3078 /*
3079 * For ASICs with DF Cstate management centralized
3080 * to PMFW, TMR setup should be performed after PMFW
3081 * loaded and before other non-psp firmware loaded.
3082 */
3083 if (psp->pmfw_centralized_cstate_management) {
3084 ret = psp_load_smu_fw(psp);
3085 if (ret)
3086 return ret;
3087 }
3088
3089 ret = psp_tmr_load(psp);
3090 if (ret) {
3091 dev_err(adev->dev, "PSP load tmr failed!\n");
3092 return ret;
3093 }
3094
3095 return 0;
3096}
3097
3098int amdgpu_psp_get_fw_type(struct amdgpu_firmware_info *ucode,
3099 enum psp_gfx_fw_type *type)
3100{
3101 switch (ucode->ucode_id) {
3102 case AMDGPU_UCODE_ID_CAP:
3103 *type = GFX_FW_TYPE_CAP;
3104 break;
3105 case AMDGPU_UCODE_ID_SDMA0:
3106 *type = GFX_FW_TYPE_SDMA0;
3107 break;
3108 case AMDGPU_UCODE_ID_SDMA1:
3109 *type = GFX_FW_TYPE_SDMA1;
3110 break;
3111 case AMDGPU_UCODE_ID_SDMA2:
3112 *type = GFX_FW_TYPE_SDMA2;
3113 break;
3114 case AMDGPU_UCODE_ID_SDMA3:
3115 *type = GFX_FW_TYPE_SDMA3;
3116 break;
3117 case AMDGPU_UCODE_ID_SDMA4:
3118 *type = GFX_FW_TYPE_SDMA4;
3119 break;
3120 case AMDGPU_UCODE_ID_SDMA5:
3121 *type = GFX_FW_TYPE_SDMA5;
3122 break;
3123 case AMDGPU_UCODE_ID_SDMA6:
3124 *type = GFX_FW_TYPE_SDMA6;
3125 break;
3126 case AMDGPU_UCODE_ID_SDMA7:
3127 *type = GFX_FW_TYPE_SDMA7;
3128 break;
3129 case AMDGPU_UCODE_ID_CP_MES:
3130 *type = GFX_FW_TYPE_CP_MES;
3131 break;
3132 case AMDGPU_UCODE_ID_CP_MES_DATA:
3133 *type = GFX_FW_TYPE_MES_STACK;
3134 break;
3135 case AMDGPU_UCODE_ID_CP_MES1:
3136 *type = GFX_FW_TYPE_CP_MES_KIQ;
3137 break;
3138 case AMDGPU_UCODE_ID_CP_MES1_DATA:
3139 *type = GFX_FW_TYPE_MES_KIQ_STACK;
3140 break;
3141 case AMDGPU_UCODE_ID_CP_CE:
3142 *type = GFX_FW_TYPE_CP_CE;
3143 break;
3144 case AMDGPU_UCODE_ID_CP_PFP:
3145 *type = GFX_FW_TYPE_CP_PFP;
3146 break;
3147 case AMDGPU_UCODE_ID_CP_ME:
3148 *type = GFX_FW_TYPE_CP_ME;
3149 break;
3150 case AMDGPU_UCODE_ID_CP_MEC1:
3151 *type = GFX_FW_TYPE_CP_MEC;
3152 break;
3153 case AMDGPU_UCODE_ID_CP_MEC1_JT:
3154 *type = GFX_FW_TYPE_CP_MEC_ME1;
3155 break;
3156 case AMDGPU_UCODE_ID_CP_MEC2:
3157 *type = GFX_FW_TYPE_CP_MEC;
3158 break;
3159 case AMDGPU_UCODE_ID_CP_MEC2_JT:
3160 *type = GFX_FW_TYPE_CP_MEC_ME2;
3161 break;
3162 case AMDGPU_UCODE_ID_RLC_P:
3163 *type = GFX_FW_TYPE_RLC_P;
3164 break;
3165 case AMDGPU_UCODE_ID_RLC_V:
3166 *type = GFX_FW_TYPE_RLC_V;
3167 break;
3168 case AMDGPU_UCODE_ID_RLC_G:
3169 *type = GFX_FW_TYPE_RLC_G;
3170 break;
3171 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
3172 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
3173 break;
3174 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
3175 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
3176 break;
3177 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
3178 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
3179 break;
3180 case AMDGPU_UCODE_ID_RLC_IRAM:
3181 *type = GFX_FW_TYPE_RLC_IRAM;
3182 break;
3183 case AMDGPU_UCODE_ID_RLC_DRAM:
3184 *type = GFX_FW_TYPE_RLC_DRAM_BOOT;
3185 break;
3186 case AMDGPU_UCODE_ID_RLC_IRAM_1:
3187 *type = GFX_FW_TYPE_RLX6_UCODE_CORE1;
3188 break;
3189 case AMDGPU_UCODE_ID_RLC_DRAM_1:
3190 *type = GFX_FW_TYPE_RLX6_DRAM_BOOT_CORE1;
3191 break;
3192 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
3193 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS;
3194 break;
3195 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS:
3196 *type = GFX_FW_TYPE_SE0_TAP_DELAYS;
3197 break;
3198 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS:
3199 *type = GFX_FW_TYPE_SE1_TAP_DELAYS;
3200 break;
3201 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS:
3202 *type = GFX_FW_TYPE_SE2_TAP_DELAYS;
3203 break;
3204 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS:
3205 *type = GFX_FW_TYPE_SE3_TAP_DELAYS;
3206 break;
3207 case AMDGPU_UCODE_ID_SMC:
3208 *type = GFX_FW_TYPE_SMU;
3209 break;
3210 case AMDGPU_UCODE_ID_PPTABLE:
3211 *type = GFX_FW_TYPE_PPTABLE;
3212 break;
3213 case AMDGPU_UCODE_ID_UVD:
3214 *type = GFX_FW_TYPE_UVD;
3215 break;
3216 case AMDGPU_UCODE_ID_UVD1:
3217 *type = GFX_FW_TYPE_UVD1;
3218 break;
3219 case AMDGPU_UCODE_ID_VCE:
3220 *type = GFX_FW_TYPE_VCE;
3221 break;
3222 case AMDGPU_UCODE_ID_VCN:
3223 *type = GFX_FW_TYPE_VCN;
3224 break;
3225 case AMDGPU_UCODE_ID_VCN1:
3226 *type = GFX_FW_TYPE_VCN1;
3227 break;
3228 case AMDGPU_UCODE_ID_DMCU_ERAM:
3229 *type = GFX_FW_TYPE_DMCU_ERAM;
3230 break;
3231 case AMDGPU_UCODE_ID_DMCU_INTV:
3232 *type = GFX_FW_TYPE_DMCU_ISR;
3233 break;
3234 case AMDGPU_UCODE_ID_VCN0_RAM:
3235 *type = GFX_FW_TYPE_VCN0_RAM;
3236 break;
3237 case AMDGPU_UCODE_ID_VCN1_RAM:
3238 *type = GFX_FW_TYPE_VCN1_RAM;
3239 break;
3240 case AMDGPU_UCODE_ID_DMCUB:
3241 *type = GFX_FW_TYPE_DMUB;
3242 break;
3243 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
3244 case AMDGPU_UCODE_ID_SDMA_RS64:
3245 *type = GFX_FW_TYPE_SDMA_UCODE_TH0;
3246 break;
3247 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
3248 *type = GFX_FW_TYPE_SDMA_UCODE_TH1;
3249 break;
3250 case AMDGPU_UCODE_ID_IMU_I:
3251 *type = GFX_FW_TYPE_IMU_I;
3252 break;
3253 case AMDGPU_UCODE_ID_IMU_D:
3254 *type = GFX_FW_TYPE_IMU_D;
3255 break;
3256 case AMDGPU_UCODE_ID_CP_RS64_PFP:
3257 *type = GFX_FW_TYPE_RS64_PFP;
3258 break;
3259 case AMDGPU_UCODE_ID_CP_RS64_ME:
3260 *type = GFX_FW_TYPE_RS64_ME;
3261 break;
3262 case AMDGPU_UCODE_ID_CP_RS64_MEC:
3263 *type = GFX_FW_TYPE_RS64_MEC;
3264 break;
3265 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
3266 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK;
3267 break;
3268 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
3269 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK;
3270 break;
3271 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
3272 *type = GFX_FW_TYPE_RS64_ME_P0_STACK;
3273 break;
3274 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
3275 *type = GFX_FW_TYPE_RS64_ME_P1_STACK;
3276 break;
3277 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
3278 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK;
3279 break;
3280 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
3281 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK;
3282 break;
3283 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
3284 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK;
3285 break;
3286 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
3287 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK;
3288 break;
3289 case AMDGPU_UCODE_ID_VPE_CTX:
3290 *type = GFX_FW_TYPE_VPEC_FW1;
3291 break;
3292 case AMDGPU_UCODE_ID_VPE_CTL:
3293 *type = GFX_FW_TYPE_VPEC_FW2;
3294 break;
3295 case AMDGPU_UCODE_ID_VPE:
3296 *type = GFX_FW_TYPE_VPE;
3297 break;
3298 case AMDGPU_UCODE_ID_UMSCH_MM_UCODE:
3299 *type = GFX_FW_TYPE_UMSCH_UCODE;
3300 break;
3301 case AMDGPU_UCODE_ID_UMSCH_MM_DATA:
3302 *type = GFX_FW_TYPE_UMSCH_DATA;
3303 break;
3304 case AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER:
3305 *type = GFX_FW_TYPE_UMSCH_CMD_BUFFER;
3306 break;
3307 case AMDGPU_UCODE_ID_P2S_TABLE:
3308 *type = GFX_FW_TYPE_P2S_TABLE;
3309 break;
3310 case AMDGPU_UCODE_ID_JPEG_RAM:
3311 *type = GFX_FW_TYPE_JPEG_RAM;
3312 break;
3313 case AMDGPU_UCODE_ID_ISP:
3314 *type = GFX_FW_TYPE_ISP;
3315 break;
3316 case AMDGPU_UCODE_ID_MAXIMUM:
3317 default:
3318 return -EINVAL;
3319 }
3320
3321 return 0;
3322}
3323
3324static void psp_print_fw_hdr(struct psp_context *psp,
3325 struct amdgpu_firmware_info *ucode)
3326{
3327 struct amdgpu_device *adev = psp->adev;
3328 struct common_firmware_header *hdr;
3329
3330 switch (ucode->ucode_id) {
3331 case AMDGPU_UCODE_ID_SDMA0:
3332 case AMDGPU_UCODE_ID_SDMA1:
3333 case AMDGPU_UCODE_ID_SDMA2:
3334 case AMDGPU_UCODE_ID_SDMA3:
3335 case AMDGPU_UCODE_ID_SDMA4:
3336 case AMDGPU_UCODE_ID_SDMA5:
3337 case AMDGPU_UCODE_ID_SDMA6:
3338 case AMDGPU_UCODE_ID_SDMA7:
3339 hdr = (struct common_firmware_header *)
3340 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
3341 amdgpu_ucode_print_sdma_hdr(hdr);
3342 break;
3343 case AMDGPU_UCODE_ID_CP_CE:
3344 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
3345 amdgpu_ucode_print_gfx_hdr(hdr);
3346 break;
3347 case AMDGPU_UCODE_ID_CP_PFP:
3348 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
3349 amdgpu_ucode_print_gfx_hdr(hdr);
3350 break;
3351 case AMDGPU_UCODE_ID_CP_ME:
3352 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
3353 amdgpu_ucode_print_gfx_hdr(hdr);
3354 break;
3355 case AMDGPU_UCODE_ID_CP_MEC1:
3356 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
3357 amdgpu_ucode_print_gfx_hdr(hdr);
3358 break;
3359 case AMDGPU_UCODE_ID_RLC_G:
3360 case AMDGPU_UCODE_ID_RLC_DRAM_1:
3361 case AMDGPU_UCODE_ID_RLC_IRAM_1:
3362 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
3363 amdgpu_ucode_print_rlc_hdr(hdr);
3364 break;
3365 case AMDGPU_UCODE_ID_SMC:
3366 hdr = (struct common_firmware_header *)adev->pm.fw->data;
3367 amdgpu_ucode_print_smc_hdr(hdr);
3368 break;
3369 default:
3370 break;
3371 }
3372}
3373
3374static int psp_prep_load_ip_fw_cmd_buf(struct psp_context *psp,
3375 struct amdgpu_firmware_info *ucode,
3376 struct psp_gfx_cmd_resp *cmd)
3377{
3378 int ret;
3379 uint64_t fw_mem_mc_addr = ucode->mc_addr;
3380
3381 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
3382 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
3383 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
3384 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
3385
3386 ret = psp_get_fw_type(psp, ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
3387 if (ret)
3388 dev_err(psp->adev->dev, "Unknown firmware type %d\n", ucode->ucode_id);
3389 return ret;
3390}
3391
3392int psp_execute_ip_fw_load(struct psp_context *psp,
3393 struct amdgpu_firmware_info *ucode)
3394{
3395 int ret = 0;
3396 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
3397
3398 ret = psp_prep_load_ip_fw_cmd_buf(psp, ucode, cmd);
3399 if (!ret) {
3400 ret = psp_cmd_submit_buf(psp, ucode, cmd,
3401 psp->fence_buf_mc_addr);
3402 }
3403
3404 release_psp_cmd_buf(psp);
3405
3406 return ret;
3407}
3408
3409static int psp_load_p2s_table(struct psp_context *psp)
3410{
3411 int ret;
3412 struct amdgpu_device *adev = psp->adev;
3413 struct amdgpu_firmware_info *ucode =
3414 &adev->firmware.ucode[AMDGPU_UCODE_ID_P2S_TABLE];
3415
3416 if (adev->in_runpm && ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) ||
3417 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)))
3418 return 0;
3419
3420 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||
3421 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) {
3422 uint32_t supp_vers = adev->flags & AMD_IS_APU ? 0x0036013D :
3423 0x0036003C;
3424 if (psp->sos.fw_version < supp_vers)
3425 return 0;
3426 }
3427
3428 if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
3429 return 0;
3430
3431 ret = psp_execute_ip_fw_load(psp, ucode);
3432
3433 return ret;
3434}
3435
3436static int psp_load_smu_fw(struct psp_context *psp)
3437{
3438 int ret;
3439 struct amdgpu_device *adev = psp->adev;
3440 struct amdgpu_firmware_info *ucode =
3441 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
3442 struct amdgpu_ras *ras = psp->ras_context.ras;
3443
3444 /*
3445 * Skip SMU FW reloading in case of using BACO for runpm only,
3446 * as SMU is always alive.
3447 */
3448 if (adev->in_runpm && ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) ||
3449 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)))
3450 return 0;
3451
3452 if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
3453 return 0;
3454
3455 if ((amdgpu_in_reset(adev) && ras && adev->ras_enabled &&
3456 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) ||
3457 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 2)))) {
3458 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
3459 if (ret)
3460 dev_err(adev->dev, "Failed to set MP1 state prepare for reload\n");
3461 }
3462
3463 ret = psp_execute_ip_fw_load(psp, ucode);
3464
3465 if (ret)
3466 dev_err(adev->dev, "PSP load smu failed!\n");
3467
3468 return ret;
3469}
3470
3471static bool fw_load_skip_check(struct psp_context *psp,
3472 struct amdgpu_firmware_info *ucode)
3473{
3474 if (!ucode->fw || !ucode->ucode_size)
3475 return true;
3476
3477 if (ucode->ucode_id == AMDGPU_UCODE_ID_P2S_TABLE)
3478 return true;
3479
3480 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
3481 (psp_smu_reload_quirk(psp) ||
3482 psp->autoload_supported ||
3483 psp->pmfw_centralized_cstate_management))
3484 return true;
3485
3486 if (amdgpu_sriov_vf(psp->adev) &&
3487 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id))
3488 return true;
3489
3490 if (psp->autoload_supported &&
3491 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
3492 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
3493 /* skip mec JT when autoload is enabled */
3494 return true;
3495
3496 return false;
3497}
3498
3499int psp_load_fw_list(struct psp_context *psp,
3500 struct amdgpu_firmware_info **ucode_list, int ucode_count)
3501{
3502 int ret = 0, i;
3503 struct amdgpu_firmware_info *ucode;
3504
3505 for (i = 0; i < ucode_count; ++i) {
3506 ucode = ucode_list[i];
3507 psp_print_fw_hdr(psp, ucode);
3508 ret = psp_execute_ip_fw_load(psp, ucode);
3509 if (ret)
3510 return ret;
3511 }
3512 return ret;
3513}
3514
3515static int psp_load_non_psp_fw(struct psp_context *psp)
3516{
3517 int i, ret;
3518 struct amdgpu_firmware_info *ucode;
3519 struct amdgpu_device *adev = psp->adev;
3520
3521 if (psp->autoload_supported &&
3522 !psp->pmfw_centralized_cstate_management) {
3523 ret = psp_load_smu_fw(psp);
3524 if (ret)
3525 return ret;
3526 }
3527
3528 /* Load P2S table first if it's available */
3529 psp_load_p2s_table(psp);
3530
3531 for (i = 0; i < adev->firmware.max_ucodes; i++) {
3532 ucode = &adev->firmware.ucode[i];
3533
3534 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
3535 !fw_load_skip_check(psp, ucode)) {
3536 ret = psp_load_smu_fw(psp);
3537 if (ret)
3538 return ret;
3539 continue;
3540 }
3541
3542 if (fw_load_skip_check(psp, ucode))
3543 continue;
3544
3545 if (psp->autoload_supported &&
3546 (amdgpu_ip_version(adev, MP0_HWIP, 0) ==
3547 IP_VERSION(11, 0, 7) ||
3548 amdgpu_ip_version(adev, MP0_HWIP, 0) ==
3549 IP_VERSION(11, 0, 11) ||
3550 amdgpu_ip_version(adev, MP0_HWIP, 0) ==
3551 IP_VERSION(11, 0, 12) ||
3552 amdgpu_ip_version(adev, MP0_HWIP, 0) ==
3553 IP_VERSION(15, 0, 0) ||
3554 amdgpu_ip_version(adev, MP0_HWIP, 0) ==
3555 IP_VERSION(15, 0, 5) ||
3556 amdgpu_ip_version(adev, MP0_HWIP, 0) ==
3557 IP_VERSION(15, 0, 8) ||
3558 amdgpu_ip_version(adev, MP0_HWIP, 0) ==
3559 IP_VERSION(15, 0, 9)) &&
3560 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
3561 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
3562 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
3563 /* PSP only receive one SDMA fw for sienna_cichlid,
3564 * as all four sdma fw are same
3565 */
3566 continue;
3567
3568 /* IMU ucode is part of IFWI and MP0 15.0.8 would load it */
3569 if (amdgpu_ip_version(adev, MP0_HWIP, 0) ==
3570 IP_VERSION(15, 0, 8) &&
3571 (ucode->ucode_id == AMDGPU_UCODE_ID_IMU_I ||
3572 ucode->ucode_id == AMDGPU_UCODE_ID_IMU_D))
3573 continue;
3574
3575 psp_print_fw_hdr(psp, ucode);
3576
3577 ret = psp_execute_ip_fw_load(psp, ucode);
3578 if (ret)
3579 return ret;
3580
3581 /* Start rlc autoload after psp received all the gfx firmware */
3582 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
3583 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) {
3584 ret = psp_rlc_autoload_start(psp);
3585 if (ret) {
3586 dev_err(adev->dev, "Failed to start rlc autoload\n");
3587 return ret;
3588 }
3589 }
3590 }
3591
3592 return 0;
3593}
3594
3595static int psp_load_fw(struct amdgpu_device *adev)
3596{
3597 int ret;
3598 struct psp_context *psp = &adev->psp;
3599
3600 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
3601 /* should not destroy ring, only stop */
3602 psp_ring_stop(psp, PSP_RING_TYPE__KM);
3603 } else {
3604 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
3605
3606 ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
3607 if (ret) {
3608 dev_err(adev->dev, "PSP ring init failed!\n");
3609 goto failed;
3610 }
3611 }
3612
3613 ret = psp_hw_start(psp);
3614 if (ret)
3615 goto failed;
3616
3617 ret = psp_load_non_psp_fw(psp);
3618 if (ret)
3619 goto failed1;
3620
3621 ret = psp_asd_initialize(psp);
3622 if (ret) {
3623 dev_err(adev->dev, "PSP load asd failed!\n");
3624 goto failed1;
3625 }
3626
3627 ret = psp_rl_load(adev);
3628 if (ret) {
3629 dev_err(adev->dev, "PSP load RL failed!\n");
3630 goto failed1;
3631 }
3632
3633 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
3634 if (adev->gmc.xgmi.num_physical_nodes > 1) {
3635 ret = psp_xgmi_initialize(psp, false, true);
3636 /* Warning the XGMI seesion initialize failure
3637 * Instead of stop driver initialization
3638 */
3639 if (ret)
3640 dev_err(psp->adev->dev,
3641 "XGMI: Failed to initialize XGMI session\n");
3642 }
3643 }
3644
3645 if (psp->ta_fw) {
3646 ret = psp_ras_initialize(psp);
3647 if (ret)
3648 dev_err(psp->adev->dev,
3649 "RAS: Failed to initialize RAS\n");
3650
3651 ret = psp_hdcp_initialize(psp);
3652 if (ret)
3653 dev_err(psp->adev->dev,
3654 "HDCP: Failed to initialize HDCP\n");
3655
3656 ret = psp_dtm_initialize(psp);
3657 if (ret)
3658 dev_err(psp->adev->dev,
3659 "DTM: Failed to initialize DTM\n");
3660
3661 ret = psp_rap_initialize(psp);
3662 if (ret)
3663 dev_err(psp->adev->dev,
3664 "RAP: Failed to initialize RAP\n");
3665
3666 ret = psp_securedisplay_initialize(psp);
3667 if (ret)
3668 dev_err(psp->adev->dev,
3669 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
3670 }
3671
3672 return 0;
3673
3674failed1:
3675 psp_free_shared_bufs(psp);
3676failed:
3677 /*
3678 * all cleanup jobs (xgmi terminate, ras terminate,
3679 * ring destroy, cmd/fence/fw buffers destory,
3680 * psp->cmd destory) are delayed to psp_hw_fini
3681 */
3682 psp_ring_destroy(psp, PSP_RING_TYPE__KM);
3683 return ret;
3684}
3685
3686static int psp_hw_init(struct amdgpu_ip_block *ip_block)
3687{
3688 int ret;
3689 struct amdgpu_device *adev = ip_block->adev;
3690
3691 mutex_lock(&adev->firmware.mutex);
3692
3693 ret = amdgpu_ucode_init_bo(adev);
3694 if (ret)
3695 goto failed;
3696
3697 ret = psp_load_fw(adev);
3698 if (ret) {
3699 dev_err(adev->dev, "PSP firmware loading failed\n");
3700 goto failed;
3701 }
3702
3703 mutex_unlock(&adev->firmware.mutex);
3704 return 0;
3705
3706failed:
3707 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
3708 mutex_unlock(&adev->firmware.mutex);
3709 return -EINVAL;
3710}
3711
3712static int psp_hw_fini(struct amdgpu_ip_block *ip_block)
3713{
3714 struct amdgpu_device *adev = ip_block->adev;
3715 struct psp_context *psp = &adev->psp;
3716
3717 if (psp->ta_fw) {
3718 psp_ras_terminate(psp);
3719 psp_securedisplay_terminate(psp);
3720 psp_rap_terminate(psp);
3721 psp_dtm_terminate(psp);
3722 psp_hdcp_terminate(psp);
3723
3724 if (adev->gmc.xgmi.num_physical_nodes > 1)
3725 psp_xgmi_terminate(psp);
3726 }
3727
3728 psp_asd_terminate(psp);
3729 psp_tmr_terminate(psp);
3730
3731 psp_ring_destroy(psp, PSP_RING_TYPE__KM);
3732
3733 return 0;
3734}
3735
3736static int psp_suspend(struct amdgpu_ip_block *ip_block)
3737{
3738 int ret = 0;
3739 struct amdgpu_device *adev = ip_block->adev;
3740 struct psp_context *psp = &adev->psp;
3741
3742 if (adev->gmc.xgmi.num_physical_nodes > 1 &&
3743 psp->xgmi_context.context.initialized) {
3744 ret = psp_xgmi_terminate(psp);
3745 if (ret) {
3746 dev_err(adev->dev, "Failed to terminate xgmi ta\n");
3747 goto out;
3748 }
3749 }
3750
3751 if (psp->ta_fw) {
3752 ret = psp_ras_terminate(psp);
3753 if (ret) {
3754 dev_err(adev->dev, "Failed to terminate ras ta\n");
3755 goto out;
3756 }
3757 ret = psp_hdcp_terminate(psp);
3758 if (ret) {
3759 dev_err(adev->dev, "Failed to terminate hdcp ta\n");
3760 goto out;
3761 }
3762 ret = psp_dtm_terminate(psp);
3763 if (ret) {
3764 dev_err(adev->dev, "Failed to terminate dtm ta\n");
3765 goto out;
3766 }
3767 ret = psp_rap_terminate(psp);
3768 if (ret) {
3769 dev_err(adev->dev, "Failed to terminate rap ta\n");
3770 goto out;
3771 }
3772 ret = psp_securedisplay_terminate(psp);
3773 if (ret) {
3774 dev_err(adev->dev, "Failed to terminate securedisplay ta\n");
3775 goto out;
3776 }
3777 }
3778
3779 ret = psp_asd_terminate(psp);
3780 if (ret) {
3781 dev_err(adev->dev, "Failed to terminate asd\n");
3782 goto out;
3783 }
3784
3785 ret = psp_tmr_terminate(psp);
3786 if (ret) {
3787 dev_err(adev->dev, "Failed to terminate tmr\n");
3788 goto out;
3789 }
3790
3791 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
3792 if (ret)
3793 dev_err(adev->dev, "PSP ring stop failed\n");
3794
3795out:
3796 return ret;
3797}
3798
3799static int psp_resume(struct amdgpu_ip_block *ip_block)
3800{
3801 int ret;
3802 struct amdgpu_device *adev = ip_block->adev;
3803 struct psp_context *psp = &adev->psp;
3804
3805 dev_info(adev->dev, "PSP is resuming...\n");
3806
3807 if (psp->mem_train_ctx.enable_mem_training) {
3808 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
3809 if (ret) {
3810 dev_err(adev->dev, "Failed to process memory training!\n");
3811 return ret;
3812 }
3813 }
3814
3815 mutex_lock(&adev->firmware.mutex);
3816
3817 ret = amdgpu_ucode_init_bo(adev);
3818 if (ret)
3819 goto failed;
3820
3821 ret = psp_hw_start(psp);
3822 if (ret)
3823 goto failed;
3824
3825 ret = psp_load_non_psp_fw(psp);
3826 if (ret)
3827 goto failed;
3828
3829 ret = psp_asd_initialize(psp);
3830 if (ret) {
3831 dev_err(adev->dev, "PSP load asd failed!\n");
3832 goto failed;
3833 }
3834
3835 ret = psp_rl_load(adev);
3836 if (ret) {
3837 dev_err(adev->dev, "PSP load RL failed!\n");
3838 goto failed;
3839 }
3840
3841 if (adev->gmc.xgmi.num_physical_nodes > 1) {
3842 ret = psp_xgmi_initialize(psp, false, true);
3843 /* Warning the XGMI seesion initialize failure
3844 * Instead of stop driver initialization
3845 */
3846 if (ret)
3847 dev_err(psp->adev->dev,
3848 "XGMI: Failed to initialize XGMI session\n");
3849 }
3850
3851 if (psp->ta_fw) {
3852 ret = psp_ras_initialize(psp);
3853 if (ret)
3854 dev_err(psp->adev->dev,
3855 "RAS: Failed to initialize RAS\n");
3856
3857 ret = psp_hdcp_initialize(psp);
3858 if (ret)
3859 dev_err(psp->adev->dev,
3860 "HDCP: Failed to initialize HDCP\n");
3861
3862 ret = psp_dtm_initialize(psp);
3863 if (ret)
3864 dev_err(psp->adev->dev,
3865 "DTM: Failed to initialize DTM\n");
3866
3867 ret = psp_rap_initialize(psp);
3868 if (ret)
3869 dev_err(psp->adev->dev,
3870 "RAP: Failed to initialize RAP\n");
3871
3872 ret = psp_securedisplay_initialize(psp);
3873 if (ret)
3874 dev_err(psp->adev->dev,
3875 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
3876 }
3877
3878 mutex_unlock(&adev->firmware.mutex);
3879
3880 return 0;
3881
3882failed:
3883 dev_err(adev->dev, "PSP resume failed\n");
3884 mutex_unlock(&adev->firmware.mutex);
3885 return ret;
3886}
3887
3888int psp_gpu_reset(struct amdgpu_device *adev)
3889{
3890 int ret;
3891
3892 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
3893 return 0;
3894
3895 mutex_lock(&adev->psp.mutex);
3896 ret = psp_mode1_reset(&adev->psp);
3897 mutex_unlock(&adev->psp.mutex);
3898
3899 return ret;
3900}
3901
3902int psp_rlc_autoload_start(struct psp_context *psp)
3903{
3904 int ret;
3905 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
3906
3907 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
3908
3909 ret = psp_cmd_submit_buf(psp, NULL, cmd,
3910 psp->fence_buf_mc_addr);
3911
3912 release_psp_cmd_buf(psp);
3913
3914 return ret;
3915}
3916
3917int psp_ring_cmd_submit(struct psp_context *psp,
3918 uint64_t cmd_buf_mc_addr,
3919 uint64_t fence_mc_addr,
3920 int index)
3921{
3922 unsigned int psp_write_ptr_reg = 0;
3923 struct psp_gfx_rb_frame *write_frame;
3924 struct psp_ring *ring = &psp->km_ring;
3925 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
3926 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
3927 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
3928 struct amdgpu_device *adev = psp->adev;
3929 uint32_t ring_size_dw = ring->ring_size / 4;
3930 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
3931
3932 /* KM (GPCOM) prepare write pointer */
3933 psp_write_ptr_reg = psp_ring_get_wptr(psp);
3934
3935 /* Update KM RB frame pointer to new frame */
3936 /* write_frame ptr increments by size of rb_frame in bytes */
3937 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
3938 if ((psp_write_ptr_reg % ring_size_dw) == 0)
3939 write_frame = ring_buffer_start;
3940 else
3941 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
3942 /* Check invalid write_frame ptr address */
3943 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
3944 dev_err(adev->dev,
3945 "ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
3946 ring_buffer_start, ring_buffer_end, write_frame);
3947 dev_err(adev->dev,
3948 "write_frame is pointing to address out of bounds\n");
3949 return -EINVAL;
3950 }
3951
3952 /* Initialize KM RB frame */
3953 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
3954
3955 /* Update KM RB frame */
3956 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
3957 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
3958 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
3959 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
3960 write_frame->fence_value = index;
3961 amdgpu_device_flush_hdp(adev, NULL);
3962
3963 /* Update the write Pointer in DWORDs */
3964 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
3965 psp_ring_set_wptr(psp, psp_write_ptr_reg);
3966 return 0;
3967}
3968
3969int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name)
3970{
3971 struct amdgpu_device *adev = psp->adev;
3972 const struct psp_firmware_header_v1_0 *asd_hdr;
3973 int err = 0;
3974
3975 err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, AMDGPU_UCODE_REQUIRED,
3976 "amdgpu/%s_asd.bin", chip_name);
3977 if (err)
3978 goto out;
3979
3980 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
3981 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
3982 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version);
3983 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
3984 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr +
3985 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
3986 return 0;
3987out:
3988 amdgpu_ucode_release(&adev->psp.asd_fw);
3989 return err;
3990}
3991
3992int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name)
3993{
3994 struct amdgpu_device *adev = psp->adev;
3995 const struct psp_firmware_header_v1_0 *toc_hdr;
3996 int err = 0;
3997
3998 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(15, 0, 8) &&
3999 adev->rev_id == 0)
4000 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, AMDGPU_UCODE_REQUIRED,
4001 "amdgpu/%s_toc_1.bin", chip_name);
4002 else
4003 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, AMDGPU_UCODE_REQUIRED,
4004 "amdgpu/%s_toc.bin", chip_name);
4005 if (err)
4006 goto out;
4007
4008 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
4009 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
4010 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
4011 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
4012 adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
4013 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
4014 return 0;
4015out:
4016 amdgpu_ucode_release(&adev->psp.toc_fw);
4017 return err;
4018}
4019
4020static int parse_sos_bin_descriptor(struct psp_context *psp,
4021 const struct psp_fw_bin_desc *desc,
4022 const struct psp_firmware_header_v2_0 *sos_hdr)
4023{
4024 uint8_t *ucode_start_addr = NULL;
4025
4026 if (!psp || !desc || !sos_hdr)
4027 return -EINVAL;
4028
4029 ucode_start_addr = (uint8_t *)sos_hdr +
4030 le32_to_cpu(desc->offset_bytes) +
4031 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
4032
4033 switch (desc->fw_type) {
4034 case PSP_FW_TYPE_PSP_SOS:
4035 psp->sos.fw_version = le32_to_cpu(desc->fw_version);
4036 psp->sos.feature_version = le32_to_cpu(desc->fw_version);
4037 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes);
4038 psp->sos.start_addr = ucode_start_addr;
4039 break;
4040 case PSP_FW_TYPE_PSP_SYS_DRV:
4041 psp->sys.fw_version = le32_to_cpu(desc->fw_version);
4042 psp->sys.feature_version = le32_to_cpu(desc->fw_version);
4043 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes);
4044 psp->sys.start_addr = ucode_start_addr;
4045 break;
4046 case PSP_FW_TYPE_PSP_KDB:
4047 psp->kdb.fw_version = le32_to_cpu(desc->fw_version);
4048 psp->kdb.feature_version = le32_to_cpu(desc->fw_version);
4049 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes);
4050 psp->kdb.start_addr = ucode_start_addr;
4051 break;
4052 case PSP_FW_TYPE_PSP_TOC:
4053 psp->toc.fw_version = le32_to_cpu(desc->fw_version);
4054 psp->toc.feature_version = le32_to_cpu(desc->fw_version);
4055 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes);
4056 psp->toc.start_addr = ucode_start_addr;
4057 break;
4058 case PSP_FW_TYPE_PSP_SPL:
4059 psp->spl.fw_version = le32_to_cpu(desc->fw_version);
4060 psp->spl.feature_version = le32_to_cpu(desc->fw_version);
4061 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes);
4062 psp->spl.start_addr = ucode_start_addr;
4063 break;
4064 case PSP_FW_TYPE_PSP_RL:
4065 psp->rl.fw_version = le32_to_cpu(desc->fw_version);
4066 psp->rl.feature_version = le32_to_cpu(desc->fw_version);
4067 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes);
4068 psp->rl.start_addr = ucode_start_addr;
4069 break;
4070 case PSP_FW_TYPE_PSP_SOC_DRV:
4071 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version);
4072 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version);
4073 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes);
4074 psp->soc_drv.start_addr = ucode_start_addr;
4075 break;
4076 case PSP_FW_TYPE_PSP_INTF_DRV:
4077 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version);
4078 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version);
4079 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes);
4080 psp->intf_drv.start_addr = ucode_start_addr;
4081 break;
4082 case PSP_FW_TYPE_PSP_DBG_DRV:
4083 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version);
4084 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version);
4085 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes);
4086 psp->dbg_drv.start_addr = ucode_start_addr;
4087 break;
4088 case PSP_FW_TYPE_PSP_RAS_DRV:
4089 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version);
4090 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version);
4091 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes);
4092 psp->ras_drv.start_addr = ucode_start_addr;
4093 break;
4094 case PSP_FW_TYPE_PSP_IPKEYMGR_DRV:
4095 psp->ipkeymgr_drv.fw_version = le32_to_cpu(desc->fw_version);
4096 psp->ipkeymgr_drv.feature_version = le32_to_cpu(desc->fw_version);
4097 psp->ipkeymgr_drv.size_bytes = le32_to_cpu(desc->size_bytes);
4098 psp->ipkeymgr_drv.start_addr = ucode_start_addr;
4099 break;
4100 case PSP_FW_TYPE_PSP_SPDM_DRV:
4101 psp->spdm_drv.fw_version = le32_to_cpu(desc->fw_version);
4102 psp->spdm_drv.feature_version = le32_to_cpu(desc->fw_version);
4103 psp->spdm_drv.size_bytes = le32_to_cpu(desc->size_bytes);
4104 psp->spdm_drv.start_addr = ucode_start_addr;
4105 break;
4106 default:
4107 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type);
4108 break;
4109 }
4110
4111 return 0;
4112}
4113
4114static int psp_init_sos_base_fw(struct amdgpu_device *adev)
4115{
4116 const struct psp_firmware_header_v1_0 *sos_hdr;
4117 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
4118 uint8_t *ucode_array_start_addr;
4119
4120 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
4121 ucode_array_start_addr = (uint8_t *)sos_hdr +
4122 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
4123
4124 if (adev->gmc.xgmi.connected_to_cpu ||
4125 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2))) {
4126 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
4127 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version);
4128
4129 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes);
4130 adev->psp.sys.start_addr = ucode_array_start_addr;
4131
4132 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes);
4133 adev->psp.sos.start_addr = ucode_array_start_addr +
4134 le32_to_cpu(sos_hdr->sos.offset_bytes);
4135 } else {
4136 /* Load alternate PSP SOS FW */
4137 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
4138
4139 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
4140 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
4141
4142 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes);
4143 adev->psp.sys.start_addr = ucode_array_start_addr +
4144 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes);
4145
4146 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes);
4147 adev->psp.sos.start_addr = ucode_array_start_addr +
4148 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes);
4149 }
4150
4151 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) {
4152 dev_warn(adev->dev, "PSP SOS FW not available");
4153 return -EINVAL;
4154 }
4155
4156 return 0;
4157}
4158
4159int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name)
4160{
4161 struct amdgpu_device *adev = psp->adev;
4162 const struct psp_firmware_header_v1_0 *sos_hdr;
4163 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
4164 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
4165 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
4166 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0;
4167 const struct psp_firmware_header_v2_1 *sos_hdr_v2_1;
4168 int fw_index, fw_bin_count, start_index = 0;
4169 const struct psp_fw_bin_desc *fw_bin;
4170 uint8_t *ucode_array_start_addr;
4171 int err = 0;
4172
4173 if (amdgpu_is_kicker_fw(adev))
4174 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, AMDGPU_UCODE_REQUIRED,
4175 "amdgpu/%s_sos_kicker.bin", chip_name);
4176 else
4177 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, AMDGPU_UCODE_REQUIRED,
4178 "amdgpu/%s_sos.bin", chip_name);
4179 if (err)
4180 goto out;
4181
4182 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
4183 ucode_array_start_addr = (uint8_t *)sos_hdr +
4184 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
4185 amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
4186
4187 switch (sos_hdr->header.header_version_major) {
4188 case 1:
4189 err = psp_init_sos_base_fw(adev);
4190 if (err)
4191 goto out;
4192
4193 if (sos_hdr->header.header_version_minor == 1) {
4194 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
4195 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes);
4196 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr +
4197 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes);
4198 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes);
4199 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
4200 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes);
4201 }
4202 if (sos_hdr->header.header_version_minor == 2) {
4203 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
4204 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes);
4205 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
4206 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes);
4207 }
4208 if (sos_hdr->header.header_version_minor == 3) {
4209 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
4210 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes);
4211 adev->psp.toc.start_addr = ucode_array_start_addr +
4212 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes);
4213 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes);
4214 adev->psp.kdb.start_addr = ucode_array_start_addr +
4215 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes);
4216 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes);
4217 adev->psp.spl.start_addr = ucode_array_start_addr +
4218 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes);
4219 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes);
4220 adev->psp.rl.start_addr = ucode_array_start_addr +
4221 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes);
4222 }
4223 break;
4224 case 2:
4225 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data;
4226
4227 fw_bin_count = le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count);
4228
4229 if (fw_bin_count >= UCODE_MAX_PSP_PACKAGING) {
4230 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n");
4231 err = -EINVAL;
4232 goto out;
4233 }
4234
4235 if (sos_hdr_v2_0->header.header_version_minor == 1) {
4236 sos_hdr_v2_1 = (const struct psp_firmware_header_v2_1 *)adev->psp.sos_fw->data;
4237
4238 fw_bin = sos_hdr_v2_1->psp_fw_bin;
4239
4240 if (psp_is_aux_sos_load_required(psp))
4241 start_index = le32_to_cpu(sos_hdr_v2_1->psp_aux_fw_bin_index);
4242 else
4243 fw_bin_count -= le32_to_cpu(sos_hdr_v2_1->psp_aux_fw_bin_index);
4244
4245 } else {
4246 fw_bin = sos_hdr_v2_0->psp_fw_bin;
4247 }
4248
4249 for (fw_index = start_index; fw_index < fw_bin_count; fw_index++) {
4250 err = parse_sos_bin_descriptor(psp, fw_bin + fw_index,
4251 sos_hdr_v2_0);
4252 if (err)
4253 goto out;
4254 }
4255 break;
4256 default:
4257 dev_err(adev->dev,
4258 "unsupported psp sos firmware\n");
4259 err = -EINVAL;
4260 goto out;
4261 }
4262
4263 return 0;
4264out:
4265 amdgpu_ucode_release(&adev->psp.sos_fw);
4266
4267 return err;
4268}
4269
4270static bool is_ta_fw_applicable(struct psp_context *psp,
4271 const struct psp_fw_bin_desc *desc)
4272{
4273 struct amdgpu_device *adev = psp->adev;
4274 uint32_t fw_version;
4275
4276 switch (desc->fw_type) {
4277 case TA_FW_TYPE_PSP_XGMI:
4278 case TA_FW_TYPE_PSP_XGMI_AUX:
4279 /* for now, AUX TA only exists on 13.0.6 ta bin,
4280 * from v20.00.0x.14
4281 */
4282 if (amdgpu_ip_version(adev, MP0_HWIP, 0) ==
4283 IP_VERSION(13, 0, 6)) {
4284 fw_version = le32_to_cpu(desc->fw_version);
4285
4286 if (adev->flags & AMD_IS_APU &&
4287 (fw_version & 0xff) >= 0x14)
4288 return desc->fw_type == TA_FW_TYPE_PSP_XGMI_AUX;
4289 else
4290 return desc->fw_type == TA_FW_TYPE_PSP_XGMI;
4291 }
4292 break;
4293 default:
4294 break;
4295 }
4296
4297 return true;
4298}
4299
4300static int parse_ta_bin_descriptor(struct psp_context *psp,
4301 const struct psp_fw_bin_desc *desc,
4302 const struct ta_firmware_header_v2_0 *ta_hdr)
4303{
4304 uint8_t *ucode_start_addr = NULL;
4305
4306 if (!psp || !desc || !ta_hdr)
4307 return -EINVAL;
4308
4309 if (!is_ta_fw_applicable(psp, desc))
4310 return 0;
4311
4312 ucode_start_addr = (uint8_t *)ta_hdr +
4313 le32_to_cpu(desc->offset_bytes) +
4314 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
4315
4316 switch (desc->fw_type) {
4317 case TA_FW_TYPE_PSP_ASD:
4318 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
4319 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version);
4320 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
4321 psp->asd_context.bin_desc.start_addr = ucode_start_addr;
4322 break;
4323 case TA_FW_TYPE_PSP_XGMI:
4324 case TA_FW_TYPE_PSP_XGMI_AUX:
4325 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
4326 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
4327 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr;
4328 break;
4329 case TA_FW_TYPE_PSP_RAS:
4330 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
4331 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
4332 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr;
4333 break;
4334 case TA_FW_TYPE_PSP_HDCP:
4335 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
4336 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
4337 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr;
4338 break;
4339 case TA_FW_TYPE_PSP_DTM:
4340 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
4341 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
4342 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr;
4343 break;
4344 case TA_FW_TYPE_PSP_RAP:
4345 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
4346 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
4347 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr;
4348 break;
4349 case TA_FW_TYPE_PSP_SECUREDISPLAY:
4350 psp->securedisplay_context.context.bin_desc.fw_version =
4351 le32_to_cpu(desc->fw_version);
4352 psp->securedisplay_context.context.bin_desc.size_bytes =
4353 le32_to_cpu(desc->size_bytes);
4354 psp->securedisplay_context.context.bin_desc.start_addr =
4355 ucode_start_addr;
4356 break;
4357 default:
4358 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type);
4359 break;
4360 }
4361
4362 return 0;
4363}
4364
4365static int parse_ta_v1_microcode(struct psp_context *psp)
4366{
4367 const struct ta_firmware_header_v1_0 *ta_hdr;
4368 struct amdgpu_device *adev = psp->adev;
4369
4370 ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data;
4371
4372 if (le16_to_cpu(ta_hdr->header.header_version_major) != 1)
4373 return -EINVAL;
4374
4375 adev->psp.xgmi_context.context.bin_desc.fw_version =
4376 le32_to_cpu(ta_hdr->xgmi.fw_version);
4377 adev->psp.xgmi_context.context.bin_desc.size_bytes =
4378 le32_to_cpu(ta_hdr->xgmi.size_bytes);
4379 adev->psp.xgmi_context.context.bin_desc.start_addr =
4380 (uint8_t *)ta_hdr +
4381 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
4382
4383 adev->psp.ras_context.context.bin_desc.fw_version =
4384 le32_to_cpu(ta_hdr->ras.fw_version);
4385 adev->psp.ras_context.context.bin_desc.size_bytes =
4386 le32_to_cpu(ta_hdr->ras.size_bytes);
4387 adev->psp.ras_context.context.bin_desc.start_addr =
4388 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr +
4389 le32_to_cpu(ta_hdr->ras.offset_bytes);
4390
4391 adev->psp.hdcp_context.context.bin_desc.fw_version =
4392 le32_to_cpu(ta_hdr->hdcp.fw_version);
4393 adev->psp.hdcp_context.context.bin_desc.size_bytes =
4394 le32_to_cpu(ta_hdr->hdcp.size_bytes);
4395 adev->psp.hdcp_context.context.bin_desc.start_addr =
4396 (uint8_t *)ta_hdr +
4397 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
4398
4399 adev->psp.dtm_context.context.bin_desc.fw_version =
4400 le32_to_cpu(ta_hdr->dtm.fw_version);
4401 adev->psp.dtm_context.context.bin_desc.size_bytes =
4402 le32_to_cpu(ta_hdr->dtm.size_bytes);
4403 adev->psp.dtm_context.context.bin_desc.start_addr =
4404 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
4405 le32_to_cpu(ta_hdr->dtm.offset_bytes);
4406
4407 adev->psp.securedisplay_context.context.bin_desc.fw_version =
4408 le32_to_cpu(ta_hdr->securedisplay.fw_version);
4409 adev->psp.securedisplay_context.context.bin_desc.size_bytes =
4410 le32_to_cpu(ta_hdr->securedisplay.size_bytes);
4411 adev->psp.securedisplay_context.context.bin_desc.start_addr =
4412 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
4413 le32_to_cpu(ta_hdr->securedisplay.offset_bytes);
4414
4415 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
4416
4417 return 0;
4418}
4419
4420static int parse_ta_v2_microcode(struct psp_context *psp)
4421{
4422 const struct ta_firmware_header_v2_0 *ta_hdr;
4423 struct amdgpu_device *adev = psp->adev;
4424 int err = 0;
4425 int ta_index = 0;
4426
4427 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data;
4428
4429 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2)
4430 return -EINVAL;
4431
4432 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
4433 dev_err(adev->dev, "packed TA count exceeds maximum limit\n");
4434 return -EINVAL;
4435 }
4436
4437 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) {
4438 err = parse_ta_bin_descriptor(psp,
4439 &ta_hdr->ta_fw_bin[ta_index],
4440 ta_hdr);
4441 if (err)
4442 return err;
4443 }
4444
4445 return 0;
4446}
4447
4448int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name)
4449{
4450 const struct common_firmware_header *hdr;
4451 struct amdgpu_device *adev = psp->adev;
4452 int err;
4453
4454 if (amdgpu_is_kicker_fw(adev))
4455 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, AMDGPU_UCODE_REQUIRED,
4456 "amdgpu/%s_ta_kicker.bin", chip_name);
4457 else
4458 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, AMDGPU_UCODE_REQUIRED,
4459 "amdgpu/%s_ta.bin", chip_name);
4460 if (err)
4461 return err;
4462
4463 hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data;
4464 switch (le16_to_cpu(hdr->header_version_major)) {
4465 case 1:
4466 err = parse_ta_v1_microcode(psp);
4467 break;
4468 case 2:
4469 err = parse_ta_v2_microcode(psp);
4470 break;
4471 default:
4472 dev_err(adev->dev, "unsupported TA header version\n");
4473 err = -EINVAL;
4474 }
4475
4476 if (err)
4477 amdgpu_ucode_release(&adev->psp.ta_fw);
4478
4479 return err;
4480}
4481
4482int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name)
4483{
4484 struct amdgpu_device *adev = psp->adev;
4485 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0;
4486 struct amdgpu_firmware_info *info = NULL;
4487 int err = 0;
4488
4489 if (!amdgpu_sriov_vf(adev)) {
4490 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n");
4491 return -EINVAL;
4492 }
4493
4494 err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, AMDGPU_UCODE_OPTIONAL,
4495 "amdgpu/%s_cap.bin", chip_name);
4496 if (err) {
4497 if (err == -ENODEV) {
4498 dev_warn(adev->dev, "cap microcode does not exist, skip\n");
4499 err = 0;
4500 } else {
4501 dev_err(adev->dev, "fail to initialize cap microcode\n");
4502 }
4503 goto out;
4504 }
4505
4506 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP];
4507 info->ucode_id = AMDGPU_UCODE_ID_CAP;
4508 info->fw = adev->psp.cap_fw;
4509 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *)
4510 adev->psp.cap_fw->data;
4511 adev->firmware.fw_size += ALIGN(
4512 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE);
4513 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version);
4514 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version);
4515 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes);
4516
4517 return 0;
4518
4519out:
4520 amdgpu_ucode_release(&adev->psp.cap_fw);
4521 return err;
4522}
4523
4524int psp_config_sq_perfmon(struct psp_context *psp,
4525 uint32_t xcp_id, bool core_override_enable,
4526 bool reg_override_enable, bool perfmon_override_enable)
4527{
4528 int ret;
4529
4530 if (amdgpu_sriov_vf(psp->adev))
4531 return 0;
4532
4533 if (xcp_id > MAX_XCP) {
4534 dev_err(psp->adev->dev, "invalid xcp_id %d\n", xcp_id);
4535 return -EINVAL;
4536 }
4537
4538 if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) {
4539 dev_err(psp->adev->dev, "Unsupported MP0 version 0x%x for CONFIG_SQ_PERFMON command\n",
4540 amdgpu_ip_version(psp->adev, MP0_HWIP, 0));
4541 return -EINVAL;
4542 }
4543 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
4544
4545 cmd->cmd_id = GFX_CMD_ID_CONFIG_SQ_PERFMON;
4546 cmd->cmd.config_sq_perfmon.gfx_xcp_mask = BIT_MASK(xcp_id);
4547 cmd->cmd.config_sq_perfmon.core_override = core_override_enable;
4548 cmd->cmd.config_sq_perfmon.reg_override = reg_override_enable;
4549 cmd->cmd.config_sq_perfmon.perfmon_override = perfmon_override_enable;
4550
4551 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
4552 if (ret)
4553 dev_warn(psp->adev->dev, "PSP failed to config sq: xcp%d core%d reg%d perfmon%d\n",
4554 xcp_id, core_override_enable, reg_override_enable, perfmon_override_enable);
4555
4556 release_psp_cmd_buf(psp);
4557 return ret;
4558}
4559
4560static int psp_set_clockgating_state(struct amdgpu_ip_block *ip_block,
4561 enum amd_clockgating_state state)
4562{
4563 return 0;
4564}
4565
4566static int psp_set_powergating_state(struct amdgpu_ip_block *ip_block,
4567 enum amd_powergating_state state)
4568{
4569 return 0;
4570}
4571
4572static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,
4573 struct device_attribute *attr,
4574 char *buf)
4575{
4576 struct drm_device *ddev = dev_get_drvdata(dev);
4577 struct amdgpu_device *adev = drm_to_adev(ddev);
4578 struct amdgpu_ip_block *ip_block;
4579 uint32_t fw_ver;
4580 int ret;
4581
4582 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP);
4583 if (!ip_block || !ip_block->status.late_initialized) {
4584 dev_info(adev->dev, "PSP block is not ready yet\n.");
4585 return -EBUSY;
4586 }
4587
4588 mutex_lock(&adev->psp.mutex);
4589 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver);
4590 mutex_unlock(&adev->psp.mutex);
4591
4592 if (ret) {
4593 dev_err(adev->dev, "Failed to read USBC PD FW, err = %d\n", ret);
4594 return ret;
4595 }
4596
4597 return sysfs_emit(buf, "%x\n", fw_ver);
4598}
4599
4600static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
4601 struct device_attribute *attr,
4602 const char *buf,
4603 size_t count)
4604{
4605 struct drm_device *ddev = dev_get_drvdata(dev);
4606 struct amdgpu_device *adev = drm_to_adev(ddev);
4607 int ret, idx;
4608 const struct firmware *usbc_pd_fw;
4609 struct amdgpu_bo *fw_buf_bo = NULL;
4610 uint64_t fw_pri_mc_addr;
4611 void *fw_pri_cpu_addr;
4612 struct amdgpu_ip_block *ip_block;
4613
4614 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP);
4615 if (!ip_block || !ip_block->status.late_initialized) {
4616 dev_err(adev->dev, "PSP block is not ready yet.");
4617 return -EBUSY;
4618 }
4619
4620 if (!drm_dev_enter(ddev, &idx))
4621 return -ENODEV;
4622
4623 ret = amdgpu_ucode_request(adev, &usbc_pd_fw, AMDGPU_UCODE_REQUIRED,
4624 "amdgpu/%s", buf);
4625 if (ret)
4626 goto fail;
4627
4628 /* LFB address which is aligned to 1MB boundary per PSP request */
4629 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000,
4630 AMDGPU_GEM_DOMAIN_VRAM |
4631 AMDGPU_GEM_DOMAIN_GTT,
4632 &fw_buf_bo, &fw_pri_mc_addr,
4633 &fw_pri_cpu_addr);
4634 if (ret)
4635 goto rel_buf;
4636
4637 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size);
4638
4639 mutex_lock(&adev->psp.mutex);
4640 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr);
4641 mutex_unlock(&adev->psp.mutex);
4642
4643 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
4644
4645rel_buf:
4646 amdgpu_ucode_release(&usbc_pd_fw);
4647fail:
4648 if (ret) {
4649 dev_err(adev->dev, "Failed to load USBC PD FW, err = %d", ret);
4650 count = ret;
4651 }
4652
4653 drm_dev_exit(idx);
4654 return count;
4655}
4656
4657int psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size)
4658{
4659 int idx;
4660
4661 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx))
4662 return -ENODEV;
4663
4664 if (!bin_size || bin_size > PSP_1_MEG) {
4665 dev_err(psp->adev->dev, "PSP firmware is invalid\n");
4666 drm_dev_exit(idx);
4667 return -EINVAL;
4668 }
4669
4670 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
4671 memcpy(psp->fw_pri_buf, start_addr, bin_size);
4672
4673 drm_dev_exit(idx);
4674 return 0;
4675}
4676
4677/**
4678 * DOC: usbc_pd_fw
4679 * Reading from this file will retrieve the USB-C PD firmware version. Writing to
4680 * this file will trigger the update process.
4681 */
4682static DEVICE_ATTR(usbc_pd_fw, 0644,
4683 psp_usbc_pd_fw_sysfs_read,
4684 psp_usbc_pd_fw_sysfs_write);
4685/**
4686 * DOC: PTL sysfs attributes
4687 * These sysfs files under /sys/class/drm/cardX/device/ptl allow users to enable or disable
4688 * the Peak Tops Limiter (PTL), configure preferred PTL data formats, and query supported
4689 * formats for each GPU.
4690 */
4691static DEVICE_ATTR(ptl_enable, 0644,
4692 ptl_enable_show, ptl_enable_store);
4693static DEVICE_ATTR(ptl_format, 0644,
4694 ptl_format_show, ptl_format_store);
4695static DEVICE_ATTR(ptl_supported_formats, 0444,
4696 ptl_supported_formats_show, NULL);
4697
4698static struct attribute *ptl_attrs[] = {
4699 &dev_attr_ptl_enable.attr,
4700 &dev_attr_ptl_format.attr,
4701 &dev_attr_ptl_supported_formats.attr,
4702 NULL,
4703};
4704
4705const struct attribute_group amdgpu_ptl_attr_group = {
4706 .name = "ptl",
4707 .attrs = ptl_attrs,
4708 .is_visible = amdgpu_ptl_is_visible,
4709};
4710
4711int is_psp_fw_valid(struct psp_bin_desc bin)
4712{
4713 return bin.size_bytes;
4714}
4715
4716static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj,
4717 const struct bin_attribute *bin_attr,
4718 char *buffer, loff_t pos, size_t count)
4719{
4720 struct device *dev = kobj_to_dev(kobj);
4721 struct drm_device *ddev = dev_get_drvdata(dev);
4722 struct amdgpu_device *adev = drm_to_adev(ddev);
4723
4724 adev->psp.vbflash_done = false;
4725
4726 /* Safeguard against memory drain */
4727 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) {
4728 dev_err(adev->dev, "File size cannot exceed %u\n", AMD_VBIOS_FILE_MAX_SIZE_B);
4729 kvfree(adev->psp.vbflash_tmp_buf);
4730 adev->psp.vbflash_tmp_buf = NULL;
4731 adev->psp.vbflash_image_size = 0;
4732 return -ENOMEM;
4733 }
4734
4735 mutex_lock(&adev->psp.mutex);
4736
4737 /* TODO Just allocate max for now and optimize to realloc later if needed */
4738 if (!adev->psp.vbflash_tmp_buf) {
4739 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL);
4740 if (!adev->psp.vbflash_tmp_buf) {
4741 mutex_unlock(&adev->psp.mutex);
4742 return -ENOMEM;
4743 }
4744 }
4745
4746 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count);
4747 adev->psp.vbflash_image_size += count;
4748 mutex_unlock(&adev->psp.mutex);
4749
4750 dev_dbg(adev->dev, "IFWI staged for update\n");
4751
4752 return count;
4753}
4754
4755static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj,
4756 const struct bin_attribute *bin_attr, char *buffer,
4757 loff_t pos, size_t count)
4758{
4759 struct device *dev = kobj_to_dev(kobj);
4760 struct drm_device *ddev = dev_get_drvdata(dev);
4761 struct amdgpu_device *adev = drm_to_adev(ddev);
4762 struct amdgpu_bo *fw_buf_bo = NULL;
4763 uint64_t fw_pri_mc_addr;
4764 void *fw_pri_cpu_addr;
4765 int ret;
4766
4767 if (adev->psp.vbflash_image_size == 0)
4768 return -EINVAL;
4769
4770 dev_dbg(adev->dev, "PSP IFWI flash process initiated\n");
4771
4772 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size,
4773 AMDGPU_GPU_PAGE_SIZE,
4774 AMDGPU_GEM_DOMAIN_VRAM,
4775 &fw_buf_bo,
4776 &fw_pri_mc_addr,
4777 &fw_pri_cpu_addr);
4778 if (ret)
4779 goto rel_buf;
4780
4781 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size);
4782
4783 mutex_lock(&adev->psp.mutex);
4784 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr);
4785 mutex_unlock(&adev->psp.mutex);
4786
4787 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
4788
4789rel_buf:
4790 kvfree(adev->psp.vbflash_tmp_buf);
4791 adev->psp.vbflash_tmp_buf = NULL;
4792 adev->psp.vbflash_image_size = 0;
4793
4794 if (ret) {
4795 dev_err(adev->dev, "Failed to load IFWI, err = %d\n", ret);
4796 return ret;
4797 }
4798
4799 dev_dbg(adev->dev, "PSP IFWI flash process done\n");
4800 return 0;
4801}
4802
4803/**
4804 * DOC: psp_vbflash
4805 * Writing to this file will stage an IFWI for update. Reading from this file
4806 * will trigger the update process.
4807 */
4808static const struct bin_attribute psp_vbflash_bin_attr = {
4809 .attr = {.name = "psp_vbflash", .mode = 0660},
4810 .size = AMD_VBIOS_FILE_MAX_SIZE_B,
4811 .write = amdgpu_psp_vbflash_write,
4812 .read = amdgpu_psp_vbflash_read,
4813};
4814
4815/**
4816 * DOC: psp_vbflash_status
4817 * The status of the flash process.
4818 * 0: IFWI flash not complete.
4819 * 1: IFWI flash complete.
4820 */
4821static ssize_t amdgpu_psp_vbflash_status(struct device *dev,
4822 struct device_attribute *attr,
4823 char *buf)
4824{
4825 struct drm_device *ddev = dev_get_drvdata(dev);
4826 struct amdgpu_device *adev = drm_to_adev(ddev);
4827 uint32_t vbflash_status;
4828
4829 vbflash_status = psp_vbflash_status(&adev->psp);
4830 if (!adev->psp.vbflash_done)
4831 vbflash_status = 0;
4832 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000))
4833 vbflash_status = 1;
4834
4835 return sysfs_emit(buf, "0x%x\n", vbflash_status);
4836}
4837static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL);
4838
4839static const struct bin_attribute *const bin_flash_attrs[] = {
4840 &psp_vbflash_bin_attr,
4841 NULL
4842};
4843
4844static struct attribute *flash_attrs[] = {
4845 &dev_attr_psp_vbflash_status.attr,
4846 &dev_attr_usbc_pd_fw.attr,
4847 NULL
4848};
4849
4850static umode_t amdgpu_flash_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx)
4851{
4852 struct device *dev = kobj_to_dev(kobj);
4853 struct drm_device *ddev = dev_get_drvdata(dev);
4854 struct amdgpu_device *adev = drm_to_adev(ddev);
4855
4856 if (attr == &dev_attr_usbc_pd_fw.attr)
4857 return adev->psp.sup_pd_fw_up ? 0660 : 0;
4858
4859 return adev->psp.sup_ifwi_up ? 0440 : 0;
4860}
4861
4862static umode_t amdgpu_bin_flash_attr_is_visible(struct kobject *kobj,
4863 const struct bin_attribute *attr,
4864 int idx)
4865{
4866 struct device *dev = kobj_to_dev(kobj);
4867 struct drm_device *ddev = dev_get_drvdata(dev);
4868 struct amdgpu_device *adev = drm_to_adev(ddev);
4869
4870 return adev->psp.sup_ifwi_up ? 0660 : 0;
4871}
4872
4873const struct attribute_group amdgpu_flash_attr_group = {
4874 .attrs = flash_attrs,
4875 .bin_attrs = bin_flash_attrs,
4876 .is_bin_visible = amdgpu_bin_flash_attr_is_visible,
4877 .is_visible = amdgpu_flash_attr_is_visible,
4878};
4879
4880#if defined(CONFIG_DEBUG_FS)
4881static int psp_read_spirom_debugfs_open(struct inode *inode, struct file *filp)
4882{
4883 struct amdgpu_device *adev = filp->f_inode->i_private;
4884 struct spirom_bo *bo_triplet;
4885 int ret;
4886
4887 /* serialize the open() file calling */
4888 if (!mutex_trylock(&adev->psp.mutex))
4889 return -EBUSY;
4890
4891 /*
4892 * make sure only one userpace process is alive for dumping so that
4893 * only one memory buffer of AMD_VBIOS_FILE_MAX_SIZE * 2 is consumed.
4894 * let's say the case where one process try opening the file while
4895 * another one has proceeded to read or release. In this way, eliminate
4896 * the use of mutex for read() or release() callback as well.
4897 */
4898 if (adev->psp.spirom_dump_trip) {
4899 mutex_unlock(&adev->psp.mutex);
4900 return -EBUSY;
4901 }
4902
4903 bo_triplet = kzalloc_obj(struct spirom_bo);
4904 if (!bo_triplet) {
4905 mutex_unlock(&adev->psp.mutex);
4906 return -ENOMEM;
4907 }
4908
4909 ret = amdgpu_bo_create_kernel(adev, AMD_VBIOS_FILE_MAX_SIZE_B * 2,
4910 AMDGPU_GPU_PAGE_SIZE,
4911 AMDGPU_GEM_DOMAIN_GTT,
4912 &bo_triplet->bo,
4913 &bo_triplet->mc_addr,
4914 &bo_triplet->cpu_addr);
4915 if (ret)
4916 goto rel_trip;
4917
4918 ret = psp_dump_spirom(&adev->psp, bo_triplet->mc_addr);
4919 if (ret)
4920 goto rel_bo;
4921
4922 adev->psp.spirom_dump_trip = bo_triplet;
4923 mutex_unlock(&adev->psp.mutex);
4924 return 0;
4925rel_bo:
4926 amdgpu_bo_free_kernel(&bo_triplet->bo, &bo_triplet->mc_addr,
4927 &bo_triplet->cpu_addr);
4928rel_trip:
4929 kfree(bo_triplet);
4930 mutex_unlock(&adev->psp.mutex);
4931 dev_err(adev->dev, "Trying IFWI dump fails, err = %d\n", ret);
4932 return ret;
4933}
4934
4935static ssize_t psp_read_spirom_debugfs_read(struct file *filp, char __user *buf, size_t size,
4936 loff_t *pos)
4937{
4938 struct amdgpu_device *adev = filp->f_inode->i_private;
4939 struct spirom_bo *bo_triplet = adev->psp.spirom_dump_trip;
4940
4941 if (!bo_triplet)
4942 return -EINVAL;
4943
4944 return simple_read_from_buffer(buf,
4945 size,
4946 pos, bo_triplet->cpu_addr,
4947 AMD_VBIOS_FILE_MAX_SIZE_B * 2);
4948}
4949
4950static int psp_read_spirom_debugfs_release(struct inode *inode, struct file *filp)
4951{
4952 struct amdgpu_device *adev = filp->f_inode->i_private;
4953 struct spirom_bo *bo_triplet = adev->psp.spirom_dump_trip;
4954
4955 if (bo_triplet) {
4956 amdgpu_bo_free_kernel(&bo_triplet->bo, &bo_triplet->mc_addr,
4957 &bo_triplet->cpu_addr);
4958 kfree(bo_triplet);
4959 }
4960
4961 adev->psp.spirom_dump_trip = NULL;
4962 return 0;
4963}
4964
4965static const struct file_operations psp_dump_spirom_debugfs_ops = {
4966 .owner = THIS_MODULE,
4967 .open = psp_read_spirom_debugfs_open,
4968 .read = psp_read_spirom_debugfs_read,
4969 .release = psp_read_spirom_debugfs_release,
4970 .llseek = default_llseek,
4971};
4972#endif
4973
4974void amdgpu_psp_debugfs_init(struct amdgpu_device *adev)
4975{
4976#if defined(CONFIG_DEBUG_FS)
4977 struct drm_minor *minor = adev_to_drm(adev)->primary;
4978
4979 debugfs_create_file_size("psp_spirom_dump", 0444, minor->debugfs_root,
4980 adev, &psp_dump_spirom_debugfs_ops, AMD_VBIOS_FILE_MAX_SIZE_B * 2);
4981#endif
4982}
4983
4984const struct amd_ip_funcs psp_ip_funcs = {
4985 .name = "psp",
4986 .early_init = psp_early_init,
4987 .sw_init = psp_sw_init,
4988 .sw_fini = psp_sw_fini,
4989 .hw_init = psp_hw_init,
4990 .hw_fini = psp_hw_fini,
4991 .suspend = psp_suspend,
4992 .resume = psp_resume,
4993 .set_clockgating_state = psp_set_clockgating_state,
4994 .set_powergating_state = psp_set_powergating_state,
4995};
4996
4997const struct amdgpu_ip_block_version psp_v3_1_ip_block = {
4998 .type = AMD_IP_BLOCK_TYPE_PSP,
4999 .major = 3,
5000 .minor = 1,
5001 .rev = 0,
5002 .funcs = &psp_ip_funcs,
5003};
5004
5005const struct amdgpu_ip_block_version psp_v10_0_ip_block = {
5006 .type = AMD_IP_BLOCK_TYPE_PSP,
5007 .major = 10,
5008 .minor = 0,
5009 .rev = 0,
5010 .funcs = &psp_ip_funcs,
5011};
5012
5013const struct amdgpu_ip_block_version psp_v11_0_ip_block = {
5014 .type = AMD_IP_BLOCK_TYPE_PSP,
5015 .major = 11,
5016 .minor = 0,
5017 .rev = 0,
5018 .funcs = &psp_ip_funcs,
5019};
5020
5021const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = {
5022 .type = AMD_IP_BLOCK_TYPE_PSP,
5023 .major = 11,
5024 .minor = 0,
5025 .rev = 8,
5026 .funcs = &psp_ip_funcs,
5027};
5028
5029const struct amdgpu_ip_block_version psp_v12_0_ip_block = {
5030 .type = AMD_IP_BLOCK_TYPE_PSP,
5031 .major = 12,
5032 .minor = 0,
5033 .rev = 0,
5034 .funcs = &psp_ip_funcs,
5035};
5036
5037const struct amdgpu_ip_block_version psp_v13_0_ip_block = {
5038 .type = AMD_IP_BLOCK_TYPE_PSP,
5039 .major = 13,
5040 .minor = 0,
5041 .rev = 0,
5042 .funcs = &psp_ip_funcs,
5043};
5044
5045const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = {
5046 .type = AMD_IP_BLOCK_TYPE_PSP,
5047 .major = 13,
5048 .minor = 0,
5049 .rev = 4,
5050 .funcs = &psp_ip_funcs,
5051};
5052
5053const struct amdgpu_ip_block_version psp_v14_0_ip_block = {
5054 .type = AMD_IP_BLOCK_TYPE_PSP,
5055 .major = 14,
5056 .minor = 0,
5057 .rev = 0,
5058 .funcs = &psp_ip_funcs,
5059};
5060
5061const struct amdgpu_ip_block_version psp_v15_0_ip_block = {
5062 .type = AMD_IP_BLOCK_TYPE_PSP,
5063 .major = 15,
5064 .minor = 0,
5065 .rev = 0,
5066 .funcs = &psp_ip_funcs,
5067};
5068
5069const struct amdgpu_ip_block_version psp_v15_0_8_ip_block = {
5070 .type = AMD_IP_BLOCK_TYPE_PSP,
5071 .major = 15,
5072 .minor = 0,
5073 .rev = 8,
5074 .funcs = &psp_ip_funcs,
5075};