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1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 *
23 */
24#include "amdgpu_reg_access.h"
25#include <linux/debugfs.h>
26#include <linux/list.h>
27#include <linux/module.h>
28#include <linux/uaccess.h>
29#include <linux/reboot.h>
30#include <linux/syscalls.h>
31#include <linux/pm_runtime.h>
32#include <linux/list_sort.h>
33
34#include "amdgpu.h"
35#include "amdgpu_ras.h"
36#include "amdgpu_atomfirmware.h"
37#include "amdgpu_xgmi.h"
38#include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
39#include "nbio_v4_3.h"
40#include "nbif_v6_3_1.h"
41#include "nbio_v7_9.h"
42#include "atom.h"
43#include "amdgpu_reset.h"
44#include "amdgpu_psp.h"
45#include "amdgpu_ras_mgr.h"
46#include "amdgpu_virt_ras_cmd.h"
47
48#ifdef CONFIG_X86_MCE_AMD
49#include <asm/mce.h>
50
51static bool notifier_registered;
52#endif
53static const char *RAS_FS_NAME = "ras";
54
55const char *ras_error_string[] = {
56 "none",
57 "parity",
58 "single_correctable",
59 "multi_uncorrectable",
60 "poison",
61};
62
63const char *ras_block_string[] = {
64 "umc",
65 "sdma",
66 "gfx",
67 "mmhub",
68 "athub",
69 "pcie_bif",
70 "hdp",
71 "xgmi_wafl",
72 "df",
73 "smn",
74 "sem",
75 "mp0",
76 "mp1",
77 "fuse",
78 "mca",
79 "vcn",
80 "jpeg",
81 "ih",
82 "mpio",
83 "mmsch",
84};
85
86const char *ras_mca_block_string[] = {
87 "mca_mp0",
88 "mca_mp1",
89 "mca_mpio",
90 "mca_iohc",
91};
92
93struct amdgpu_ras_block_list {
94 /* ras block link */
95 struct list_head node;
96
97 struct amdgpu_ras_block_object *ras_obj;
98
99 /* set by ras_late_init, cleared by ras_suspend/ras_fini */
100 bool active;
101};
102
103const char *get_ras_block_str(struct ras_common_if *ras_block)
104{
105 if (!ras_block)
106 return "NULL";
107
108 if (ras_block->block >= AMDGPU_RAS_BLOCK_COUNT ||
109 ras_block->block >= ARRAY_SIZE(ras_block_string))
110 return "OUT OF RANGE";
111
112 if (ras_block->block == AMDGPU_RAS_BLOCK__MCA)
113 return ras_mca_block_string[ras_block->sub_block_index];
114
115 return ras_block_string[ras_block->block];
116}
117
118#define ras_block_str(_BLOCK_) \
119 (((_BLOCK_) < ARRAY_SIZE(ras_block_string)) ? ras_block_string[_BLOCK_] : "Out Of Range")
120
121#define ras_err_str(i) (ras_error_string[ffs(i)])
122
123#define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
124
125/* inject address is 52 bits */
126#define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52)
127
128/* typical ECC bad page rate is 1 bad page per 100MB VRAM */
129#define RAS_BAD_PAGE_COVER (100 * 1024 * 1024ULL)
130
131#define BYPASS_ALLOCATED_ADDRESS 0x0
132#define BYPASS_INITIALIZATION_ADDRESS 0x1
133
134enum amdgpu_ras_retire_page_reservation {
135 AMDGPU_RAS_RETIRE_PAGE_RESERVED,
136 AMDGPU_RAS_RETIRE_PAGE_PENDING,
137 AMDGPU_RAS_RETIRE_PAGE_FAULT,
138};
139
140atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
141
142static int amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
143 uint64_t addr);
144static int amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
145 uint64_t addr);
146
147static void amdgpu_ras_critical_region_init(struct amdgpu_device *adev);
148static void amdgpu_ras_critical_region_fini(struct amdgpu_device *adev);
149
150#ifdef CONFIG_X86_MCE_AMD
151static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev);
152static void
153amdgpu_unregister_bad_pages_mca_notifier(struct amdgpu_device *adev);
154struct mce_notifier_adev_list {
155 struct amdgpu_device *devs[MAX_GPU_INSTANCE];
156 int num_gpu;
157};
158static struct mce_notifier_adev_list mce_adev_list;
159#endif
160
161void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
162{
163 if (adev && amdgpu_ras_get_context(adev))
164 amdgpu_ras_get_context(adev)->error_query_ready = ready;
165}
166
167static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
168{
169 if (adev && amdgpu_ras_get_context(adev))
170 return amdgpu_ras_get_context(adev)->error_query_ready;
171
172 return false;
173}
174
175static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address)
176{
177 struct ras_err_data err_data;
178 struct eeprom_table_record err_rec;
179 int ret;
180
181 ret = amdgpu_ras_check_bad_page(adev, address);
182 if (ret == -EINVAL) {
183 dev_warn(adev->dev,
184 "RAS WARN: input address 0x%llx is invalid.\n",
185 address);
186 return -EINVAL;
187 } else if (ret == 1) {
188 dev_warn(adev->dev,
189 "RAS WARN: 0x%llx has already been marked as bad page!\n",
190 address);
191 return 0;
192 }
193
194 ret = amdgpu_ras_error_data_init(&err_data);
195 if (ret)
196 return ret;
197
198 memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
199 err_data.err_addr = &err_rec;
200 amdgpu_umc_fill_error_record(&err_data, address, address, 0, 0);
201
202 if (amdgpu_bad_page_threshold != 0) {
203 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
204 err_data.err_addr_cnt, false);
205 amdgpu_ras_save_bad_pages(adev, NULL);
206 }
207
208 amdgpu_ras_error_data_fini(&err_data);
209
210 dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n");
211 dev_warn(adev->dev, "Clear EEPROM:\n");
212 dev_warn(adev->dev, " echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n");
213
214 return 0;
215}
216
217static int amdgpu_check_address_validity(struct amdgpu_device *adev,
218 uint64_t address, uint64_t flags)
219{
220 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
221 struct amdgpu_vram_block_info blk_info;
222 uint64_t page_pfns[32] = {0};
223 int i, ret, count;
224 bool hit = false;
225
226 if (amdgpu_ip_version(adev, UMC_HWIP, 0) < IP_VERSION(12, 0, 0))
227 return 0;
228
229 if (amdgpu_sriov_vf(adev)) {
230 if (amdgpu_uniras_enabled(adev)) {
231 if (amdgpu_virt_ras_check_address_validity(adev, address, &hit))
232 return -EPERM;
233 if (hit)
234 return -EACCES;
235 } else {
236 if (amdgpu_virt_check_vf_critical_region(adev, address, &hit))
237 return -EPERM;
238 return hit ? -EACCES : 0;
239 }
240 }
241
242 if ((address >= adev->gmc.mc_vram_size) ||
243 (address >= RAS_UMC_INJECT_ADDR_LIMIT))
244 return -EFAULT;
245
246 if (amdgpu_sriov_vf(adev))
247 count = amdgpu_virt_ras_convert_retired_address(adev, address,
248 page_pfns, ARRAY_SIZE(page_pfns));
249 else
250 count = amdgpu_ras_mgr_lookup_bad_pages_in_a_row(adev, address,
251 page_pfns, ARRAY_SIZE(page_pfns));
252
253 if (count <= 0)
254 return -EPERM;
255
256 for (i = 0; i < count; i++) {
257 memset(&blk_info, 0, sizeof(blk_info));
258 ret = amdgpu_vram_mgr_query_address_block_info(&adev->mman.vram_mgr,
259 page_pfns[i] << AMDGPU_GPU_PAGE_SHIFT, &blk_info);
260 if (!ret) {
261 /* The input address that needs to be checked is allocated by
262 * current calling process, so it is necessary to exclude
263 * the calling process.
264 */
265 if ((flags == BYPASS_ALLOCATED_ADDRESS) &&
266 ((blk_info.task.pid != task_pid_nr(current)) ||
267 strncmp(blk_info.task.comm, current->comm, TASK_COMM_LEN)))
268 return -EACCES;
269 else if ((flags == BYPASS_INITIALIZATION_ADDRESS) &&
270 (blk_info.task.pid == con->init_task_pid) &&
271 !strncmp(blk_info.task.comm, con->init_task_comm, TASK_COMM_LEN))
272 return -EACCES;
273 }
274 }
275
276 return 0;
277}
278
279static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
280 size_t size, loff_t *pos)
281{
282 struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
283 struct ras_query_if info = {
284 .head = obj->head,
285 };
286 ssize_t s;
287 char val[128];
288
289 if (amdgpu_ras_query_error_status(obj->adev, &info))
290 return -EINVAL;
291
292 /* Hardware counter will be reset automatically after the query on Vega20 and Arcturus */
293 if (amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) &&
294 amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) {
295 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
296 dev_warn(obj->adev->dev, "Failed to reset error counter and error status");
297 }
298
299 s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
300 "ue", info.ue_count,
301 "ce", info.ce_count);
302 if (*pos >= s)
303 return 0;
304
305 s -= *pos;
306 s = min_t(u64, s, size);
307
308
309 if (copy_to_user(buf, &val[*pos], s))
310 return -EINVAL;
311
312 *pos += s;
313
314 return s;
315}
316
317static const struct file_operations amdgpu_ras_debugfs_ops = {
318 .owner = THIS_MODULE,
319 .read = amdgpu_ras_debugfs_read,
320 .write = NULL,
321 .llseek = default_llseek
322};
323
324static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
325{
326 int i;
327
328 for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
329 *block_id = i;
330 if (strcmp(name, ras_block_string[i]) == 0)
331 return 0;
332 }
333 return -EINVAL;
334}
335
336static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
337 const char __user *buf, size_t size,
338 loff_t *pos, struct ras_debug_if *data)
339{
340 ssize_t s = min_t(u64, 64, size);
341 char str[65];
342 char block_name[33];
343 char err[9] = "ue";
344 int op = -1;
345 int block_id;
346 uint32_t sub_block;
347 u64 address, value;
348 /* default value is 0 if the mask is not set by user */
349 u32 instance_mask = 0;
350
351 if (*pos)
352 return -EINVAL;
353 *pos = size;
354
355 memset(str, 0, sizeof(str));
356 memset(data, 0, sizeof(*data));
357
358 if (copy_from_user(str, buf, s))
359 return -EINVAL;
360
361 if (sscanf(str, "disable %32s", block_name) == 1)
362 op = 0;
363 else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
364 op = 1;
365 else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
366 op = 2;
367 else if (strstr(str, "retire_page") != NULL)
368 op = 3;
369 else if (strstr(str, "check_address") != NULL)
370 op = 4;
371 else if (str[0] && str[1] && str[2] && str[3])
372 /* ascii string, but commands are not matched. */
373 return -EINVAL;
374
375 if (op != -1) {
376 if (op == 3) {
377 if (sscanf(str, "%*s 0x%llx", &address) != 1 &&
378 sscanf(str, "%*s %llu", &address) != 1)
379 return -EINVAL;
380
381 data->op = op;
382 data->inject.address = address;
383
384 return 0;
385 } else if (op == 4) {
386 if (sscanf(str, "%*s 0x%llx 0x%llx", &address, &value) != 2 &&
387 sscanf(str, "%*s %llu %llu", &address, &value) != 2)
388 return -EINVAL;
389
390 data->op = op;
391 data->inject.address = address;
392 data->inject.value = value;
393 return 0;
394 }
395
396 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
397 return -EINVAL;
398
399 data->head.block = block_id;
400 /* only ue, ce and poison errors are supported */
401 if (!memcmp("ue", err, 2))
402 data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
403 else if (!memcmp("ce", err, 2))
404 data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
405 else if (!memcmp("poison", err, 6))
406 data->head.type = AMDGPU_RAS_ERROR__POISON;
407 else
408 return -EINVAL;
409
410 data->op = op;
411
412 if (op == 2) {
413 if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx 0x%x",
414 &sub_block, &address, &value, &instance_mask) != 4 &&
415 sscanf(str, "%*s %*s %*s %u %llu %llu %u",
416 &sub_block, &address, &value, &instance_mask) != 4 &&
417 sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
418 &sub_block, &address, &value) != 3 &&
419 sscanf(str, "%*s %*s %*s %u %llu %llu",
420 &sub_block, &address, &value) != 3)
421 return -EINVAL;
422 data->head.sub_block_index = sub_block;
423 data->inject.address = address;
424 data->inject.value = value;
425 data->inject.instance_mask = instance_mask;
426 }
427 } else {
428 if (size < sizeof(*data))
429 return -EINVAL;
430
431 if (copy_from_user(data, buf, sizeof(*data)))
432 return -EINVAL;
433 }
434
435 return 0;
436}
437
438static void amdgpu_ras_instance_mask_check(struct amdgpu_device *adev,
439 struct ras_debug_if *data)
440{
441 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1;
442 uint32_t mask, inst_mask = data->inject.instance_mask;
443
444 /* no need to set instance mask if there is only one instance */
445 if (num_xcc <= 1 && inst_mask) {
446 data->inject.instance_mask = 0;
447 dev_dbg(adev->dev,
448 "RAS inject mask(0x%x) isn't supported and force it to 0.\n",
449 inst_mask);
450
451 return;
452 }
453
454 switch (data->head.block) {
455 case AMDGPU_RAS_BLOCK__GFX:
456 mask = GENMASK(num_xcc - 1, 0);
457 break;
458 case AMDGPU_RAS_BLOCK__SDMA:
459 mask = GENMASK(adev->sdma.num_instances - 1, 0);
460 break;
461 case AMDGPU_RAS_BLOCK__VCN:
462 case AMDGPU_RAS_BLOCK__JPEG:
463 mask = GENMASK(adev->vcn.num_vcn_inst - 1, 0);
464 break;
465 default:
466 mask = inst_mask;
467 break;
468 }
469
470 /* remove invalid bits in instance mask */
471 data->inject.instance_mask &= mask;
472 if (inst_mask != data->inject.instance_mask)
473 dev_dbg(adev->dev,
474 "Adjust RAS inject mask 0x%x to 0x%x\n",
475 inst_mask, data->inject.instance_mask);
476}
477
478/**
479 * DOC: AMDGPU RAS debugfs control interface
480 *
481 * The control interface accepts struct ras_debug_if which has two members.
482 *
483 * First member: ras_debug_if::head or ras_debug_if::inject.
484 *
485 * head is used to indicate which IP block will be under control.
486 *
487 * head has four members, they are block, type, sub_block_index, name.
488 * block: which IP will be under control.
489 * type: what kind of error will be enabled/disabled/injected.
490 * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
491 * name: the name of IP.
492 *
493 * inject has three more members than head, they are address, value and mask.
494 * As their names indicate, inject operation will write the
495 * value to the address.
496 *
497 * The second member: struct ras_debug_if::op.
498 * It has three kinds of operations.
499 *
500 * - 0: disable RAS on the block. Take ::head as its data.
501 * - 1: enable RAS on the block. Take ::head as its data.
502 * - 2: inject errors on the block. Take ::inject as its data.
503 *
504 * How to use the interface?
505 *
506 * In a program
507 *
508 * Copy the struct ras_debug_if in your code and initialize it.
509 * Write the struct to the control interface.
510 *
511 * From shell
512 *
513 * .. code-block:: bash
514 *
515 * echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
516 * echo "enable <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
517 * echo "inject <block> <error> <sub-block> <address> <value> <mask>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
518 *
519 * Where N, is the card which you want to affect.
520 *
521 * "disable" requires only the block.
522 * "enable" requires the block and error type.
523 * "inject" requires the block, error type, address, and value.
524 *
525 * The block is one of: umc, sdma, gfx, etc.
526 * see ras_block_string[] for details
527 *
528 * The error type is one of: ue, ce and poison where,
529 * ue is multi-uncorrectable
530 * ce is single-correctable
531 * poison is poison
532 *
533 * The sub-block is a the sub-block index, pass 0 if there is no sub-block.
534 * The address and value are hexadecimal numbers, leading 0x is optional.
535 * The mask means instance mask, is optional, default value is 0x1.
536 *
537 * For instance,
538 *
539 * .. code-block:: bash
540 *
541 * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
542 * echo inject umc ce 0 0 0 3 > /sys/kernel/debug/dri/0/ras/ras_ctrl
543 * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
544 *
545 * How to check the result of the operation?
546 *
547 * To check disable/enable, see "ras" features at,
548 * /sys/class/drm/card[0/1/2...]/device/ras/features
549 *
550 * To check inject, see the corresponding error count at,
551 * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count
552 *
553 * .. note::
554 * Operations are only allowed on blocks which are supported.
555 * Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask
556 * to see which blocks support RAS on a particular asic.
557 *
558 */
559static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f,
560 const char __user *buf,
561 size_t size, loff_t *pos)
562{
563 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
564 struct ras_debug_if data;
565 int ret = 0;
566
567 if (!amdgpu_ras_get_error_query_ready(adev)) {
568 dev_warn(adev->dev, "RAS WARN: error injection "
569 "currently inaccessible\n");
570 return size;
571 }
572
573 ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
574 if (ret)
575 return ret;
576
577 if (data.op == 3) {
578 ret = amdgpu_reserve_page_direct(adev, data.inject.address);
579 if (!ret)
580 return size;
581 else
582 return ret;
583 } else if (data.op == 4) {
584 ret = amdgpu_check_address_validity(adev, data.inject.address, data.inject.value);
585 return ret ? ret : size;
586 }
587
588 if (!amdgpu_ras_is_supported(adev, data.head.block))
589 return -EINVAL;
590
591 switch (data.op) {
592 case 0:
593 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
594 break;
595 case 1:
596 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
597 break;
598 case 2:
599 /*
600 * UMC ce/ue error injection for a bad page is not allowed. For
601 * uniras (SMU v13+) devices the injection address is validated by
602 * the ras_mgr inject handler, so only run the legacy bad page
603 * check for the legacy RAS path.
604 */
605 if (data.head.block == AMDGPU_RAS_BLOCK__UMC &&
606 !amdgpu_uniras_enabled(adev))
607 ret = amdgpu_ras_check_bad_page(adev, data.inject.address);
608 if (ret == -EINVAL) {
609 dev_warn(adev->dev, "RAS WARN: input address 0x%llx is invalid.",
610 data.inject.address);
611 break;
612 } else if (ret == 1) {
613 dev_warn(adev->dev, "RAS WARN: inject: 0x%llx has already been marked as bad!\n",
614 data.inject.address);
615 break;
616 }
617
618 amdgpu_ras_instance_mask_check(adev, &data);
619
620 /* data.inject.address is offset instead of absolute gpu address */
621 ret = amdgpu_ras_error_inject(adev, &data.inject);
622 break;
623 default:
624 ret = -EINVAL;
625 break;
626 }
627
628 if (ret)
629 return ret;
630
631 return size;
632}
633
634static int amdgpu_uniras_clear_badpages_info(struct amdgpu_device *adev);
635
636/**
637 * DOC: AMDGPU RAS debugfs EEPROM table reset interface
638 *
639 * Some boards contain an EEPROM which is used to persistently store a list of
640 * bad pages which experiences ECC errors in vram. This interface provides
641 * a way to reset the EEPROM, e.g., after testing error injection.
642 *
643 * Usage:
644 *
645 * .. code-block:: bash
646 *
647 * echo 1 > ../ras/ras_eeprom_reset
648 *
649 * will reset EEPROM table to 0 entries.
650 *
651 */
652static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f,
653 const char __user *buf,
654 size_t size, loff_t *pos)
655{
656 struct amdgpu_device *adev =
657 (struct amdgpu_device *)file_inode(f)->i_private;
658 int ret;
659
660 if (amdgpu_uniras_enabled(adev)) {
661 ret = amdgpu_uniras_clear_badpages_info(adev);
662 return ret ? ret : size;
663 }
664
665 ret = amdgpu_ras_eeprom_reset_table(
666 &(amdgpu_ras_get_context(adev)->eeprom_control));
667
668 if (!ret) {
669 /* Something was written to EEPROM.
670 */
671 amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS;
672 return size;
673 } else {
674 return ret;
675 }
676}
677
678static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
679 .owner = THIS_MODULE,
680 .read = NULL,
681 .write = amdgpu_ras_debugfs_ctrl_write,
682 .llseek = default_llseek
683};
684
685static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
686 .owner = THIS_MODULE,
687 .read = NULL,
688 .write = amdgpu_ras_debugfs_eeprom_write,
689 .llseek = default_llseek
690};
691
692/**
693 * DOC: AMDGPU RAS sysfs Error Count Interface
694 *
695 * It allows the user to read the error count for each IP block on the gpu through
696 * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
697 *
698 * It outputs the multiple lines which report the uncorrected (ue) and corrected
699 * (ce) error counts.
700 *
701 * The format of one line is below,
702 *
703 * [ce|ue]: count
704 *
705 * Example:
706 *
707 * .. code-block:: bash
708 *
709 * ue: 0
710 * ce: 1
711 *
712 */
713static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
714 struct device_attribute *attr, char *buf)
715{
716 struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
717 struct ras_query_if info = {
718 .head = obj->head,
719 };
720
721 if (!amdgpu_ras_get_error_query_ready(obj->adev))
722 return sysfs_emit(buf, "Query currently inaccessible\n");
723
724 if (amdgpu_ras_query_error_status(obj->adev, &info))
725 return -EINVAL;
726
727 if (amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) &&
728 amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) {
729 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
730 dev_warn(obj->adev->dev, "Failed to reset error counter and error status");
731 }
732
733 if (info.head.block == AMDGPU_RAS_BLOCK__UMC)
734 return sysfs_emit(buf, "%s: %lu\n%s: %lu\n%s: %lu\n", "ue", info.ue_count,
735 "ce", info.ce_count, "de", info.de_count);
736 else
737 return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count,
738 "ce", info.ce_count);
739}
740
741/* obj begin */
742
743#define get_obj(obj) do { (obj)->use++; } while (0)
744#define alive_obj(obj) ((obj)->use)
745
746static inline void put_obj(struct ras_manager *obj)
747{
748 if (obj && (--obj->use == 0)) {
749 list_del(&obj->node);
750 amdgpu_ras_error_data_fini(&obj->err_data);
751 }
752
753 if (obj && (obj->use < 0))
754 DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", get_ras_block_str(&obj->head));
755}
756
757/* make one obj and return it. */
758static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
759 struct ras_common_if *head)
760{
761 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
762 struct ras_manager *obj;
763
764 if (!adev->ras_enabled || !con)
765 return NULL;
766
767 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
768 return NULL;
769
770 if (head->block == AMDGPU_RAS_BLOCK__MCA) {
771 if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
772 return NULL;
773
774 obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
775 } else
776 obj = &con->objs[head->block];
777
778 /* already exist. return obj? */
779 if (alive_obj(obj))
780 return NULL;
781
782 if (amdgpu_ras_error_data_init(&obj->err_data))
783 return NULL;
784
785 obj->head = *head;
786 obj->adev = adev;
787 list_add(&obj->node, &con->head);
788 get_obj(obj);
789
790 return obj;
791}
792
793/* return an obj equal to head, or the first when head is NULL */
794struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
795 struct ras_common_if *head)
796{
797 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
798 struct ras_manager *obj;
799 int i;
800
801 if (!adev->ras_enabled || !con)
802 return NULL;
803
804 if (head) {
805 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
806 return NULL;
807
808 if (head->block == AMDGPU_RAS_BLOCK__MCA) {
809 if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
810 return NULL;
811
812 obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
813 } else
814 obj = &con->objs[head->block];
815
816 if (alive_obj(obj))
817 return obj;
818 } else {
819 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT + AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
820 obj = &con->objs[i];
821 if (alive_obj(obj))
822 return obj;
823 }
824 }
825
826 return NULL;
827}
828/* obj end */
829
830/* feature ctl begin */
831static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
832 struct ras_common_if *head)
833{
834 return adev->ras_hw_enabled & BIT(head->block);
835}
836
837static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
838 struct ras_common_if *head)
839{
840 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
841
842 return con->features & BIT(head->block);
843}
844
845/*
846 * if obj is not created, then create one.
847 * set feature enable flag.
848 */
849static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
850 struct ras_common_if *head, int enable)
851{
852 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
853 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
854
855 /* If hardware does not support ras, then do not create obj.
856 * But if hardware support ras, we can create the obj.
857 * Ras framework checks con->hw_supported to see if it need do
858 * corresponding initialization.
859 * IP checks con->support to see if it need disable ras.
860 */
861 if (!amdgpu_ras_is_feature_allowed(adev, head))
862 return 0;
863
864 if (enable) {
865 if (!obj) {
866 obj = amdgpu_ras_create_obj(adev, head);
867 if (!obj)
868 return -EINVAL;
869 } else {
870 /* In case we create obj somewhere else */
871 get_obj(obj);
872 }
873 con->features |= BIT(head->block);
874 } else {
875 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
876 con->features &= ~BIT(head->block);
877 put_obj(obj);
878 }
879 }
880
881 return 0;
882}
883
884/* wrapper of psp_ras_enable_features */
885int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
886 struct ras_common_if *head, bool enable)
887{
888 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
889 union ta_ras_cmd_input *info;
890 int ret;
891
892 if (!con)
893 return -EINVAL;
894
895 /* For non-gfx ip, do not enable ras feature if it is not allowed */
896 /* For gfx ip, regardless of feature support status, */
897 /* Force issue enable or disable ras feature commands */
898 if (head->block != AMDGPU_RAS_BLOCK__GFX &&
899 !amdgpu_ras_is_feature_allowed(adev, head))
900 return 0;
901
902 /* Only enable gfx ras feature from host side */
903 if (head->block == AMDGPU_RAS_BLOCK__GFX &&
904 !amdgpu_sriov_vf(adev) &&
905 !amdgpu_ras_intr_triggered()) {
906 info = kzalloc_obj(union ta_ras_cmd_input);
907 if (!info)
908 return -ENOMEM;
909
910 if (!enable) {
911 info->disable_features = (struct ta_ras_disable_features_input) {
912 .block_id = amdgpu_ras_block_to_ta(head->block),
913 .error_type = amdgpu_ras_error_to_ta(head->type),
914 };
915 } else {
916 info->enable_features = (struct ta_ras_enable_features_input) {
917 .block_id = amdgpu_ras_block_to_ta(head->block),
918 .error_type = amdgpu_ras_error_to_ta(head->type),
919 };
920 }
921
922 ret = psp_ras_enable_features(&adev->psp, info, enable);
923 if (ret) {
924 dev_err(adev->dev, "ras %s %s failed poison:%d ret:%d\n",
925 enable ? "enable":"disable",
926 get_ras_block_str(head),
927 amdgpu_ras_is_poison_mode_supported(adev), ret);
928 kfree(info);
929 return ret;
930 }
931
932 kfree(info);
933 }
934
935 /* setup the obj */
936 __amdgpu_ras_feature_enable(adev, head, enable);
937
938 return 0;
939}
940
941/* Only used in device probe stage and called only once. */
942int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
943 struct ras_common_if *head, bool enable)
944{
945 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
946 int ret;
947
948 if (!con)
949 return -EINVAL;
950
951 if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
952 if (enable) {
953 /* There is no harm to issue a ras TA cmd regardless of
954 * the currecnt ras state.
955 * If current state == target state, it will do nothing
956 * But sometimes it requests driver to reset and repost
957 * with error code -EAGAIN.
958 */
959 ret = amdgpu_ras_feature_enable(adev, head, 1);
960 /* With old ras TA, we might fail to enable ras.
961 * Log it and just setup the object.
962 * TODO need remove this WA in the future.
963 */
964 if (ret == -EINVAL) {
965 ret = __amdgpu_ras_feature_enable(adev, head, 1);
966 if (!ret)
967 dev_info(adev->dev,
968 "RAS INFO: %s setup object\n",
969 get_ras_block_str(head));
970 }
971 } else {
972 /* setup the object then issue a ras TA disable cmd.*/
973 ret = __amdgpu_ras_feature_enable(adev, head, 1);
974 if (ret)
975 return ret;
976
977 /* gfx block ras disable cmd must send to ras-ta */
978 if (head->block == AMDGPU_RAS_BLOCK__GFX)
979 con->features |= BIT(head->block);
980
981 ret = amdgpu_ras_feature_enable(adev, head, 0);
982
983 /* clean gfx block ras features flag */
984 if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX)
985 con->features &= ~BIT(head->block);
986 }
987 } else
988 ret = amdgpu_ras_feature_enable(adev, head, enable);
989
990 return ret;
991}
992
993static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
994 bool bypass)
995{
996 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
997 struct ras_manager *obj, *tmp;
998
999 list_for_each_entry_safe(obj, tmp, &con->head, node) {
1000 /* bypass psp.
1001 * aka just release the obj and corresponding flags
1002 */
1003 if (bypass) {
1004 if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
1005 break;
1006 } else {
1007 if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
1008 break;
1009 }
1010 }
1011
1012 return con->features;
1013}
1014
1015static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
1016 bool bypass)
1017{
1018 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1019 int i;
1020 const enum amdgpu_ras_error_type default_ras_type = AMDGPU_RAS_ERROR__NONE;
1021
1022 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
1023 struct ras_common_if head = {
1024 .block = i,
1025 .type = default_ras_type,
1026 .sub_block_index = 0,
1027 };
1028
1029 if (i == AMDGPU_RAS_BLOCK__MCA)
1030 continue;
1031
1032 if (bypass) {
1033 /*
1034 * bypass psp. vbios enable ras for us.
1035 * so just create the obj
1036 */
1037 if (__amdgpu_ras_feature_enable(adev, &head, 1))
1038 break;
1039 } else {
1040 if (amdgpu_ras_feature_enable(adev, &head, 1))
1041 break;
1042 }
1043 }
1044
1045 for (i = 0; i < AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
1046 struct ras_common_if head = {
1047 .block = AMDGPU_RAS_BLOCK__MCA,
1048 .type = default_ras_type,
1049 .sub_block_index = i,
1050 };
1051
1052 if (bypass) {
1053 /*
1054 * bypass psp. vbios enable ras for us.
1055 * so just create the obj
1056 */
1057 if (__amdgpu_ras_feature_enable(adev, &head, 1))
1058 break;
1059 } else {
1060 if (amdgpu_ras_feature_enable(adev, &head, 1))
1061 break;
1062 }
1063 }
1064
1065 return con->features;
1066}
1067/* feature ctl end */
1068
1069static int amdgpu_ras_block_match_default(struct amdgpu_ras_block_object *block_obj,
1070 enum amdgpu_ras_block block)
1071{
1072 if (!block_obj)
1073 return -EINVAL;
1074
1075 if (block_obj->ras_comm.block == block)
1076 return 0;
1077
1078 return -EINVAL;
1079}
1080
1081static struct amdgpu_ras_block_object *amdgpu_ras_get_ras_block(struct amdgpu_device *adev,
1082 enum amdgpu_ras_block block, uint32_t sub_block_index)
1083{
1084 struct amdgpu_ras_block_list *node, *tmp;
1085 struct amdgpu_ras_block_object *obj;
1086
1087 if (block >= AMDGPU_RAS_BLOCK__LAST)
1088 return NULL;
1089
1090 list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
1091 if (!node->ras_obj) {
1092 dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
1093 continue;
1094 }
1095
1096 obj = node->ras_obj;
1097 if (obj->ras_block_match) {
1098 if (obj->ras_block_match(obj, block, sub_block_index) == 0)
1099 return obj;
1100 } else {
1101 if (amdgpu_ras_block_match_default(obj, block) == 0)
1102 return obj;
1103 }
1104 }
1105
1106 return NULL;
1107}
1108
1109static void amdgpu_ras_get_ecc_info(struct amdgpu_device *adev, struct ras_err_data *err_data)
1110{
1111 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1112 int ret = 0;
1113
1114 /*
1115 * choosing right query method according to
1116 * whether smu support query error information
1117 */
1118 ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(ras->umc_ecc));
1119 if (ret == -EOPNOTSUPP) {
1120 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
1121 adev->umc.ras->ras_block.hw_ops->query_ras_error_count)
1122 adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data);
1123
1124 /* umc query_ras_error_address is also responsible for clearing
1125 * error status
1126 */
1127 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
1128 adev->umc.ras->ras_block.hw_ops->query_ras_error_address)
1129 adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, err_data);
1130 } else if (!ret) {
1131 if (adev->umc.ras &&
1132 adev->umc.ras->ecc_info_query_ras_error_count)
1133 adev->umc.ras->ecc_info_query_ras_error_count(adev, err_data);
1134
1135 if (adev->umc.ras &&
1136 adev->umc.ras->ecc_info_query_ras_error_address)
1137 adev->umc.ras->ecc_info_query_ras_error_address(adev, err_data);
1138 }
1139}
1140
1141static void amdgpu_ras_error_print_error_data(struct amdgpu_device *adev,
1142 struct ras_manager *ras_mgr,
1143 struct ras_err_data *err_data,
1144 struct ras_query_context *qctx,
1145 const char *blk_name,
1146 bool is_ue)
1147{
1148 struct amdgpu_smuio_mcm_config_info *mcm_info;
1149 struct ras_err_node *err_node;
1150 struct ras_err_info *err_info;
1151 u64 event_id = qctx->evid.event_id;
1152
1153 if (is_ue) {
1154 for_each_ras_error(err_node, err_data) {
1155 err_info = &err_node->err_info;
1156 mcm_info = &err_info->mcm_info;
1157 if (err_info->ue_count) {
1158 RAS_EVENT_LOG(adev, event_id, "socket: %d, die: %d, "
1159 "%lld new uncorrectable hardware errors detected in %s block\n",
1160 mcm_info->socket_id,
1161 mcm_info->die_id,
1162 err_info->ue_count,
1163 blk_name);
1164 }
1165 }
1166
1167 for_each_ras_error(err_node, &ras_mgr->err_data) {
1168 err_info = &err_node->err_info;
1169 mcm_info = &err_info->mcm_info;
1170 RAS_EVENT_LOG(adev, event_id, "socket: %d, die: %d, "
1171 "%lld uncorrectable hardware errors detected in total in %s block\n",
1172 mcm_info->socket_id, mcm_info->die_id, err_info->ue_count, blk_name);
1173 }
1174
1175 } else {
1176 if (adev->debug_disable_ce_logs)
1177 return;
1178
1179 for_each_ras_error(err_node, err_data) {
1180 err_info = &err_node->err_info;
1181 mcm_info = &err_info->mcm_info;
1182 if (err_info->ce_count) {
1183 RAS_EVENT_LOG(adev, event_id, "socket: %d, die: %d, "
1184 "%lld new correctable hardware errors detected in %s block\n",
1185 mcm_info->socket_id,
1186 mcm_info->die_id,
1187 err_info->ce_count,
1188 blk_name);
1189 }
1190 }
1191
1192 for_each_ras_error(err_node, &ras_mgr->err_data) {
1193 err_info = &err_node->err_info;
1194 mcm_info = &err_info->mcm_info;
1195 RAS_EVENT_LOG(adev, event_id, "socket: %d, die: %d, "
1196 "%lld correctable hardware errors detected in total in %s block\n",
1197 mcm_info->socket_id, mcm_info->die_id,
1198 err_info->ce_count, blk_name);
1199 }
1200 }
1201}
1202
1203static inline bool err_data_has_source_info(struct ras_err_data *data)
1204{
1205 return !list_empty(&data->err_node_list);
1206}
1207
1208static void amdgpu_ras_error_generate_report(struct amdgpu_device *adev,
1209 struct ras_query_if *query_if,
1210 struct ras_err_data *err_data,
1211 struct ras_query_context *qctx)
1212{
1213 struct ras_manager *ras_mgr = amdgpu_ras_find_obj(adev, &query_if->head);
1214 const char *blk_name = get_ras_block_str(&query_if->head);
1215 u64 event_id = qctx->evid.event_id;
1216
1217 if (err_data->ce_count) {
1218 if (err_data_has_source_info(err_data)) {
1219 amdgpu_ras_error_print_error_data(adev, ras_mgr, err_data, qctx, blk_name, false);
1220 } else if (!adev->aid_mask &&
1221 adev->smuio.funcs &&
1222 adev->smuio.funcs->get_socket_id &&
1223 adev->smuio.funcs->get_die_id) {
1224 RAS_EVENT_LOG(adev, event_id, "socket: %d, die: %d "
1225 "%ld correctable hardware errors "
1226 "detected in %s block\n",
1227 adev->smuio.funcs->get_socket_id(adev),
1228 adev->smuio.funcs->get_die_id(adev),
1229 ras_mgr->err_data.ce_count,
1230 blk_name);
1231 } else {
1232 RAS_EVENT_LOG(adev, event_id, "%ld correctable hardware errors "
1233 "detected in %s block\n",
1234 ras_mgr->err_data.ce_count,
1235 blk_name);
1236 }
1237 }
1238
1239 if (err_data->ue_count) {
1240 if (err_data_has_source_info(err_data)) {
1241 amdgpu_ras_error_print_error_data(adev, ras_mgr, err_data, qctx, blk_name, true);
1242 } else if (!adev->aid_mask &&
1243 adev->smuio.funcs &&
1244 adev->smuio.funcs->get_socket_id &&
1245 adev->smuio.funcs->get_die_id) {
1246 RAS_EVENT_LOG(adev, event_id, "socket: %d, die: %d "
1247 "%ld uncorrectable hardware errors "
1248 "detected in %s block\n",
1249 adev->smuio.funcs->get_socket_id(adev),
1250 adev->smuio.funcs->get_die_id(adev),
1251 ras_mgr->err_data.ue_count,
1252 blk_name);
1253 } else {
1254 RAS_EVENT_LOG(adev, event_id, "%ld uncorrectable hardware errors "
1255 "detected in %s block\n",
1256 ras_mgr->err_data.ue_count,
1257 blk_name);
1258 }
1259 }
1260}
1261
1262static void amdgpu_ras_virt_error_generate_report(struct amdgpu_device *adev,
1263 struct ras_query_if *query_if,
1264 struct ras_err_data *err_data,
1265 struct ras_query_context *qctx)
1266{
1267 unsigned long new_ue, new_ce, new_de;
1268 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &query_if->head);
1269 const char *blk_name = get_ras_block_str(&query_if->head);
1270 u64 event_id = qctx->evid.event_id;
1271
1272 new_ce = err_data->ce_count - obj->err_data.ce_count;
1273 new_ue = err_data->ue_count - obj->err_data.ue_count;
1274 new_de = err_data->de_count - obj->err_data.de_count;
1275
1276 if (new_ce) {
1277 RAS_EVENT_LOG(adev, event_id, "%lu correctable hardware errors "
1278 "detected in %s block\n",
1279 new_ce,
1280 blk_name);
1281 }
1282
1283 if (new_ue) {
1284 RAS_EVENT_LOG(adev, event_id, "%lu uncorrectable hardware errors "
1285 "detected in %s block\n",
1286 new_ue,
1287 blk_name);
1288 }
1289
1290 if (new_de) {
1291 RAS_EVENT_LOG(adev, event_id, "%lu deferred hardware errors "
1292 "detected in %s block\n",
1293 new_de,
1294 blk_name);
1295 }
1296}
1297
1298static void amdgpu_rasmgr_error_data_statistic_update(struct ras_manager *obj, struct ras_err_data *err_data)
1299{
1300 struct ras_err_node *err_node;
1301 struct ras_err_info *err_info;
1302
1303 if (err_data_has_source_info(err_data)) {
1304 for_each_ras_error(err_node, err_data) {
1305 err_info = &err_node->err_info;
1306
1307 amdgpu_ras_error_statistic_ce_count(&obj->err_data,
1308 &err_info->mcm_info, err_info->ce_count);
1309 amdgpu_ras_error_statistic_ue_count(&obj->err_data,
1310 &err_info->mcm_info, err_info->ue_count);
1311 }
1312 } else {
1313 /* for legacy asic path which doesn't has error source info */
1314 obj->err_data.ue_count += err_data->ue_count;
1315 obj->err_data.ce_count += err_data->ce_count;
1316 }
1317}
1318
1319static void amdgpu_ras_mgr_virt_error_data_statistics_update(struct ras_manager *obj,
1320 struct ras_err_data *err_data)
1321{
1322 /* Host reports absolute counts */
1323 obj->err_data.ue_count = err_data->ue_count;
1324 obj->err_data.ce_count = err_data->ce_count;
1325 obj->err_data.de_count = err_data->de_count;
1326}
1327
1328static int amdgpu_ras_query_error_status_helper(struct amdgpu_device *adev,
1329 struct ras_query_if *info,
1330 struct ras_err_data *err_data,
1331 struct ras_query_context *qctx,
1332 unsigned int error_query_mode)
1333{
1334 enum amdgpu_ras_block blk = info ? info->head.block : AMDGPU_RAS_BLOCK_COUNT;
1335 struct amdgpu_ras_block_object *block_obj = NULL;
1336
1337 if (blk == AMDGPU_RAS_BLOCK_COUNT)
1338 return -EINVAL;
1339
1340 if (error_query_mode == AMDGPU_RAS_INVALID_ERROR_QUERY)
1341 return -EINVAL;
1342
1343 if (error_query_mode == AMDGPU_RAS_VIRT_ERROR_COUNT_QUERY) {
1344 return amdgpu_virt_req_ras_err_count(adev, blk, err_data);
1345 } else {
1346 if (info->head.block == AMDGPU_RAS_BLOCK__UMC) {
1347 amdgpu_ras_get_ecc_info(adev, err_data);
1348 } else {
1349 block_obj = amdgpu_ras_get_ras_block(adev, info->head.block, 0);
1350 if (!block_obj || !block_obj->hw_ops) {
1351 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1352 get_ras_block_str(&info->head));
1353 return -EINVAL;
1354 }
1355
1356 if (block_obj->hw_ops->query_ras_error_count)
1357 block_obj->hw_ops->query_ras_error_count(adev, err_data);
1358
1359 if ((info->head.block == AMDGPU_RAS_BLOCK__SDMA) ||
1360 (info->head.block == AMDGPU_RAS_BLOCK__GFX) ||
1361 (info->head.block == AMDGPU_RAS_BLOCK__MMHUB)) {
1362 if (block_obj->hw_ops->query_ras_error_status)
1363 block_obj->hw_ops->query_ras_error_status(adev);
1364 }
1365 }
1366 }
1367
1368 return 0;
1369}
1370
1371/* query/inject/cure begin */
1372static int amdgpu_ras_query_error_status_with_event(struct amdgpu_device *adev,
1373 struct ras_query_if *info,
1374 enum ras_event_type type)
1375{
1376 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1377 struct ras_err_data err_data;
1378 struct ras_query_context qctx;
1379 unsigned int error_query_mode;
1380 int ret;
1381
1382 if (!obj)
1383 return -EINVAL;
1384
1385 ret = amdgpu_ras_error_data_init(&err_data);
1386 if (ret)
1387 return ret;
1388
1389 if (!amdgpu_ras_get_error_query_mode(adev, &error_query_mode))
1390 return -EINVAL;
1391
1392 memset(&qctx, 0, sizeof(qctx));
1393 qctx.evid.type = type;
1394 qctx.evid.event_id = amdgpu_ras_acquire_event_id(adev, type);
1395
1396 if (!down_read_trylock(&adev->reset_domain->sem)) {
1397 ret = -EIO;
1398 goto out_fini_err_data;
1399 }
1400
1401 ret = amdgpu_ras_query_error_status_helper(adev, info,
1402 &err_data,
1403 &qctx,
1404 error_query_mode);
1405 up_read(&adev->reset_domain->sem);
1406 if (ret)
1407 goto out_fini_err_data;
1408
1409 if (error_query_mode != AMDGPU_RAS_VIRT_ERROR_COUNT_QUERY) {
1410 amdgpu_rasmgr_error_data_statistic_update(obj, &err_data);
1411 amdgpu_ras_error_generate_report(adev, info, &err_data, &qctx);
1412 } else {
1413 /* Host provides absolute error counts. First generate the report
1414 * using the previous VF internal count against new host count.
1415 * Then Update VF internal count.
1416 */
1417 amdgpu_ras_virt_error_generate_report(adev, info, &err_data, &qctx);
1418 amdgpu_ras_mgr_virt_error_data_statistics_update(obj, &err_data);
1419 }
1420
1421 info->ue_count = obj->err_data.ue_count;
1422 info->ce_count = obj->err_data.ce_count;
1423
1424out_fini_err_data:
1425 amdgpu_ras_error_data_fini(&err_data);
1426
1427 return ret;
1428}
1429
1430static int amdgpu_uniras_clear_badpages_info(struct amdgpu_device *adev)
1431{
1432 struct ras_cmd_dev_handle req = {0};
1433 int ret;
1434
1435 ret = amdgpu_ras_mgr_handle_ras_cmd(adev, RAS_CMD__CLEAR_BAD_PAGE_INFO,
1436 &req, sizeof(req), NULL, 0);
1437 if (ret) {
1438 dev_err(adev->dev, "Failed to clear bad pages info, ret: %d\n", ret);
1439 return -EINVAL;
1440 }
1441
1442 return 0;
1443}
1444
1445static int amdgpu_uniras_query_block_ecc(struct amdgpu_device *adev,
1446 struct ras_query_if *info)
1447{
1448 struct ras_cmd_block_ecc_info_req req = {0};
1449 struct ras_cmd_block_ecc_info_rsp rsp = {0};
1450 int ret;
1451
1452 if (!info)
1453 return -EINVAL;
1454
1455 req.block_id = info->head.block;
1456 req.subblock_id = info->head.sub_block_index;
1457
1458 ret = amdgpu_ras_mgr_handle_ras_cmd(adev, RAS_CMD__GET_BLOCK_ECC_STATUS,
1459 &req, sizeof(req), &rsp, sizeof(rsp));
1460 if (!ret) {
1461 info->ce_count = rsp.ce_count;
1462 info->ue_count = rsp.ue_count;
1463 info->de_count = rsp.de_count;
1464 }
1465
1466 return ret;
1467}
1468
1469int amdgpu_ras_query_error_status(struct amdgpu_device *adev, struct ras_query_if *info)
1470{
1471 if (amdgpu_uniras_enabled(adev))
1472 return amdgpu_uniras_query_block_ecc(adev, info);
1473 else
1474 return amdgpu_ras_query_error_status_with_event(adev, info, RAS_EVENT_TYPE_INVALID);
1475}
1476
1477int amdgpu_ras_reset_error_count(struct amdgpu_device *adev,
1478 enum amdgpu_ras_block block)
1479{
1480 struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0);
1481
1482 if (!block_obj || !block_obj->hw_ops) {
1483 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1484 ras_block_str(block));
1485 return -EOPNOTSUPP;
1486 }
1487
1488 if (!amdgpu_ras_is_supported(adev, block))
1489 return -EOPNOTSUPP;
1490
1491 if (amdgpu_sriov_vf(adev))
1492 return -EOPNOTSUPP;
1493
1494 /* skip ras error reset in gpu reset */
1495 if (amdgpu_in_reset(adev) || amdgpu_ras_in_recovery(adev))
1496 return -EOPNOTSUPP;
1497
1498 if (block_obj->hw_ops->reset_ras_error_count)
1499 block_obj->hw_ops->reset_ras_error_count(adev);
1500
1501 return 0;
1502}
1503
1504int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
1505 enum amdgpu_ras_block block)
1506{
1507 struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0);
1508
1509 if (amdgpu_ras_reset_error_count(adev, block) == -EOPNOTSUPP)
1510 return 0;
1511
1512 if ((block == AMDGPU_RAS_BLOCK__GFX) ||
1513 (block == AMDGPU_RAS_BLOCK__MMHUB)) {
1514 if (block_obj->hw_ops->reset_ras_error_status)
1515 block_obj->hw_ops->reset_ras_error_status(adev);
1516 }
1517
1518 return 0;
1519}
1520
1521static int amdgpu_uniras_error_inject(struct amdgpu_device *adev,
1522 struct ras_inject_if *info)
1523{
1524 struct ras_cmd_inject_error_req inject_req;
1525 struct ras_cmd_inject_error_rsp rsp;
1526
1527 if (!info)
1528 return -EINVAL;
1529
1530 memset(&inject_req, 0, sizeof(inject_req));
1531 inject_req.block_id = info->head.block;
1532 inject_req.subblock_id = info->head.sub_block_index;
1533 inject_req.address = info->address;
1534 inject_req.error_type = info->head.type;
1535 inject_req.instance_mask = info->instance_mask;
1536 inject_req.method = info->value;
1537
1538 return amdgpu_ras_mgr_handle_ras_cmd(adev, RAS_CMD__INJECT_ERROR,
1539 &inject_req, sizeof(inject_req), &rsp, sizeof(rsp)) ? -EINVAL : 0;
1540}
1541
1542/* wrapper of psp_ras_trigger_error */
1543int amdgpu_ras_error_inject(struct amdgpu_device *adev,
1544 struct ras_inject_if *info)
1545{
1546 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1547 struct ta_ras_trigger_error_input block_info = {
1548 .block_id = amdgpu_ras_block_to_ta(info->head.block),
1549 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
1550 .sub_block_index = info->head.sub_block_index,
1551 .address = info->address,
1552 .value = info->value,
1553 };
1554 int ret = -EINVAL;
1555 struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev,
1556 info->head.block,
1557 info->head.sub_block_index);
1558
1559 if (amdgpu_uniras_enabled(adev))
1560 return amdgpu_uniras_error_inject(adev, info);
1561
1562 /* inject on guest isn't allowed, return success directly */
1563 if (amdgpu_sriov_vf(adev))
1564 return 0;
1565
1566 if (!obj)
1567 return -EINVAL;
1568
1569 if (!block_obj || !block_obj->hw_ops) {
1570 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1571 get_ras_block_str(&info->head));
1572 return -EINVAL;
1573 }
1574
1575 /* Calculate XGMI relative offset */
1576 if (adev->gmc.xgmi.num_physical_nodes > 1 &&
1577 info->head.block != AMDGPU_RAS_BLOCK__GFX) {
1578 block_info.address =
1579 amdgpu_xgmi_get_relative_phy_addr(adev,
1580 block_info.address);
1581 }
1582
1583 if (block_obj->hw_ops->ras_error_inject) {
1584 if (info->head.block == AMDGPU_RAS_BLOCK__GFX)
1585 ret = block_obj->hw_ops->ras_error_inject(adev, info, info->instance_mask);
1586 else /* Special ras_error_inject is defined (e.g: xgmi) */
1587 ret = block_obj->hw_ops->ras_error_inject(adev, &block_info,
1588 info->instance_mask);
1589 } else {
1590 /* default path */
1591 ret = psp_ras_trigger_error(&adev->psp, &block_info, info->instance_mask);
1592 }
1593
1594 if (ret)
1595 dev_err(adev->dev, "ras inject %s failed %d\n",
1596 get_ras_block_str(&info->head), ret);
1597
1598 return ret;
1599}
1600
1601/**
1602 * amdgpu_ras_query_error_count_helper -- Get error counter for specific IP
1603 * @adev: pointer to AMD GPU device
1604 * @ce_count: pointer to an integer to be set to the count of correctible errors.
1605 * @ue_count: pointer to an integer to be set to the count of uncorrectible errors.
1606 * @query_info: pointer to ras_query_if
1607 *
1608 * Return 0 for query success or do nothing, otherwise return an error
1609 * on failures
1610 */
1611static int amdgpu_ras_query_error_count_helper(struct amdgpu_device *adev,
1612 unsigned long *ce_count,
1613 unsigned long *ue_count,
1614 struct ras_query_if *query_info)
1615{
1616 int ret;
1617
1618 if (!query_info)
1619 /* do nothing if query_info is not specified */
1620 return 0;
1621
1622 ret = amdgpu_ras_query_error_status(adev, query_info);
1623 if (ret)
1624 return ret;
1625
1626 *ce_count += query_info->ce_count;
1627 *ue_count += query_info->ue_count;
1628
1629 /* some hardware/IP supports read to clear
1630 * no need to explictly reset the err status after the query call */
1631 if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) &&
1632 amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) {
1633 if (amdgpu_ras_reset_error_status(adev, query_info->head.block))
1634 dev_warn(adev->dev,
1635 "Failed to reset error counter and error status\n");
1636 }
1637
1638 return 0;
1639}
1640
1641/**
1642 * amdgpu_ras_query_error_count -- Get error counts of all IPs or specific IP
1643 * @adev: pointer to AMD GPU device
1644 * @ce_count: pointer to an integer to be set to the count of correctible errors.
1645 * @ue_count: pointer to an integer to be set to the count of uncorrectible
1646 * errors.
1647 * @query_info: pointer to ras_query_if if the query request is only for
1648 * specific ip block; if info is NULL, then the qurey request is for
1649 * all the ip blocks that support query ras error counters/status
1650 *
1651 * If set, @ce_count or @ue_count, count and return the corresponding
1652 * error counts in those integer pointers. Return 0 if the device
1653 * supports RAS. Return -EOPNOTSUPP if the device doesn't support RAS.
1654 */
1655int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
1656 unsigned long *ce_count,
1657 unsigned long *ue_count,
1658 struct ras_query_if *query_info)
1659{
1660 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1661 struct ras_manager *obj;
1662 unsigned long ce, ue;
1663 int ret;
1664
1665 if (!adev->ras_enabled || !con)
1666 return -EOPNOTSUPP;
1667
1668 /* Don't count since no reporting.
1669 */
1670 if (!ce_count && !ue_count)
1671 return 0;
1672
1673 ce = 0;
1674 ue = 0;
1675 if (!query_info) {
1676 /* query all the ip blocks that support ras query interface */
1677 list_for_each_entry(obj, &con->head, node) {
1678 struct ras_query_if info = {
1679 .head = obj->head,
1680 };
1681
1682 ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, &info);
1683 }
1684 } else {
1685 /* query specific ip block */
1686 ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, query_info);
1687 }
1688
1689 if (ret)
1690 return ret;
1691
1692 if (ce_count)
1693 *ce_count = ce;
1694
1695 if (ue_count)
1696 *ue_count = ue;
1697
1698 return 0;
1699}
1700/* query/inject/cure end */
1701
1702
1703/* sysfs begin */
1704
1705static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1706 struct ras_badpage *bps, uint32_t count, uint32_t start);
1707static int amdgpu_uniras_badpages_read(struct amdgpu_device *adev,
1708 struct ras_badpage *bps, uint32_t count, uint32_t start);
1709
1710static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
1711{
1712 switch (flags) {
1713 case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
1714 return "R";
1715 case AMDGPU_RAS_RETIRE_PAGE_PENDING:
1716 return "P";
1717 case AMDGPU_RAS_RETIRE_PAGE_FAULT:
1718 default:
1719 return "F";
1720 }
1721}
1722
1723/**
1724 * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
1725 *
1726 * It allows user to read the bad pages of vram on the gpu through
1727 * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
1728 *
1729 * It outputs multiple lines, and each line stands for one gpu page.
1730 *
1731 * The format of one line is below,
1732 * gpu pfn : gpu page size : flags
1733 *
1734 * gpu pfn and gpu page size are printed in hex format.
1735 * flags can be one of below character,
1736 *
1737 * R: reserved, this gpu page is reserved and not able to use.
1738 *
1739 * P: pending for reserve, this gpu page is marked as bad, will be reserved
1740 * in next window of page_reserve.
1741 *
1742 * F: unable to reserve. this gpu page can't be reserved due to some reasons.
1743 *
1744 * Examples:
1745 *
1746 * .. code-block:: bash
1747 *
1748 * 0x00000001 : 0x00001000 : R
1749 * 0x00000002 : 0x00001000 : P
1750 *
1751 */
1752
1753static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
1754 struct kobject *kobj, const struct bin_attribute *attr,
1755 char *buf, loff_t ppos, size_t count)
1756{
1757 struct amdgpu_ras *con =
1758 container_of(attr, struct amdgpu_ras, badpages_attr);
1759 struct amdgpu_device *adev = con->adev;
1760 const unsigned int element_size =
1761 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
1762 unsigned int start = div64_ul(ppos + element_size - 1, element_size);
1763 unsigned int end = div64_ul(ppos + count - 1, element_size);
1764 ssize_t s = 0;
1765 struct ras_badpage *bps = NULL;
1766 int bps_count = 0, i, status;
1767 uint64_t address;
1768
1769 memset(buf, 0, count);
1770
1771 bps_count = end - start;
1772 bps = kmalloc_objs(*bps, bps_count);
1773 if (!bps)
1774 return 0;
1775
1776 memset(bps, 0, sizeof(*bps) * bps_count);
1777
1778 if (amdgpu_uniras_enabled(adev))
1779 bps_count = amdgpu_uniras_badpages_read(adev, bps, bps_count, start);
1780 else
1781 bps_count = amdgpu_ras_badpages_read(adev, bps, bps_count, start);
1782
1783 if (bps_count <= 0) {
1784 kfree(bps);
1785 return 0;
1786 }
1787
1788 for (i = 0; i < bps_count; i++) {
1789 address = ((uint64_t)bps[i].bp) << AMDGPU_GPU_PAGE_SHIFT;
1790
1791 bps[i].size = AMDGPU_GPU_PAGE_SIZE;
1792
1793 status = amdgpu_vram_mgr_query_page_status(&adev->mman.vram_mgr,
1794 address);
1795 if (status == -EBUSY)
1796 bps[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
1797 else if (status == -ENOENT)
1798 bps[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
1799 else
1800 bps[i].flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED;
1801
1802 if ((bps[i].flags != AMDGPU_RAS_RETIRE_PAGE_RESERVED) &&
1803 amdgpu_ras_check_critical_address(adev, address))
1804 bps[i].flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED;
1805
1806 s += scnprintf(&buf[s], element_size + 1,
1807 "0x%08x : 0x%08x : %1s\n",
1808 bps[i].bp,
1809 bps[i].size,
1810 amdgpu_ras_badpage_flags_str(bps[i].flags));
1811 }
1812
1813 kfree(bps);
1814
1815 return s;
1816}
1817
1818static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
1819 struct device_attribute *attr, char *buf)
1820{
1821 struct amdgpu_ras *con =
1822 container_of(attr, struct amdgpu_ras, features_attr);
1823
1824 return sysfs_emit(buf, "feature mask: 0x%x\n", con->features);
1825}
1826
1827static bool amdgpu_ras_get_version_info(struct amdgpu_device *adev, u32 *major,
1828 u32 *minor, u32 *rev)
1829{
1830 int i;
1831
1832 if (!adev || !major || !minor || !rev || !amdgpu_uniras_enabled(adev))
1833 return false;
1834
1835 for (i = 0; i < adev->num_ip_blocks; i++) {
1836 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_RAS) {
1837 *major = adev->ip_blocks[i].version->major;
1838 *minor = adev->ip_blocks[i].version->minor;
1839 *rev = adev->ip_blocks[i].version->rev;
1840 return true;
1841 }
1842 }
1843
1844 return false;
1845}
1846
1847static ssize_t amdgpu_ras_sysfs_version_show(struct device *dev,
1848 struct device_attribute *attr, char *buf)
1849{
1850 struct amdgpu_ras *con =
1851 container_of(attr, struct amdgpu_ras, version_attr);
1852 u32 major, minor, rev;
1853 ssize_t size = 0;
1854
1855 size += sysfs_emit_at(buf, size, "table version: 0x%x\n",
1856 con->eeprom_control.tbl_hdr.version);
1857
1858 if (amdgpu_ras_get_version_info(con->adev, &major, &minor, &rev))
1859 size += sysfs_emit_at(buf, size, "ras version: %u.%u.%u\n",
1860 major, minor, rev);
1861
1862 return size;
1863}
1864
1865static ssize_t amdgpu_ras_sysfs_schema_show(struct device *dev,
1866 struct device_attribute *attr, char *buf)
1867{
1868 struct amdgpu_ras *con =
1869 container_of(attr, struct amdgpu_ras, schema_attr);
1870 return sysfs_emit(buf, "schema: 0x%x\n", con->schema);
1871}
1872
1873static struct {
1874 enum ras_event_type type;
1875 const char *name;
1876} dump_event[] = {
1877 {RAS_EVENT_TYPE_FATAL, "Fatal Error"},
1878 {RAS_EVENT_TYPE_POISON_CREATION, "Poison Creation"},
1879 {RAS_EVENT_TYPE_POISON_CONSUMPTION, "Poison Consumption"},
1880};
1881
1882static ssize_t amdgpu_ras_sysfs_event_state_show(struct device *dev,
1883 struct device_attribute *attr, char *buf)
1884{
1885 struct amdgpu_ras *con =
1886 container_of(attr, struct amdgpu_ras, event_state_attr);
1887 struct ras_event_manager *event_mgr = con->event_mgr;
1888 struct ras_event_state *event_state;
1889 int i, size = 0;
1890
1891 if (!event_mgr)
1892 return -EINVAL;
1893
1894 size += sysfs_emit_at(buf, size, "current seqno: %llu\n", atomic64_read(&event_mgr->seqno));
1895 for (i = 0; i < ARRAY_SIZE(dump_event); i++) {
1896 event_state = &event_mgr->event_state[dump_event[i].type];
1897 size += sysfs_emit_at(buf, size, "%s: count:%llu, last_seqno:%llu\n",
1898 dump_event[i].name,
1899 atomic64_read(&event_state->count),
1900 event_state->last_seqno);
1901 }
1902
1903 return (ssize_t)size;
1904}
1905
1906static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev)
1907{
1908 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1909
1910 if (adev->dev->kobj.sd)
1911 sysfs_remove_file_from_group(&adev->dev->kobj,
1912 &con->badpages_attr.attr,
1913 RAS_FS_NAME);
1914}
1915
1916static int amdgpu_ras_sysfs_remove_dev_attr_node(struct amdgpu_device *adev)
1917{
1918 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1919 struct attribute *attrs[] = {
1920 &con->features_attr.attr,
1921 &con->version_attr.attr,
1922 &con->schema_attr.attr,
1923 &con->event_state_attr.attr,
1924 NULL
1925 };
1926 struct attribute_group group = {
1927 .name = RAS_FS_NAME,
1928 .attrs = attrs,
1929 };
1930
1931 if (adev->dev->kobj.sd)
1932 sysfs_remove_group(&adev->dev->kobj, &group);
1933
1934 return 0;
1935}
1936
1937int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
1938 struct ras_common_if *head)
1939{
1940 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1941
1942 if (!obj || obj->attr_inuse)
1943 return -EINVAL;
1944
1945 if (amdgpu_sriov_vf(adev) && !amdgpu_virt_ras_telemetry_block_en(adev, head->block))
1946 return 0;
1947
1948 get_obj(obj);
1949
1950 snprintf(obj->fs_data.sysfs_name, sizeof(obj->fs_data.sysfs_name),
1951 "%s_err_count", head->name);
1952
1953 obj->sysfs_attr = (struct device_attribute){
1954 .attr = {
1955 .name = obj->fs_data.sysfs_name,
1956 .mode = S_IRUGO,
1957 },
1958 .show = amdgpu_ras_sysfs_read,
1959 };
1960 sysfs_attr_init(&obj->sysfs_attr.attr);
1961
1962 if (sysfs_add_file_to_group(&adev->dev->kobj,
1963 &obj->sysfs_attr.attr,
1964 RAS_FS_NAME)) {
1965 put_obj(obj);
1966 return -EINVAL;
1967 }
1968
1969 obj->attr_inuse = 1;
1970
1971 return 0;
1972}
1973
1974int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
1975 struct ras_common_if *head)
1976{
1977 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1978
1979 if (!obj || !obj->attr_inuse)
1980 return -EINVAL;
1981
1982 if (adev->dev->kobj.sd)
1983 sysfs_remove_file_from_group(&adev->dev->kobj,
1984 &obj->sysfs_attr.attr,
1985 RAS_FS_NAME);
1986 obj->attr_inuse = 0;
1987 put_obj(obj);
1988
1989 return 0;
1990}
1991
1992static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
1993{
1994 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1995 struct ras_manager *obj, *tmp;
1996
1997 list_for_each_entry_safe(obj, tmp, &con->head, node) {
1998 amdgpu_ras_sysfs_remove(adev, &obj->head);
1999 }
2000
2001 if (amdgpu_bad_page_threshold != 0)
2002 amdgpu_ras_sysfs_remove_bad_page_node(adev);
2003
2004 amdgpu_ras_sysfs_remove_dev_attr_node(adev);
2005
2006 return 0;
2007}
2008/* sysfs end */
2009
2010/**
2011 * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
2012 *
2013 * Normally when there is an uncorrectable error, the driver will reset
2014 * the GPU to recover. However, in the event of an unrecoverable error,
2015 * the driver provides an interface to reboot the system automatically
2016 * in that event.
2017 *
2018 * The following file in debugfs provides that interface:
2019 * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
2020 *
2021 * Usage:
2022 *
2023 * .. code-block:: bash
2024 *
2025 * echo true > .../ras/auto_reboot
2026 *
2027 */
2028/* debugfs begin */
2029static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
2030{
2031 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2032 struct amdgpu_ras_eeprom_control *eeprom = &con->eeprom_control;
2033 struct drm_minor *minor = adev_to_drm(adev)->primary;
2034 struct dentry *dir;
2035
2036 dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root);
2037 debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev,
2038 &amdgpu_ras_debugfs_ctrl_ops);
2039 debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev,
2040 &amdgpu_ras_debugfs_eeprom_ops);
2041 debugfs_create_u32("bad_page_cnt_threshold", 0444, dir,
2042 &con->bad_page_cnt_threshold);
2043 debugfs_create_u32("ras_num_recs", 0444, dir, &eeprom->ras_num_recs);
2044 debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled);
2045 debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled);
2046 debugfs_create_file("ras_eeprom_size", S_IRUGO, dir, adev,
2047 &amdgpu_ras_debugfs_eeprom_size_ops);
2048 con->de_ras_eeprom_table = debugfs_create_file("ras_eeprom_table",
2049 S_IRUGO, dir, adev,
2050 &amdgpu_ras_debugfs_eeprom_table_ops);
2051 amdgpu_ras_debugfs_set_ret_size(&con->eeprom_control);
2052
2053 /*
2054 * After one uncorrectable error happens, usually GPU recovery will
2055 * be scheduled. But due to the known problem in GPU recovery failing
2056 * to bring GPU back, below interface provides one direct way to
2057 * user to reboot system automatically in such case within
2058 * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
2059 * will never be called.
2060 */
2061 debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot);
2062
2063 /*
2064 * User could set this not to clean up hardware's error count register
2065 * of RAS IPs during ras recovery.
2066 */
2067 debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir,
2068 &con->disable_ras_err_cnt_harvest);
2069 return dir;
2070}
2071
2072static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
2073 struct ras_fs_if *head,
2074 struct dentry *dir)
2075{
2076 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
2077
2078 if (!obj || !dir)
2079 return;
2080
2081 get_obj(obj);
2082
2083 memcpy(obj->fs_data.debugfs_name,
2084 head->debugfs_name,
2085 sizeof(obj->fs_data.debugfs_name));
2086
2087 debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir,
2088 obj, &amdgpu_ras_debugfs_ops);
2089}
2090
2091void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
2092{
2093 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2094 struct dentry *dir;
2095 struct ras_manager *obj;
2096 struct ras_fs_if fs_info;
2097
2098 /*
2099 * it won't be called in resume path, no need to check
2100 * suspend and gpu reset status
2101 */
2102 if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con)
2103 return;
2104
2105 dir = amdgpu_ras_debugfs_create_ctrl_node(adev);
2106
2107 list_for_each_entry(obj, &con->head, node) {
2108 if (amdgpu_ras_is_supported(adev, obj->head.block) &&
2109 (obj->attr_inuse == 1)) {
2110 snprintf(fs_info.debugfs_name, sizeof(fs_info.debugfs_name),
2111 "%s_err_inject",
2112 get_ras_block_str(&obj->head));
2113 fs_info.head = obj->head;
2114 amdgpu_ras_debugfs_create(adev, &fs_info, dir);
2115 }
2116 }
2117}
2118
2119/* debugfs end */
2120
2121/* ras fs */
2122static const BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,
2123 amdgpu_ras_sysfs_badpages_read, NULL, 0);
2124static DEVICE_ATTR(features, S_IRUGO,
2125 amdgpu_ras_sysfs_features_read, NULL);
2126static DEVICE_ATTR(version, 0444,
2127 amdgpu_ras_sysfs_version_show, NULL);
2128static DEVICE_ATTR(schema, 0444,
2129 amdgpu_ras_sysfs_schema_show, NULL);
2130static DEVICE_ATTR(event_state, 0444,
2131 amdgpu_ras_sysfs_event_state_show, NULL);
2132static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
2133{
2134 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2135 struct attribute_group group = {
2136 .name = RAS_FS_NAME,
2137 };
2138 struct attribute *attrs[] = {
2139 &con->features_attr.attr,
2140 &con->version_attr.attr,
2141 &con->schema_attr.attr,
2142 &con->event_state_attr.attr,
2143 NULL
2144 };
2145 const struct bin_attribute *bin_attrs[] = {
2146 NULL,
2147 NULL,
2148 };
2149 int r;
2150
2151 group.attrs = attrs;
2152
2153 /* add features entry */
2154 con->features_attr = dev_attr_features;
2155 sysfs_attr_init(attrs[0]);
2156
2157 /* add version entry */
2158 con->version_attr = dev_attr_version;
2159 sysfs_attr_init(attrs[1]);
2160
2161 /* add schema entry */
2162 con->schema_attr = dev_attr_schema;
2163 sysfs_attr_init(attrs[2]);
2164
2165 /* add event_state entry */
2166 con->event_state_attr = dev_attr_event_state;
2167 sysfs_attr_init(attrs[3]);
2168
2169 if (amdgpu_bad_page_threshold != 0) {
2170 /* add bad_page_features entry */
2171 con->badpages_attr = bin_attr_gpu_vram_bad_pages;
2172 sysfs_bin_attr_init(&con->badpages_attr);
2173 bin_attrs[0] = &con->badpages_attr;
2174 group.bin_attrs = bin_attrs;
2175 }
2176
2177 r = sysfs_create_group(&adev->dev->kobj, &group);
2178 if (r)
2179 dev_err(adev->dev, "Failed to create RAS sysfs group!");
2180
2181 return 0;
2182}
2183
2184static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
2185{
2186 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2187 struct ras_manager *con_obj, *ip_obj, *tmp;
2188
2189 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
2190 list_for_each_entry_safe(con_obj, tmp, &con->head, node) {
2191 ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head);
2192 if (ip_obj)
2193 put_obj(ip_obj);
2194 }
2195 }
2196
2197 amdgpu_ras_sysfs_remove_all(adev);
2198 return 0;
2199}
2200/* ras fs end */
2201
2202/* ih begin */
2203
2204/* For the hardware that cannot enable bif ring for both ras_controller_irq
2205 * and ras_err_evnet_athub_irq ih cookies, the driver has to poll status
2206 * register to check whether the interrupt is triggered or not, and properly
2207 * ack the interrupt if it is there
2208 */
2209void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev)
2210{
2211 /* Fatal error events are handled on host side */
2212 if (amdgpu_sriov_vf(adev))
2213 return;
2214 /*
2215 * If the current interrupt is caused by a non-fatal RAS error, skip
2216 * check for fatal error. For fatal errors, FED status of all devices
2217 * in XGMI hive gets set when the first device gets fatal error
2218 * interrupt. The error gets propagated to other devices as well, so
2219 * make sure to ack the interrupt regardless of FED status.
2220 */
2221 if (!amdgpu_ras_get_fed_status(adev) &&
2222 amdgpu_ras_is_err_state(adev, AMDGPU_RAS_BLOCK__ANY))
2223 return;
2224
2225 if (amdgpu_uniras_enabled(adev)) {
2226 amdgpu_ras_mgr_handle_fatal_interrupt(adev, NULL);
2227 return;
2228 }
2229
2230 if (adev->nbio.ras &&
2231 adev->nbio.ras->handle_ras_controller_intr_no_bifring)
2232 adev->nbio.ras->handle_ras_controller_intr_no_bifring(adev);
2233
2234 if (adev->nbio.ras &&
2235 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring)
2236 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring(adev);
2237}
2238
2239static void amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *obj,
2240 struct amdgpu_iv_entry *entry)
2241{
2242 bool poison_stat = false;
2243 struct amdgpu_device *adev = obj->adev;
2244 struct amdgpu_ras_block_object *block_obj =
2245 amdgpu_ras_get_ras_block(adev, obj->head.block, 0);
2246 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2247 enum ras_event_type type = RAS_EVENT_TYPE_POISON_CONSUMPTION;
2248 u64 event_id;
2249 int ret;
2250
2251 if (!block_obj || !con)
2252 return;
2253
2254 ret = amdgpu_ras_mark_ras_event(adev, type);
2255 if (ret)
2256 return;
2257
2258 amdgpu_ras_set_err_poison(adev, block_obj->ras_comm.block);
2259 /* both query_poison_status and handle_poison_consumption are optional,
2260 * but at least one of them should be implemented if we need poison
2261 * consumption handler
2262 */
2263 if (block_obj->hw_ops && block_obj->hw_ops->query_poison_status) {
2264 poison_stat = block_obj->hw_ops->query_poison_status(adev);
2265 if (!poison_stat) {
2266 /* Not poison consumption interrupt, no need to handle it */
2267 dev_info(adev->dev, "No RAS poison status in %s poison IH.\n",
2268 block_obj->ras_comm.name);
2269
2270 return;
2271 }
2272 }
2273
2274 amdgpu_umc_poison_handler(adev, obj->head.block, 0);
2275
2276 if (block_obj->hw_ops && block_obj->hw_ops->handle_poison_consumption)
2277 poison_stat = block_obj->hw_ops->handle_poison_consumption(adev);
2278
2279 /* gpu reset is fallback for failed and default cases.
2280 * For RMA case, amdgpu_umc_poison_handler will handle gpu reset.
2281 */
2282 if (poison_stat && !amdgpu_ras_is_rma(adev)) {
2283 event_id = amdgpu_ras_acquire_event_id(adev, type);
2284 RAS_EVENT_LOG(adev, event_id,
2285 "GPU reset for %s RAS poison consumption is issued!\n",
2286 block_obj->ras_comm.name);
2287 amdgpu_ras_reset_gpu(adev);
2288 }
2289
2290 if (!poison_stat)
2291 amdgpu_gfx_poison_consumption_handler(adev, entry);
2292}
2293
2294static void amdgpu_ras_interrupt_poison_creation_handler(struct ras_manager *obj,
2295 struct amdgpu_iv_entry *entry)
2296{
2297 struct amdgpu_device *adev = obj->adev;
2298 enum ras_event_type type = RAS_EVENT_TYPE_POISON_CREATION;
2299 u64 event_id;
2300 int ret;
2301
2302 ret = amdgpu_ras_mark_ras_event(adev, type);
2303 if (ret)
2304 return;
2305
2306 event_id = amdgpu_ras_acquire_event_id(adev, type);
2307 RAS_EVENT_LOG(adev, event_id, "Poison is created\n");
2308
2309}
2310
2311static void amdgpu_ras_interrupt_umc_handler(struct ras_manager *obj,
2312 struct amdgpu_iv_entry *entry)
2313{
2314 struct ras_ih_data *data = &obj->ih_data;
2315 struct ras_err_data err_data;
2316 int ret;
2317
2318 if (!data->cb)
2319 return;
2320
2321 ret = amdgpu_ras_error_data_init(&err_data);
2322 if (ret)
2323 return;
2324
2325 /* Let IP handle its data, maybe we need get the output
2326 * from the callback to update the error type/count, etc
2327 */
2328 amdgpu_ras_set_fed(obj->adev, true);
2329 ret = data->cb(obj->adev, &err_data, entry);
2330 /* ue will trigger an interrupt, and in that case
2331 * we need do a reset to recovery the whole system.
2332 * But leave IP do that recovery, here we just dispatch
2333 * the error.
2334 */
2335 if (ret == AMDGPU_RAS_SUCCESS) {
2336 /* these counts could be left as 0 if
2337 * some blocks do not count error number
2338 */
2339 obj->err_data.ue_count += err_data.ue_count;
2340 obj->err_data.ce_count += err_data.ce_count;
2341 }
2342
2343 amdgpu_ras_error_data_fini(&err_data);
2344}
2345
2346static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
2347{
2348 struct ras_ih_data *data = &obj->ih_data;
2349 struct amdgpu_iv_entry entry;
2350
2351 while (data->rptr != data->wptr) {
2352 rmb();
2353 memcpy(&entry, &data->ring[data->rptr],
2354 data->element_size);
2355
2356 wmb();
2357 data->rptr = (data->aligned_element_size +
2358 data->rptr) % data->ring_size;
2359
2360 if (amdgpu_ras_is_poison_mode_supported(obj->adev)) {
2361 if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
2362 amdgpu_ras_interrupt_poison_creation_handler(obj, &entry);
2363 else
2364 amdgpu_ras_interrupt_poison_consumption_handler(obj, &entry);
2365 } else {
2366 if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
2367 amdgpu_ras_interrupt_umc_handler(obj, &entry);
2368 else
2369 dev_warn(obj->adev->dev,
2370 "No RAS interrupt handler for non-UMC block with poison disabled.\n");
2371 }
2372 }
2373}
2374
2375static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
2376{
2377 struct ras_ih_data *data =
2378 container_of(work, struct ras_ih_data, ih_work);
2379 struct ras_manager *obj =
2380 container_of(data, struct ras_manager, ih_data);
2381
2382 amdgpu_ras_interrupt_handler(obj);
2383}
2384
2385int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
2386 struct ras_dispatch_if *info)
2387{
2388 struct ras_manager *obj;
2389 struct ras_ih_data *data;
2390
2391 if (amdgpu_uniras_enabled(adev)) {
2392 struct ras_ih_info ih_info;
2393
2394 memset(&ih_info, 0, sizeof(ih_info));
2395 ih_info.block = info->head.block;
2396 memcpy(&ih_info.iv_entry, info->entry, sizeof(struct amdgpu_iv_entry));
2397
2398 return amdgpu_ras_mgr_handle_controller_interrupt(adev, &ih_info);
2399 }
2400
2401 obj = amdgpu_ras_find_obj(adev, &info->head);
2402 if (!obj)
2403 return -EINVAL;
2404
2405 data = &obj->ih_data;
2406
2407 if (data->inuse == 0)
2408 return 0;
2409
2410 /* Might be overflow... */
2411 memcpy(&data->ring[data->wptr], info->entry,
2412 data->element_size);
2413
2414 wmb();
2415 data->wptr = (data->aligned_element_size +
2416 data->wptr) % data->ring_size;
2417
2418 schedule_work(&data->ih_work);
2419
2420 return 0;
2421}
2422
2423int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
2424 struct ras_common_if *head)
2425{
2426 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
2427 struct ras_ih_data *data;
2428
2429 if (!obj)
2430 return -EINVAL;
2431
2432 data = &obj->ih_data;
2433 if (data->inuse == 0)
2434 return 0;
2435
2436 cancel_work_sync(&data->ih_work);
2437
2438 kfree(data->ring);
2439 memset(data, 0, sizeof(*data));
2440 put_obj(obj);
2441
2442 return 0;
2443}
2444
2445int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
2446 struct ras_common_if *head)
2447{
2448 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
2449 struct ras_ih_data *data;
2450 struct amdgpu_ras_block_object *ras_obj;
2451
2452 if (!obj) {
2453 /* in case we registe the IH before enable ras feature */
2454 obj = amdgpu_ras_create_obj(adev, head);
2455 if (!obj)
2456 return -EINVAL;
2457 } else
2458 get_obj(obj);
2459
2460 ras_obj = container_of(head, struct amdgpu_ras_block_object, ras_comm);
2461
2462 data = &obj->ih_data;
2463 /* add the callback.etc */
2464 *data = (struct ras_ih_data) {
2465 .inuse = 0,
2466 .cb = ras_obj->ras_cb,
2467 .element_size = sizeof(struct amdgpu_iv_entry),
2468 .rptr = 0,
2469 .wptr = 0,
2470 };
2471
2472 INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
2473
2474 data->aligned_element_size = ALIGN(data->element_size, 8);
2475 /* the ring can store 64 iv entries. */
2476 data->ring_size = 64 * data->aligned_element_size;
2477 data->ring = kmalloc(data->ring_size, GFP_KERNEL);
2478 if (!data->ring) {
2479 put_obj(obj);
2480 return -ENOMEM;
2481 }
2482
2483 /* IH is ready */
2484 data->inuse = 1;
2485
2486 return 0;
2487}
2488
2489static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
2490{
2491 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2492 struct ras_manager *obj, *tmp;
2493
2494 list_for_each_entry_safe(obj, tmp, &con->head, node) {
2495 amdgpu_ras_interrupt_remove_handler(adev, &obj->head);
2496 }
2497
2498 return 0;
2499}
2500/* ih end */
2501
2502/* traversal all IPs except NBIO to query error counter */
2503static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev, enum ras_event_type type)
2504{
2505 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2506 struct ras_manager *obj;
2507
2508 if (!adev->ras_enabled || !con)
2509 return;
2510
2511 list_for_each_entry(obj, &con->head, node) {
2512 struct ras_query_if info = {
2513 .head = obj->head,
2514 };
2515
2516 /*
2517 * PCIE_BIF IP has one different isr by ras controller
2518 * interrupt, the specific ras counter query will be
2519 * done in that isr. So skip such block from common
2520 * sync flood interrupt isr calling.
2521 */
2522 if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF)
2523 continue;
2524
2525 /*
2526 * this is a workaround for aldebaran, skip send msg to
2527 * smu to get ecc_info table due to smu handle get ecc
2528 * info table failed temporarily.
2529 * should be removed until smu fix handle ecc_info table.
2530 */
2531 if ((info.head.block == AMDGPU_RAS_BLOCK__UMC) &&
2532 (amdgpu_ip_version(adev, MP1_HWIP, 0) ==
2533 IP_VERSION(13, 0, 2)))
2534 continue;
2535
2536 amdgpu_ras_query_error_status_with_event(adev, &info, type);
2537
2538 if (amdgpu_ip_version(adev, MP0_HWIP, 0) !=
2539 IP_VERSION(11, 0, 2) &&
2540 amdgpu_ip_version(adev, MP0_HWIP, 0) !=
2541 IP_VERSION(11, 0, 4) &&
2542 amdgpu_ip_version(adev, MP0_HWIP, 0) !=
2543 IP_VERSION(13, 0, 0)) {
2544 if (amdgpu_ras_reset_error_status(adev, info.head.block))
2545 dev_warn(adev->dev, "Failed to reset error counter and error status");
2546 }
2547 }
2548}
2549
2550/* Parse RdRspStatus and WrRspStatus */
2551static void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
2552 struct ras_query_if *info)
2553{
2554 struct amdgpu_ras_block_object *block_obj;
2555 /*
2556 * Only two block need to query read/write
2557 * RspStatus at current state
2558 */
2559 if ((info->head.block != AMDGPU_RAS_BLOCK__GFX) &&
2560 (info->head.block != AMDGPU_RAS_BLOCK__MMHUB))
2561 return;
2562
2563 block_obj = amdgpu_ras_get_ras_block(adev,
2564 info->head.block,
2565 info->head.sub_block_index);
2566
2567 if (!block_obj || !block_obj->hw_ops) {
2568 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
2569 get_ras_block_str(&info->head));
2570 return;
2571 }
2572
2573 if (block_obj->hw_ops->query_ras_error_status)
2574 block_obj->hw_ops->query_ras_error_status(adev);
2575
2576}
2577
2578static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
2579{
2580 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2581 struct ras_manager *obj;
2582
2583 if (!adev->ras_enabled || !con)
2584 return;
2585
2586 list_for_each_entry(obj, &con->head, node) {
2587 struct ras_query_if info = {
2588 .head = obj->head,
2589 };
2590
2591 amdgpu_ras_error_status_query(adev, &info);
2592 }
2593}
2594
2595static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
2596 struct ras_badpage *bps, uint32_t count, uint32_t start)
2597{
2598 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2599 struct ras_err_handler_data *data;
2600 int r = 0;
2601 uint32_t i;
2602
2603 if (!con || !con->eh_data || !bps || !count)
2604 return -EINVAL;
2605
2606 mutex_lock(&con->recovery_lock);
2607 data = con->eh_data;
2608 if (start < data->count) {
2609 for (i = start; i < data->count; i++) {
2610 if (!data->bps[i].ts)
2611 continue;
2612
2613 /* U64_MAX is used to mark the record as invalid */
2614 if (data->bps[i].retired_page == U64_MAX)
2615 continue;
2616
2617 bps[r].bp = data->bps[i].retired_page;
2618 r++;
2619 if (r >= count)
2620 break;
2621 }
2622 }
2623 mutex_unlock(&con->recovery_lock);
2624
2625 return r;
2626}
2627
2628static int amdgpu_uniras_badpages_read(struct amdgpu_device *adev,
2629 struct ras_badpage *bps, uint32_t count, uint32_t start)
2630{
2631 struct ras_cmd_bad_pages_info_req cmd_input;
2632 struct ras_cmd_bad_pages_info_rsp *output;
2633 uint32_t group, start_group, end_group;
2634 uint32_t pos, pos_in_group;
2635 int r = 0, i;
2636
2637 if (!bps || !count)
2638 return -EINVAL;
2639
2640 output = kmalloc_obj(*output);
2641 if (!output)
2642 return -ENOMEM;
2643
2644 memset(&cmd_input, 0, sizeof(cmd_input));
2645
2646 start_group = start / RAS_CMD_MAX_BAD_PAGES_PER_GROUP;
2647 end_group = (start + count + RAS_CMD_MAX_BAD_PAGES_PER_GROUP - 1) /
2648 RAS_CMD_MAX_BAD_PAGES_PER_GROUP;
2649
2650 pos = start;
2651 for (group = start_group; group < end_group; group++) {
2652 memset(output, 0, sizeof(*output));
2653 cmd_input.group_index = group;
2654 if (amdgpu_ras_mgr_handle_ras_cmd(adev, RAS_CMD__GET_BAD_PAGES,
2655 &cmd_input, sizeof(cmd_input), output, sizeof(*output)))
2656 goto out;
2657
2658 if (pos >= output->bp_total_cnt)
2659 goto out;
2660
2661 pos_in_group = pos - group * RAS_CMD_MAX_BAD_PAGES_PER_GROUP;
2662 for (i = pos_in_group; i < output->bp_in_group; i++, pos++) {
2663 if (!output->records[i].ts)
2664 continue;
2665
2666 bps[r].bp = output->records[i].retired_page;
2667 r++;
2668 if (r >= count)
2669 goto out;
2670 }
2671 }
2672
2673out:
2674 kfree(output);
2675 return r;
2676}
2677
2678static void amdgpu_ras_set_fed_all(struct amdgpu_device *adev,
2679 struct amdgpu_hive_info *hive, bool status)
2680{
2681 struct amdgpu_device *tmp_adev;
2682
2683 if (hive) {
2684 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head)
2685 amdgpu_ras_set_fed(tmp_adev, status);
2686 } else {
2687 amdgpu_ras_set_fed(adev, status);
2688 }
2689}
2690
2691bool amdgpu_ras_in_recovery(struct amdgpu_device *adev)
2692{
2693 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
2694 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
2695 int hive_ras_recovery = 0;
2696
2697 if (hive) {
2698 hive_ras_recovery = atomic_read(&hive->ras_recovery);
2699 amdgpu_put_xgmi_hive(hive);
2700 }
2701
2702 if (ras && (atomic_read(&ras->in_recovery) || hive_ras_recovery))
2703 return true;
2704
2705 return false;
2706}
2707
2708static enum ras_event_type amdgpu_ras_get_fatal_error_event(struct amdgpu_device *adev)
2709{
2710 if (amdgpu_ras_intr_triggered())
2711 return RAS_EVENT_TYPE_FATAL;
2712 else
2713 return RAS_EVENT_TYPE_POISON_CONSUMPTION;
2714}
2715
2716static void amdgpu_ras_do_recovery(struct work_struct *work)
2717{
2718 struct amdgpu_ras *ras =
2719 container_of(work, struct amdgpu_ras, recovery_work);
2720 struct amdgpu_device *remote_adev = NULL;
2721 struct amdgpu_device *adev = ras->adev;
2722 struct list_head device_list, *device_list_handle = NULL;
2723 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
2724 unsigned int error_query_mode;
2725 enum ras_event_type type;
2726
2727 if (hive) {
2728 atomic_set(&hive->ras_recovery, 1);
2729
2730 /* If any device which is part of the hive received RAS fatal
2731 * error interrupt, set fatal error status on all. This
2732 * condition will need a recovery, and flag will be cleared
2733 * as part of recovery.
2734 */
2735 list_for_each_entry(remote_adev, &hive->device_list,
2736 gmc.xgmi.head)
2737 if (amdgpu_ras_get_fed_status(remote_adev)) {
2738 amdgpu_ras_set_fed_all(adev, hive, true);
2739 break;
2740 }
2741 }
2742 if (!ras->disable_ras_err_cnt_harvest) {
2743
2744 /* Build list of devices to query RAS related errors */
2745 if (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
2746 device_list_handle = &hive->device_list;
2747 } else {
2748 INIT_LIST_HEAD(&device_list);
2749 list_add_tail(&adev->gmc.xgmi.head, &device_list);
2750 device_list_handle = &device_list;
2751 }
2752
2753 if (amdgpu_ras_get_error_query_mode(adev, &error_query_mode)) {
2754 if (error_query_mode == AMDGPU_RAS_FIRMWARE_ERROR_QUERY &&
2755 (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE1_RESET)) {
2756 /* wait 500ms to ensure pmfw polling mca bank info done */
2757 msleep(500);
2758 }
2759 }
2760
2761 type = amdgpu_ras_get_fatal_error_event(adev);
2762 list_for_each_entry(remote_adev,
2763 device_list_handle, gmc.xgmi.head) {
2764 if (amdgpu_uniras_enabled(remote_adev)) {
2765 amdgpu_ras_mgr_update_ras_ecc(remote_adev);
2766 } else {
2767 amdgpu_ras_query_err_status(remote_adev);
2768 amdgpu_ras_log_on_err_counter(remote_adev, type);
2769 }
2770 }
2771
2772 }
2773
2774 if (amdgpu_device_should_recover_gpu(ras->adev)) {
2775 struct amdgpu_reset_context reset_context;
2776 memset(&reset_context, 0, sizeof(reset_context));
2777
2778 reset_context.method = AMD_RESET_METHOD_NONE;
2779 reset_context.reset_req_dev = adev;
2780 reset_context.src = AMDGPU_RESET_SRC_RAS;
2781 set_bit(AMDGPU_SKIP_COREDUMP, &reset_context.flags);
2782
2783 /* Perform full reset in fatal error mode */
2784 if (!amdgpu_ras_is_poison_mode_supported(ras->adev))
2785 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2786 else {
2787 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2788
2789 if (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE2_RESET) {
2790 ras->gpu_reset_flags &= ~AMDGPU_RAS_GPU_RESET_MODE2_RESET;
2791 reset_context.method = AMD_RESET_METHOD_MODE2;
2792 }
2793
2794 /* Fatal error occurs in poison mode, mode1 reset is used to
2795 * recover gpu.
2796 */
2797 if (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE1_RESET) {
2798 ras->gpu_reset_flags &= ~AMDGPU_RAS_GPU_RESET_MODE1_RESET;
2799 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2800
2801 psp_fatal_error_recovery_quirk(&adev->psp);
2802 }
2803 }
2804
2805 amdgpu_device_gpu_recover(ras->adev, NULL, &reset_context);
2806 }
2807 atomic_set(&ras->in_recovery, 0);
2808 if (hive) {
2809 atomic_set(&hive->ras_recovery, 0);
2810 amdgpu_put_xgmi_hive(hive);
2811 }
2812}
2813
2814/* alloc/realloc bps array */
2815static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
2816 struct ras_err_handler_data *data, int pages)
2817{
2818 unsigned int old_space = data->count + data->space_left;
2819 unsigned int new_space = old_space + pages;
2820 unsigned int align_space = ALIGN(new_space, 512);
2821 void *bps = kmalloc_objs(*data->bps, align_space);
2822
2823 if (!bps) {
2824 return -ENOMEM;
2825 }
2826
2827 if (data->bps) {
2828 memcpy(bps, data->bps,
2829 data->count * sizeof(*data->bps));
2830 kfree(data->bps);
2831 }
2832
2833 data->bps = bps;
2834 data->space_left += align_space - old_space;
2835 return 0;
2836}
2837
2838static bool __check_record_in_range(struct amdgpu_device *adev,
2839 struct eeprom_table_record *bps, int count)
2840{
2841 int i;
2842
2843 for (i = 0; i < count; i++) {
2844 if (bps[i].retired_page >=
2845 (adev->gmc.real_vram_size >> AMDGPU_GPU_PAGE_SHIFT)) {
2846 dev_warn(adev->dev,
2847 "Recorded address out of range: 0x%llx, 0x%llx, 0x%x, 0x%x\n",
2848 bps[i].address, bps[i].retired_page,
2849 bps[i].mem_channel, bps[i].mcumc_id);
2850 return false;
2851 }
2852 }
2853
2854 return true;
2855}
2856
2857static int __amdgpu_ras_restore_bad_pages(struct amdgpu_device *adev,
2858 struct eeprom_table_record *bps, int count)
2859{
2860 int j;
2861 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2862 struct ras_err_handler_data *data = con->eh_data;
2863
2864 if (!__check_record_in_range(adev, bps, count))
2865 return 0;
2866
2867 for (j = 0; j < count; j++) {
2868 if (!data->space_left &&
2869 amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
2870 return -ENOMEM;
2871 }
2872
2873 if (amdgpu_ras_check_bad_page_unlock(con,
2874 bps[j].retired_page << AMDGPU_GPU_PAGE_SHIFT)) {
2875 /* set to U64_MAX to mark it as invalid */
2876 data->bps[data->count].retired_page = U64_MAX;
2877 data->count++;
2878 data->space_left--;
2879 continue;
2880 }
2881
2882 amdgpu_ras_reserve_page(adev, bps[j].retired_page);
2883
2884 memcpy(&data->bps[data->count], &(bps[j]),
2885 sizeof(struct eeprom_table_record));
2886 data->count++;
2887 data->space_left--;
2888 con->bad_page_num++;
2889 }
2890
2891 return 0;
2892}
2893
2894static int __amdgpu_ras_convert_rec_array_from_rom(struct amdgpu_device *adev,
2895 struct eeprom_table_record *bps, struct ras_err_data *err_data,
2896 enum amdgpu_memory_partition nps)
2897{
2898 /*old asics just have pa in eeprom*/
2899 memcpy(err_data->err_addr, bps,
2900 sizeof(struct eeprom_table_record) * adev->umc.retire_unit);
2901
2902 return __amdgpu_ras_restore_bad_pages(adev, err_data->err_addr, adev->umc.retire_unit);
2903}
2904
2905/* it deal with vram only. */
2906int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
2907 struct eeprom_table_record *bps, int pages, bool from_rom)
2908{
2909 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2910 struct ras_err_data err_data;
2911 struct amdgpu_ras_eeprom_control *control =
2912 &adev->psp.ras_context.ras->eeprom_control;
2913 enum amdgpu_memory_partition nps = AMDGPU_NPS1_PARTITION_MODE;
2914 int ret = 0;
2915 uint32_t i = 0;
2916
2917 if (!con || !con->eh_data || !bps || pages <= 0)
2918 return 0;
2919
2920 if (from_rom) {
2921 err_data.err_addr =
2922 kzalloc_objs(struct eeprom_table_record,
2923 adev->umc.retire_unit);
2924 if (!err_data.err_addr) {
2925 dev_warn(adev->dev, "Failed to alloc UMC error address record in mca2pa conversion!\n");
2926 return -ENOMEM;
2927 }
2928
2929 if (adev->gmc.gmc_funcs->query_mem_partition_mode)
2930 nps = adev->gmc.gmc_funcs->query_mem_partition_mode(adev);
2931 }
2932
2933 mutex_lock(&con->recovery_lock);
2934
2935 if (from_rom) {
2936 /* there is no pa recs in V3, so skip pa recs processing */
2937 if (control->tbl_hdr.version < RAS_TABLE_VER_V3) {
2938 for (i = 0; i < pages; i++) {
2939 if (control->ras_num_recs - i >= adev->umc.retire_unit) {
2940 if ((bps[i].address == bps[i + 1].address) &&
2941 (bps[i].mem_channel == bps[i + 1].mem_channel)) {
2942 /* deal with retire_unit records a time */
2943 ret = __amdgpu_ras_convert_rec_array_from_rom(adev,
2944 &bps[i], &err_data, nps);
2945 i += (adev->umc.retire_unit - 1);
2946 } else {
2947 break;
2948 }
2949 } else {
2950 break;
2951 }
2952 }
2953 }
2954 for (; i < pages; i++)
2955 bps[i].retired_page &= ~(UMC_NPS_MASK << UMC_NPS_SHIFT);
2956
2957 con->eh_data->count_saved = con->eh_data->count;
2958 } else {
2959 ret = __amdgpu_ras_restore_bad_pages(adev, bps, pages);
2960 }
2961
2962 if (from_rom)
2963 kfree(err_data.err_addr);
2964 mutex_unlock(&con->recovery_lock);
2965
2966 return ret;
2967}
2968
2969/*
2970 * write error record array to eeprom, the function should be
2971 * protected by recovery_lock
2972 * new_cnt: new added UE count, excluding reserved bad pages, can be NULL
2973 */
2974int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev,
2975 unsigned long *new_cnt)
2976{
2977 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2978 struct ras_err_handler_data *data;
2979 struct amdgpu_ras_eeprom_control *control;
2980 int save_count, unit_num;
2981
2982 if (!con || !con->eh_data) {
2983 if (new_cnt)
2984 *new_cnt = 0;
2985
2986 return 0;
2987 }
2988
2989 if (!con->eeprom_control.is_eeprom_valid) {
2990 dev_warn(adev->dev,
2991 "Failed to save EEPROM table data because of EEPROM data corruption!");
2992 if (new_cnt)
2993 *new_cnt = 0;
2994
2995 return 0;
2996 }
2997
2998 mutex_lock(&con->recovery_lock);
2999 control = &con->eeprom_control;
3000 data = con->eh_data;
3001 unit_num = data->count / adev->umc.retire_unit - control->ras_num_recs;
3002
3003 save_count = con->bad_page_num - control->ras_num_bad_pages;
3004 mutex_unlock(&con->recovery_lock);
3005
3006 if (new_cnt)
3007 *new_cnt = unit_num;
3008
3009 /* only new entries are saved */
3010 if (unit_num && save_count) {
3011 /*old asics only save pa to eeprom like before*/
3012 if (amdgpu_ras_eeprom_append(control,
3013 &data->bps[data->count_saved], unit_num)) {
3014 dev_err(adev->dev, "Failed to save EEPROM table data!");
3015 return -EIO;
3016 }
3017
3018 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
3019 data->count_saved = data->count;
3020 }
3021
3022 return 0;
3023}
3024
3025/*
3026 * read error record array in eeprom and reserve enough space for
3027 * storing new bad pages
3028 */
3029static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
3030{
3031 struct amdgpu_ras_eeprom_control *control =
3032 &adev->psp.ras_context.ras->eeprom_control;
3033 struct eeprom_table_record *bps;
3034 int ret;
3035
3036 /* no bad page record, skip eeprom access */
3037 if (control->ras_num_recs == 0 || amdgpu_bad_page_threshold == 0)
3038 return 0;
3039
3040 bps = kzalloc_objs(*bps, control->ras_num_recs);
3041 if (!bps)
3042 return -ENOMEM;
3043
3044 ret = amdgpu_ras_eeprom_read(control, bps, control->ras_num_recs);
3045 if (ret) {
3046 dev_err(adev->dev, "Failed to load EEPROM table records!");
3047 } else {
3048 ret = amdgpu_ras_add_bad_pages(adev, bps, control->ras_num_recs, true);
3049 if (ret)
3050 goto out;
3051
3052 ret = amdgpu_ras_eeprom_check(control);
3053 if (ret)
3054 goto out;
3055
3056 /* HW not usable */
3057 if (amdgpu_ras_is_rma(adev))
3058 ret = -EHWPOISON;
3059 }
3060
3061out:
3062 kfree(bps);
3063 return ret;
3064}
3065
3066static int amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
3067 uint64_t addr)
3068{
3069 struct ras_err_handler_data *data = con->eh_data;
3070 struct amdgpu_device *adev = con->adev;
3071 int i;
3072
3073 if ((addr >= adev->gmc.mc_vram_size &&
3074 adev->gmc.mc_vram_size) ||
3075 (addr >= RAS_UMC_INJECT_ADDR_LIMIT))
3076 return -EINVAL;
3077
3078 addr >>= AMDGPU_GPU_PAGE_SHIFT;
3079 for (i = 0; i < data->count; i++)
3080 if (addr == data->bps[i].retired_page)
3081 return 1;
3082
3083 return 0;
3084}
3085
3086/*
3087 * check if an address belongs to bad page
3088 *
3089 * Note: this check is only for umc block
3090 */
3091static int amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
3092 uint64_t addr)
3093{
3094 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3095 int ret = 0;
3096
3097 if (!con || !con->eh_data)
3098 return ret;
3099
3100 mutex_lock(&con->recovery_lock);
3101 ret = amdgpu_ras_check_bad_page_unlock(con, addr);
3102 mutex_unlock(&con->recovery_lock);
3103 return ret;
3104}
3105
3106static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev,
3107 uint32_t max_count)
3108{
3109 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3110
3111 /*
3112 * amdgpu_bad_page_threshold is used to config
3113 * the threshold for the number of bad pages.
3114 * -1: Threshold is set to default value
3115 * Driver will issue a warning message when threshold is reached
3116 * and continue runtime services.
3117 * 0: Disable bad page retirement
3118 * Driver will not retire bad pages
3119 * which is intended for debugging purpose.
3120 * -2: Threshold is determined by a formula
3121 * that assumes 1 bad page per 100M of local memory.
3122 * Driver will continue runtime services when threhold is reached.
3123 * 0 < threshold < max number of bad page records in EEPROM,
3124 * A user-defined threshold is set
3125 * Driver will halt runtime services when this custom threshold is reached.
3126 */
3127 if (amdgpu_bad_page_threshold == -2) {
3128 u64 val = adev->gmc.mc_vram_size;
3129
3130 do_div(val, RAS_BAD_PAGE_COVER);
3131 con->bad_page_cnt_threshold = min(lower_32_bits(val),
3132 max_count);
3133 } else if (amdgpu_bad_page_threshold == -1) {
3134 con->bad_page_cnt_threshold = ((con->reserved_pages_in_bytes) >> 21) << 4;
3135 } else {
3136 con->bad_page_cnt_threshold = min_t(int, max_count,
3137 amdgpu_bad_page_threshold);
3138 }
3139}
3140
3141int amdgpu_ras_init_badpage_info(struct amdgpu_device *adev)
3142{
3143 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3144 struct amdgpu_ras_eeprom_control *control;
3145 int ret;
3146
3147 if (!con || amdgpu_sriov_vf(adev))
3148 return 0;
3149
3150 /*
3151 * For the reset-on-init path (e.g. an NPS memory partition,
3152 * switch) the RAS IP block hw_init has not been enabled and
3153 * the amdgpu_uniras_enabled return false, check amdgpu ras
3154 * context uniras_enabled flag, eeprom init will be called
3155 * during RAS IP block hw_init.
3156 */
3157 if (amdgpu_uniras_enabled(adev) || con->uniras_enabled)
3158 return 0;
3159
3160 control = &con->eeprom_control;
3161
3162 ret = amdgpu_ras_eeprom_init(control);
3163 control->is_eeprom_valid = !ret;
3164
3165 if (control->ras_num_recs && control->is_eeprom_valid) {
3166 ret = amdgpu_ras_load_bad_pages(adev);
3167 if (ret) {
3168 control->is_eeprom_valid = false;
3169 return 0;
3170 }
3171
3172 amdgpu_dpm_send_hbm_bad_pages_num(
3173 adev, control->ras_num_bad_pages);
3174
3175 if (con->update_channel_flag == true) {
3176 amdgpu_dpm_send_hbm_bad_channel_flag(
3177 adev, control->bad_channel_bitmap);
3178 con->update_channel_flag = false;
3179 }
3180 }
3181
3182 return 0;
3183}
3184
3185int amdgpu_ras_recovery_init(struct amdgpu_device *adev, bool init_bp_info)
3186{
3187 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3188 struct ras_err_handler_data **data;
3189 u32 max_eeprom_records_count = 0;
3190 int ret;
3191
3192 if (!con || amdgpu_sriov_vf(adev))
3193 return 0;
3194
3195 /* Allow access to RAS EEPROM via debugfs, when the ASIC
3196 * supports RAS and debugfs is enabled, but when
3197 * adev->ras_enabled is unset, i.e. when "ras_enable"
3198 * module parameter is set to 0.
3199 */
3200 con->adev = adev;
3201
3202 if (!adev->ras_enabled)
3203 return 0;
3204
3205 data = &con->eh_data;
3206 *data = kzalloc_obj(**data);
3207 if (!*data) {
3208 ret = -ENOMEM;
3209 goto out;
3210 }
3211
3212 mutex_init(&con->recovery_lock);
3213 INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
3214 atomic_set(&con->in_recovery, 0);
3215 con->eeprom_control.bad_channel_bitmap = 0;
3216
3217 max_eeprom_records_count = amdgpu_ras_eeprom_max_record_count(&con->eeprom_control);
3218 amdgpu_ras_validate_threshold(adev, max_eeprom_records_count);
3219
3220 if (init_bp_info) {
3221 ret = amdgpu_ras_init_badpage_info(adev);
3222 if (ret)
3223 goto free;
3224 }
3225
3226 mutex_init(&con->page_rsv_lock);
3227 mutex_init(&con->page_retirement_lock);
3228
3229#ifdef CONFIG_X86_MCE_AMD
3230 if ((adev->asic_type == CHIP_ALDEBARAN) &&
3231 (adev->gmc.xgmi.connected_to_cpu))
3232 amdgpu_register_bad_pages_mca_notifier(adev);
3233#endif
3234 return 0;
3235
3236free:
3237 kfree((*data)->bps);
3238 kfree(*data);
3239 con->eh_data = NULL;
3240out:
3241 dev_warn(adev->dev, "Failed to initialize ras recovery! (%d)\n", ret);
3242
3243 /*
3244 * Except error threshold exceeding case, other failure cases in this
3245 * function would not fail amdgpu driver init.
3246 */
3247 if (!amdgpu_ras_is_rma(adev))
3248 ret = 0;
3249 else
3250 ret = -EINVAL;
3251
3252 return ret;
3253}
3254
3255static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
3256{
3257 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3258 struct ras_err_handler_data *data = con->eh_data;
3259
3260 /* recovery_init failed to init it, fini is useless */
3261 if (!data)
3262 return 0;
3263
3264 mutex_destroy(&con->page_rsv_lock);
3265
3266 cancel_work_sync(&con->recovery_work);
3267
3268 mutex_lock(&con->recovery_lock);
3269 con->eh_data = NULL;
3270 kfree(data->bps);
3271 kfree(data);
3272 mutex_unlock(&con->recovery_lock);
3273
3274 amdgpu_ras_critical_region_init(adev);
3275#ifdef CONFIG_X86_MCE_AMD
3276 amdgpu_unregister_bad_pages_mca_notifier(adev);
3277#endif
3278 return 0;
3279}
3280/* recovery end */
3281
3282static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
3283{
3284 if (amdgpu_sriov_vf(adev)) {
3285 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
3286 case IP_VERSION(13, 0, 2):
3287 case IP_VERSION(13, 0, 6):
3288 case IP_VERSION(13, 0, 12):
3289 case IP_VERSION(13, 0, 14):
3290 case IP_VERSION(13, 0, 15):
3291 return true;
3292 default:
3293 return false;
3294 }
3295 }
3296
3297 if (adev->asic_type == CHIP_IP_DISCOVERY) {
3298 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
3299 case IP_VERSION(13, 0, 0):
3300 case IP_VERSION(13, 0, 6):
3301 case IP_VERSION(13, 0, 10):
3302 case IP_VERSION(13, 0, 12):
3303 case IP_VERSION(13, 0, 14):
3304 case IP_VERSION(13, 0, 15):
3305 case IP_VERSION(14, 0, 3):
3306 return true;
3307 default:
3308 return false;
3309 }
3310 }
3311
3312 return adev->asic_type == CHIP_VEGA10 ||
3313 adev->asic_type == CHIP_VEGA20 ||
3314 adev->asic_type == CHIP_ARCTURUS ||
3315 adev->asic_type == CHIP_ALDEBARAN ||
3316 adev->asic_type == CHIP_SIENNA_CICHLID;
3317}
3318
3319/*
3320 * this is workaround for vega20 workstation sku,
3321 * force enable gfx ras, ignore vbios gfx ras flag
3322 * due to GC EDC can not write
3323 */
3324static void amdgpu_ras_get_quirks(struct amdgpu_device *adev)
3325{
3326 struct atom_context *ctx = adev->mode_info.atom_context;
3327
3328 if (!ctx)
3329 return;
3330
3331 if (strnstr(ctx->vbios_pn, "D16406",
3332 sizeof(ctx->vbios_pn)) ||
3333 strnstr(ctx->vbios_pn, "D36002",
3334 sizeof(ctx->vbios_pn)))
3335 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX);
3336}
3337
3338/* Query ras capablity via atomfirmware interface */
3339static void amdgpu_ras_query_ras_capablity_from_vbios(struct amdgpu_device *adev)
3340{
3341 /* mem_ecc cap */
3342 if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
3343 dev_info(adev->dev, "MEM ECC is active.\n");
3344 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC |
3345 1 << AMDGPU_RAS_BLOCK__DF);
3346 } else {
3347 dev_info(adev->dev, "MEM ECC is not presented.\n");
3348 }
3349
3350 /* sram_ecc cap */
3351 if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
3352 dev_info(adev->dev, "SRAM ECC is active.\n");
3353 if (!amdgpu_sriov_vf(adev))
3354 adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
3355 1 << AMDGPU_RAS_BLOCK__DF);
3356 else
3357 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__PCIE_BIF |
3358 1 << AMDGPU_RAS_BLOCK__SDMA |
3359 1 << AMDGPU_RAS_BLOCK__GFX);
3360
3361 /*
3362 * VCN/JPEG RAS can be supported on both bare metal and
3363 * SRIOV environment
3364 */
3365 if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(2, 6, 0) ||
3366 amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 0) ||
3367 amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 3) ||
3368 amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(5, 0, 1))
3369 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__VCN |
3370 1 << AMDGPU_RAS_BLOCK__JPEG);
3371 else
3372 adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__VCN |
3373 1 << AMDGPU_RAS_BLOCK__JPEG);
3374
3375 /*
3376 * XGMI RAS is not supported if xgmi num physical nodes
3377 * is zero
3378 */
3379 if (!adev->gmc.xgmi.num_physical_nodes)
3380 adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__XGMI_WAFL);
3381 } else {
3382 dev_info(adev->dev, "SRAM ECC is not presented.\n");
3383 }
3384}
3385
3386/* Query poison mode from umc/df IP callbacks */
3387static void amdgpu_ras_query_poison_mode(struct amdgpu_device *adev)
3388{
3389 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3390 bool df_poison, umc_poison;
3391
3392 /* poison setting is useless on SRIOV guest */
3393 if (amdgpu_sriov_vf(adev) || !con)
3394 return;
3395
3396 /* Init poison supported flag, the default value is false */
3397 if (adev->gmc.xgmi.connected_to_cpu ||
3398 adev->gmc.is_app_apu) {
3399 /* enabled by default when GPU is connected to CPU */
3400 con->poison_supported = true;
3401 } else if (adev->df.funcs &&
3402 adev->df.funcs->query_ras_poison_mode &&
3403 adev->umc.ras &&
3404 adev->umc.ras->query_ras_poison_mode) {
3405 df_poison =
3406 adev->df.funcs->query_ras_poison_mode(adev);
3407 umc_poison =
3408 adev->umc.ras->query_ras_poison_mode(adev);
3409
3410 /* Only poison is set in both DF and UMC, we can support it */
3411 if (df_poison && umc_poison)
3412 con->poison_supported = true;
3413 else if (df_poison != umc_poison)
3414 dev_warn(adev->dev,
3415 "Poison setting is inconsistent in DF/UMC(%d:%d)!\n",
3416 df_poison, umc_poison);
3417 }
3418}
3419
3420/*
3421 * check hardware's ras ability which will be saved in hw_supported.
3422 * if hardware does not support ras, we can skip some ras initializtion and
3423 * forbid some ras operations from IP.
3424 * if software itself, say boot parameter, limit the ras ability. We still
3425 * need allow IP do some limited operations, like disable. In such case,
3426 * we have to initialize ras as normal. but need check if operation is
3427 * allowed or not in each function.
3428 */
3429static void amdgpu_ras_check_supported(struct amdgpu_device *adev)
3430{
3431 adev->ras_hw_enabled = adev->ras_enabled = 0;
3432
3433 if (!amdgpu_ras_asic_supported(adev))
3434 return;
3435
3436 if (amdgpu_sriov_vf(adev)) {
3437 if (amdgpu_virt_get_ras_capability(adev))
3438 goto init_ras_enabled_flag;
3439 }
3440
3441 /* query ras capability from psp */
3442 if (amdgpu_psp_get_ras_capability(&adev->psp))
3443 goto init_ras_enabled_flag;
3444
3445 /* query ras capablity from bios */
3446 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) {
3447 amdgpu_ras_query_ras_capablity_from_vbios(adev);
3448 } else {
3449 /* driver only manages a few IP blocks RAS feature
3450 * when GPU is connected cpu through XGMI */
3451 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX |
3452 1 << AMDGPU_RAS_BLOCK__SDMA |
3453 1 << AMDGPU_RAS_BLOCK__MMHUB);
3454 }
3455
3456 /* apply asic specific settings (vega20 only for now) */
3457 amdgpu_ras_get_quirks(adev);
3458
3459 /* query poison mode from umc/df ip callback */
3460 amdgpu_ras_query_poison_mode(adev);
3461
3462init_ras_enabled_flag:
3463 /* hw_supported needs to be aligned with RAS block mask. */
3464 adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK;
3465
3466 adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 :
3467 adev->ras_hw_enabled & amdgpu_ras_mask;
3468
3469 /* bad page feature is not applicable to specific app platform */
3470 if (adev->gmc.is_app_apu &&
3471 amdgpu_ip_version(adev, UMC_HWIP, 0) == IP_VERSION(12, 0, 0))
3472 amdgpu_bad_page_threshold = 0;
3473}
3474
3475static void amdgpu_ras_counte_dw(struct work_struct *work)
3476{
3477 struct amdgpu_ras *con = container_of(work, struct amdgpu_ras,
3478 ras_counte_delay_work.work);
3479 struct amdgpu_device *adev = con->adev;
3480 struct drm_device *dev = adev_to_drm(adev);
3481 unsigned long ce_count, ue_count;
3482 int res;
3483
3484 res = pm_runtime_get_sync(dev->dev);
3485 if (res < 0)
3486 goto Out;
3487
3488 /* Cache new values.
3489 */
3490 if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, NULL) == 0) {
3491 atomic_set(&con->ras_ce_count, ce_count);
3492 atomic_set(&con->ras_ue_count, ue_count);
3493 }
3494
3495Out:
3496 pm_runtime_put_autosuspend(dev->dev);
3497}
3498
3499static int amdgpu_get_ras_schema(struct amdgpu_device *adev)
3500{
3501 return amdgpu_ras_is_poison_mode_supported(adev) ? AMDGPU_RAS_ERROR__POISON : 0 |
3502 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE |
3503 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE |
3504 AMDGPU_RAS_ERROR__PARITY;
3505}
3506
3507static void ras_event_mgr_init(struct ras_event_manager *mgr)
3508{
3509 struct ras_event_state *event_state;
3510 int i;
3511
3512 memset(mgr, 0, sizeof(*mgr));
3513 atomic64_set(&mgr->seqno, 0);
3514
3515 for (i = 0; i < ARRAY_SIZE(mgr->event_state); i++) {
3516 event_state = &mgr->event_state[i];
3517 event_state->last_seqno = RAS_EVENT_INVALID_ID;
3518 atomic64_set(&event_state->count, 0);
3519 }
3520}
3521
3522static void amdgpu_ras_event_mgr_init(struct amdgpu_device *adev)
3523{
3524 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3525 struct amdgpu_hive_info *hive;
3526
3527 if (!ras)
3528 return;
3529
3530 hive = amdgpu_get_xgmi_hive(adev);
3531 ras->event_mgr = hive ? &hive->event_mgr : &ras->__event_mgr;
3532
3533 /* init event manager with node 0 on xgmi system */
3534 if (!amdgpu_reset_in_recovery(adev)) {
3535 if (!hive || adev->gmc.xgmi.node_id == 0)
3536 ras_event_mgr_init(ras->event_mgr);
3537 }
3538
3539 if (hive)
3540 amdgpu_put_xgmi_hive(hive);
3541}
3542
3543static void amdgpu_ras_init_reserved_vram_size(struct amdgpu_device *adev)
3544{
3545 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3546
3547 if (!con || (adev->flags & AMD_IS_APU))
3548 return;
3549
3550 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
3551 case IP_VERSION(13, 0, 2):
3552 case IP_VERSION(13, 0, 6):
3553 case IP_VERSION(13, 0, 12):
3554 case IP_VERSION(13, 0, 15):
3555 con->reserved_pages_in_bytes = AMDGPU_RAS_RESERVED_VRAM_SIZE_DEFAULT;
3556 break;
3557 case IP_VERSION(13, 0, 14):
3558 con->reserved_pages_in_bytes = (AMDGPU_RAS_RESERVED_VRAM_SIZE_DEFAULT << 1);
3559 break;
3560 default:
3561 break;
3562 }
3563}
3564
3565int amdgpu_ras_init(struct amdgpu_device *adev)
3566{
3567 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3568 int r;
3569
3570 if (con)
3571 return 0;
3572
3573 con = kzalloc(sizeof(*con) +
3574 sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT +
3575 sizeof(struct ras_manager) * AMDGPU_RAS_MCA_BLOCK_COUNT,
3576 GFP_KERNEL);
3577 if (!con)
3578 return -ENOMEM;
3579
3580 con->adev = adev;
3581 INIT_DELAYED_WORK(&con->ras_counte_delay_work, amdgpu_ras_counte_dw);
3582 atomic_set(&con->ras_ce_count, 0);
3583 atomic_set(&con->ras_ue_count, 0);
3584
3585 con->objs = (struct ras_manager *)(con + 1);
3586
3587 amdgpu_ras_set_context(adev, con);
3588
3589 amdgpu_ras_check_supported(adev);
3590
3591 if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) {
3592 /* set gfx block ras context feature for VEGA20 Gaming
3593 * send ras disable cmd to ras ta during ras late init.
3594 */
3595 if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) {
3596 con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);
3597
3598 return 0;
3599 }
3600
3601 r = 0;
3602 goto release_con;
3603 }
3604
3605 con->update_channel_flag = false;
3606 con->features = 0;
3607 con->schema = 0;
3608 INIT_LIST_HEAD(&con->head);
3609 /* Might need get this flag from vbios. */
3610 con->flags = RAS_DEFAULT_FLAGS;
3611
3612 /* initialize nbio ras function ahead of any other
3613 * ras functions so hardware fatal error interrupt
3614 * can be enabled as early as possible */
3615 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
3616 case IP_VERSION(7, 4, 0):
3617 case IP_VERSION(7, 4, 1):
3618 case IP_VERSION(7, 4, 4):
3619 if (!adev->gmc.xgmi.connected_to_cpu)
3620 adev->nbio.ras = &nbio_v7_4_ras;
3621 break;
3622 case IP_VERSION(4, 3, 0):
3623 if (adev->ras_hw_enabled & (1 << AMDGPU_RAS_BLOCK__DF))
3624 /* unlike other generation of nbio ras,
3625 * nbio v4_3 only support fatal error interrupt
3626 * to inform software that DF is freezed due to
3627 * system fatal error event. driver should not
3628 * enable nbio ras in such case. Instead,
3629 * check DF RAS */
3630 adev->nbio.ras = &nbio_v4_3_ras;
3631 break;
3632 case IP_VERSION(6, 3, 1):
3633 if (adev->ras_hw_enabled & (1 << AMDGPU_RAS_BLOCK__DF))
3634 /* unlike other generation of nbio ras,
3635 * nbif v6_3_1 only support fatal error interrupt
3636 * to inform software that DF is freezed due to
3637 * system fatal error event. driver should not
3638 * enable nbio ras in such case. Instead,
3639 * check DF RAS
3640 */
3641 adev->nbio.ras = &nbif_v6_3_1_ras;
3642 break;
3643 case IP_VERSION(7, 9, 0):
3644 case IP_VERSION(7, 9, 1):
3645 if (!adev->gmc.is_app_apu)
3646 adev->nbio.ras = &nbio_v7_9_ras;
3647 break;
3648 default:
3649 /* nbio ras is not available */
3650 break;
3651 }
3652
3653 /* nbio ras block needs to be enabled ahead of other ras blocks
3654 * to handle fatal error */
3655 r = amdgpu_nbio_ras_sw_init(adev);
3656 if (r)
3657 goto release_con;
3658
3659 if (adev->nbio.ras &&
3660 adev->nbio.ras->init_ras_controller_interrupt) {
3661 r = adev->nbio.ras->init_ras_controller_interrupt(adev);
3662 if (r)
3663 goto release_con;
3664 }
3665
3666 if (adev->nbio.ras &&
3667 adev->nbio.ras->init_ras_err_event_athub_interrupt) {
3668 r = adev->nbio.ras->init_ras_err_event_athub_interrupt(adev);
3669 if (r)
3670 goto release_con;
3671 }
3672
3673 /* Packed socket_id to ras feature mask bits[31:29] */
3674 if (adev->smuio.funcs &&
3675 adev->smuio.funcs->get_socket_id)
3676 con->features |= ((adev->smuio.funcs->get_socket_id(adev)) <<
3677 AMDGPU_RAS_FEATURES_SOCKETID_SHIFT);
3678
3679 /* Get RAS schema for particular SOC */
3680 con->schema = amdgpu_get_ras_schema(adev);
3681
3682 amdgpu_ras_init_reserved_vram_size(adev);
3683
3684 if (amdgpu_ras_fs_init(adev)) {
3685 r = -EINVAL;
3686 goto release_con;
3687 }
3688
3689 con->init_task_pid = task_pid_nr(current);
3690 get_task_comm(con->init_task_comm, current);
3691
3692 mutex_init(&con->critical_region_lock);
3693 INIT_LIST_HEAD(&con->critical_region_head);
3694
3695 dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
3696 "hardware ability[%x] ras_mask[%x]\n",
3697 adev->ras_hw_enabled, adev->ras_enabled);
3698
3699 return 0;
3700release_con:
3701 amdgpu_ras_set_context(adev, NULL);
3702 kfree(con);
3703
3704 return r;
3705}
3706
3707int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev)
3708{
3709 if (adev->gmc.xgmi.connected_to_cpu ||
3710 adev->gmc.is_app_apu)
3711 return 1;
3712 return 0;
3713}
3714
3715static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev,
3716 struct ras_common_if *ras_block)
3717{
3718 struct ras_query_if info = {
3719 .head = *ras_block,
3720 };
3721
3722 if (!amdgpu_persistent_edc_harvesting_supported(adev))
3723 return 0;
3724
3725 if (amdgpu_ras_query_error_status(adev, &info) != 0)
3726 drm_warn(adev_to_drm(adev), "RAS init query failure");
3727
3728 if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0)
3729 drm_warn(adev_to_drm(adev), "RAS init harvest reset failure");
3730
3731 return 0;
3732}
3733
3734bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev)
3735{
3736 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3737
3738 if (!con)
3739 return false;
3740
3741 return con->poison_supported;
3742}
3743
3744/* helper function to handle common stuff in ip late init phase */
3745int amdgpu_ras_block_late_init(struct amdgpu_device *adev,
3746 struct ras_common_if *ras_block)
3747{
3748 struct amdgpu_ras_block_object *ras_obj = NULL;
3749 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3750 struct ras_query_if *query_info;
3751 unsigned long ue_count, ce_count;
3752 int r;
3753
3754 /* disable RAS feature per IP block if it is not supported */
3755 if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
3756 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
3757 return 0;
3758 }
3759
3760 r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
3761 if (r) {
3762 if (adev->in_suspend || amdgpu_reset_in_recovery(adev)) {
3763 /* in resume phase, if fail to enable ras,
3764 * clean up all ras fs nodes, and disable ras */
3765 goto cleanup;
3766 } else
3767 return r;
3768 }
3769
3770 /* check for errors on warm reset edc persisant supported ASIC */
3771 amdgpu_persistent_edc_harvesting(adev, ras_block);
3772
3773 /* in resume phase, no need to create ras fs node */
3774 if (adev->in_suspend || amdgpu_reset_in_recovery(adev))
3775 return 0;
3776
3777 ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
3778 if (ras_obj->ras_cb || (ras_obj->hw_ops &&
3779 (ras_obj->hw_ops->query_poison_status ||
3780 ras_obj->hw_ops->handle_poison_consumption))) {
3781 r = amdgpu_ras_interrupt_add_handler(adev, ras_block);
3782 if (r)
3783 goto cleanup;
3784 }
3785
3786 if (amdgpu_uniras_enabled(adev) || (ras_obj->hw_ops &&
3787 (ras_obj->hw_ops->query_ras_error_count ||
3788 ras_obj->hw_ops->query_ras_error_status)) ||
3789 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) ||
3790 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) ||
3791 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6)) {
3792 r = amdgpu_ras_sysfs_create(adev, ras_block);
3793 if (r)
3794 goto interrupt;
3795
3796 /* Those are the cached values at init.
3797 */
3798 query_info = kzalloc_obj(*query_info);
3799 if (!query_info)
3800 return -ENOMEM;
3801 memcpy(&query_info->head, ras_block, sizeof(struct ras_common_if));
3802
3803 if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, query_info) == 0) {
3804 atomic_set(&con->ras_ce_count, ce_count);
3805 atomic_set(&con->ras_ue_count, ue_count);
3806 }
3807
3808 kfree(query_info);
3809 }
3810
3811 return 0;
3812
3813interrupt:
3814 if (ras_obj->ras_cb)
3815 amdgpu_ras_interrupt_remove_handler(adev, ras_block);
3816cleanup:
3817 amdgpu_ras_feature_enable(adev, ras_block, 0);
3818 return r;
3819}
3820
3821static int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev,
3822 struct ras_common_if *ras_block)
3823{
3824 return amdgpu_ras_block_late_init(adev, ras_block);
3825}
3826
3827/* helper function to remove ras fs node and interrupt handler */
3828void amdgpu_ras_block_late_fini(struct amdgpu_device *adev,
3829 struct ras_common_if *ras_block)
3830{
3831 struct amdgpu_ras_block_object *ras_obj;
3832 if (!ras_block)
3833 return;
3834
3835 amdgpu_ras_sysfs_remove(adev, ras_block);
3836
3837 ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
3838 if (ras_obj->ras_cb)
3839 amdgpu_ras_interrupt_remove_handler(adev, ras_block);
3840}
3841
3842static void amdgpu_ras_block_late_fini_default(struct amdgpu_device *adev,
3843 struct ras_common_if *ras_block)
3844{
3845 return amdgpu_ras_block_late_fini(adev, ras_block);
3846}
3847
3848/* do some init work after IP late init as dependence.
3849 * and it runs in resume/gpu reset/booting up cases.
3850 */
3851void amdgpu_ras_resume(struct amdgpu_device *adev)
3852{
3853 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3854 struct ras_manager *obj, *tmp;
3855
3856 if (!adev->ras_enabled || !con) {
3857 /* clean ras context for VEGA20 Gaming after send ras disable cmd */
3858 amdgpu_release_ras_context(adev);
3859
3860 return;
3861 }
3862
3863 if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
3864 /* Set up all other IPs which are not implemented. There is a
3865 * tricky thing that IP's actual ras error type should be
3866 * MULTI_UNCORRECTABLE, but as driver does not handle it, so
3867 * ERROR_NONE make sense anyway.
3868 */
3869 amdgpu_ras_enable_all_features(adev, 1);
3870
3871 /* We enable ras on all hw_supported block, but as boot
3872 * parameter might disable some of them and one or more IP has
3873 * not implemented yet. So we disable them on behalf.
3874 */
3875 list_for_each_entry_safe(obj, tmp, &con->head, node) {
3876 if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
3877 amdgpu_ras_feature_enable(adev, &obj->head, 0);
3878 /* there should be no any reference. */
3879 WARN_ON(alive_obj(obj));
3880 }
3881 }
3882 }
3883}
3884
3885void amdgpu_ras_suspend(struct amdgpu_device *adev)
3886{
3887 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3888 struct amdgpu_ras_block_list *node;
3889 struct amdgpu_ras_block_object *obj;
3890
3891 if (!adev->ras_enabled || !con)
3892 return;
3893
3894 /* run per-block ras_suspend before tearing down the RAS context */
3895 list_for_each_entry(node, &adev->ras_list, node) {
3896 if (!node->active)
3897 continue;
3898
3899 obj = node->ras_obj;
3900 if (obj && obj->ras_suspend)
3901 obj->ras_suspend(adev, &obj->ras_comm);
3902 node->active = false;
3903 }
3904
3905 amdgpu_ras_disable_all_features(adev, 0);
3906 /* Make sure all ras objects are disabled. */
3907 if (AMDGPU_RAS_GET_FEATURES(con->features))
3908 amdgpu_ras_disable_all_features(adev, 1);
3909}
3910
3911int amdgpu_ras_late_init(struct amdgpu_device *adev)
3912{
3913 struct amdgpu_ras_block_list *node, *tmp;
3914 struct amdgpu_ras_block_object *obj;
3915 int r;
3916
3917 amdgpu_ras_event_mgr_init(adev);
3918
3919 /* Guest side doesn't need init ras feature */
3920 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_ras_telemetry_en(adev))
3921 return 0;
3922
3923 if (amdgpu_uniras_enabled(adev))
3924 amdgpu_ras_mgr_set_debug_mode(adev, false);
3925
3926 list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
3927 obj = node->ras_obj;
3928 if (!obj) {
3929 dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
3930 continue;
3931 }
3932
3933 if (!amdgpu_ras_is_supported(adev, obj->ras_comm.block))
3934 continue;
3935
3936 if (obj->ras_late_init) {
3937 r = obj->ras_late_init(adev, &obj->ras_comm);
3938 if (r) {
3939 dev_err(adev->dev, "%s failed to execute ras_late_init! ret:%d\n",
3940 obj->ras_comm.name, r);
3941 return r;
3942 }
3943 } else {
3944 r = amdgpu_ras_block_late_init_default(adev, &obj->ras_comm);
3945 if (r) {
3946 dev_err(adev->dev, "%s failed to execute ras_block_late_init_default! ret:%d\n",
3947 obj->ras_comm.name, r);
3948 return r;
3949 }
3950 }
3951 node->active = true;
3952 }
3953
3954 amdgpu_ras_check_bad_page_status(adev);
3955
3956 return 0;
3957}
3958
3959/* do some fini work before IP fini as dependence */
3960int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
3961{
3962 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3963
3964 if (!adev->ras_enabled || !con)
3965 return 0;
3966
3967
3968 /* Need disable ras on all IPs here before ip [hw/sw]fini */
3969 if (AMDGPU_RAS_GET_FEATURES(con->features))
3970 amdgpu_ras_disable_all_features(adev, 0);
3971 amdgpu_ras_recovery_fini(adev);
3972 return 0;
3973}
3974
3975int amdgpu_ras_fini(struct amdgpu_device *adev)
3976{
3977 struct amdgpu_ras_block_list *ras_node, *tmp;
3978 struct amdgpu_ras_block_object *obj = NULL;
3979 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3980
3981 if (!adev->ras_enabled || !con)
3982 return 0;
3983
3984 amdgpu_ras_critical_region_fini(adev);
3985 mutex_destroy(&con->critical_region_lock);
3986
3987 list_for_each_entry_safe(ras_node, tmp, &adev->ras_list, node) {
3988 if (ras_node->ras_obj) {
3989 obj = ras_node->ras_obj;
3990 /* fall back to default cleanup if ras_suspend already ran */
3991 if (ras_node->active && obj->ras_fini)
3992 obj->ras_fini(adev, &obj->ras_comm);
3993 else
3994 amdgpu_ras_block_late_fini_default(adev, &obj->ras_comm);
3995 ras_node->active = false;
3996 }
3997
3998 /* Clear ras blocks from ras_list and free ras block list node */
3999 list_del(&ras_node->node);
4000 kfree(ras_node);
4001 }
4002
4003 amdgpu_ras_fs_fini(adev);
4004 amdgpu_ras_interrupt_remove_all(adev);
4005
4006 WARN(AMDGPU_RAS_GET_FEATURES(con->features), "Feature mask is not cleared");
4007
4008 if (AMDGPU_RAS_GET_FEATURES(con->features))
4009 amdgpu_ras_disable_all_features(adev, 0);
4010
4011 cancel_delayed_work_sync(&con->ras_counte_delay_work);
4012
4013 amdgpu_ras_set_context(adev, NULL);
4014 kfree(con);
4015
4016 return 0;
4017}
4018
4019bool amdgpu_ras_get_fed_status(struct amdgpu_device *adev)
4020{
4021 struct amdgpu_ras *ras;
4022
4023 ras = amdgpu_ras_get_context(adev);
4024 if (!ras)
4025 return false;
4026
4027 return test_bit(AMDGPU_RAS_BLOCK__LAST, &ras->ras_err_state);
4028}
4029
4030void amdgpu_ras_set_fed(struct amdgpu_device *adev, bool status)
4031{
4032 struct amdgpu_ras *ras;
4033
4034 ras = amdgpu_ras_get_context(adev);
4035 if (ras) {
4036 if (status)
4037 set_bit(AMDGPU_RAS_BLOCK__LAST, &ras->ras_err_state);
4038 else
4039 clear_bit(AMDGPU_RAS_BLOCK__LAST, &ras->ras_err_state);
4040 }
4041}
4042
4043void amdgpu_ras_clear_err_state(struct amdgpu_device *adev)
4044{
4045 struct amdgpu_ras *ras;
4046
4047 ras = amdgpu_ras_get_context(adev);
4048 if (ras) {
4049 ras->ras_err_state = 0;
4050 ras->gpu_reset_flags = 0;
4051 }
4052}
4053
4054void amdgpu_ras_set_err_poison(struct amdgpu_device *adev,
4055 enum amdgpu_ras_block block)
4056{
4057 struct amdgpu_ras *ras;
4058
4059 ras = amdgpu_ras_get_context(adev);
4060 if (ras)
4061 set_bit(block, &ras->ras_err_state);
4062}
4063
4064bool amdgpu_ras_is_err_state(struct amdgpu_device *adev, int block)
4065{
4066 struct amdgpu_ras *ras;
4067
4068 ras = amdgpu_ras_get_context(adev);
4069 if (ras) {
4070 if (block == AMDGPU_RAS_BLOCK__ANY)
4071 return (ras->ras_err_state != 0);
4072 else
4073 return test_bit(block, &ras->ras_err_state) ||
4074 test_bit(AMDGPU_RAS_BLOCK__LAST,
4075 &ras->ras_err_state);
4076 }
4077
4078 return false;
4079}
4080
4081static struct ras_event_manager *__get_ras_event_mgr(struct amdgpu_device *adev)
4082{
4083 struct amdgpu_ras *ras;
4084
4085 ras = amdgpu_ras_get_context(adev);
4086 if (!ras)
4087 return NULL;
4088
4089 return ras->event_mgr;
4090}
4091
4092int amdgpu_ras_mark_ras_event_caller(struct amdgpu_device *adev, enum ras_event_type type,
4093 const void *caller)
4094{
4095 struct ras_event_manager *event_mgr;
4096 struct ras_event_state *event_state;
4097 int ret = 0;
4098
4099 if (amdgpu_uniras_enabled(adev))
4100 return 0;
4101
4102 if (type >= RAS_EVENT_TYPE_COUNT) {
4103 ret = -EINVAL;
4104 goto out;
4105 }
4106
4107 event_mgr = __get_ras_event_mgr(adev);
4108 if (!event_mgr) {
4109 ret = -EINVAL;
4110 goto out;
4111 }
4112
4113 event_state = &event_mgr->event_state[type];
4114 event_state->last_seqno = atomic64_inc_return(&event_mgr->seqno);
4115 atomic64_inc(&event_state->count);
4116
4117out:
4118 if (ret && caller)
4119 dev_warn(adev->dev, "failed mark ras event (%d) in %ps, ret:%d\n",
4120 (int)type, caller, ret);
4121
4122 return ret;
4123}
4124
4125u64 amdgpu_ras_acquire_event_id(struct amdgpu_device *adev, enum ras_event_type type)
4126{
4127 struct ras_event_manager *event_mgr;
4128 u64 id;
4129
4130 if (type >= RAS_EVENT_TYPE_COUNT)
4131 return RAS_EVENT_INVALID_ID;
4132
4133 switch (type) {
4134 case RAS_EVENT_TYPE_FATAL:
4135 case RAS_EVENT_TYPE_POISON_CREATION:
4136 case RAS_EVENT_TYPE_POISON_CONSUMPTION:
4137 event_mgr = __get_ras_event_mgr(adev);
4138 if (!event_mgr)
4139 return RAS_EVENT_INVALID_ID;
4140
4141 id = event_mgr->event_state[type].last_seqno;
4142 break;
4143 case RAS_EVENT_TYPE_INVALID:
4144 default:
4145 id = RAS_EVENT_INVALID_ID;
4146 break;
4147 }
4148
4149 return id;
4150}
4151
4152int amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
4153{
4154 if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
4155 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
4156 enum ras_event_type type = RAS_EVENT_TYPE_FATAL;
4157 u64 event_id = RAS_EVENT_INVALID_ID;
4158
4159 if (amdgpu_uniras_enabled(adev))
4160 return 0;
4161
4162 if (!amdgpu_ras_mark_ras_event(adev, type))
4163 event_id = amdgpu_ras_acquire_event_id(adev, type);
4164
4165 RAS_EVENT_LOG(adev, event_id, "uncorrectable hardware error"
4166 "(ERREVENT_ATHUB_INTERRUPT) detected!\n");
4167
4168 amdgpu_ras_set_fed(adev, true);
4169 ras->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE1_RESET;
4170 amdgpu_ras_reset_gpu(adev);
4171 }
4172
4173 return -EBUSY;
4174}
4175
4176bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
4177{
4178 if (adev->asic_type == CHIP_VEGA20 &&
4179 adev->pm.fw_version <= 0x283400) {
4180 return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) &&
4181 amdgpu_ras_intr_triggered();
4182 }
4183
4184 return false;
4185}
4186
4187void amdgpu_release_ras_context(struct amdgpu_device *adev)
4188{
4189 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
4190
4191 if (!con)
4192 return;
4193
4194 if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {
4195 con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX);
4196 amdgpu_ras_set_context(adev, NULL);
4197 kfree(con);
4198 }
4199}
4200
4201#ifdef CONFIG_X86_MCE_AMD
4202static struct amdgpu_device *find_adev(uint32_t node_id)
4203{
4204 int i;
4205 struct amdgpu_device *adev = NULL;
4206
4207 for (i = 0; i < mce_adev_list.num_gpu; i++) {
4208 adev = mce_adev_list.devs[i];
4209
4210 if (adev && adev->gmc.xgmi.connected_to_cpu &&
4211 adev->gmc.xgmi.physical_node_id == node_id)
4212 break;
4213 adev = NULL;
4214 }
4215
4216 return adev;
4217}
4218
4219#define GET_MCA_IPID_GPUID(m) (((m) >> 44) & 0xF)
4220#define GET_UMC_INST(m) (((m) >> 21) & 0x7)
4221#define GET_CHAN_INDEX(m) ((((m) >> 12) & 0x3) | (((m) >> 18) & 0x4))
4222#define GPU_ID_OFFSET 8
4223
4224static int amdgpu_bad_page_notifier(struct notifier_block *nb,
4225 unsigned long val, void *data)
4226{
4227 struct mce *m = (struct mce *)data;
4228 struct amdgpu_device *adev = NULL;
4229 uint32_t gpu_id = 0;
4230 uint32_t umc_inst = 0, ch_inst = 0;
4231
4232 /*
4233 * If the error was generated in UMC_V2, which belongs to GPU UMCs,
4234 * and error occurred in DramECC (Extended error code = 0) then only
4235 * process the error, else bail out.
4236 */
4237 if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) &&
4238 (XEC(m->status, 0x3f) == 0x0)))
4239 return NOTIFY_DONE;
4240
4241 /*
4242 * If it is correctable error, return.
4243 */
4244 if (mce_is_correctable(m))
4245 return NOTIFY_OK;
4246
4247 /*
4248 * GPU Id is offset by GPU_ID_OFFSET in MCA_IPID_UMC register.
4249 */
4250 gpu_id = GET_MCA_IPID_GPUID(m->ipid) - GPU_ID_OFFSET;
4251
4252 adev = find_adev(gpu_id);
4253 if (!adev) {
4254 DRM_WARN("%s: Unable to find adev for gpu_id: %d\n", __func__,
4255 gpu_id);
4256 return NOTIFY_DONE;
4257 }
4258
4259 /*
4260 * If it is uncorrectable error, then find out UMC instance and
4261 * channel index.
4262 */
4263 umc_inst = GET_UMC_INST(m->ipid);
4264 ch_inst = GET_CHAN_INDEX(m->ipid);
4265
4266 dev_info(adev->dev, "Uncorrectable error detected in UMC inst: %d, chan_idx: %d",
4267 umc_inst, ch_inst);
4268
4269 if (!amdgpu_umc_page_retirement_mca(adev, m->addr, ch_inst, umc_inst))
4270 return NOTIFY_OK;
4271 else
4272 return NOTIFY_DONE;
4273}
4274
4275static struct notifier_block amdgpu_bad_page_nb = {
4276 .notifier_call = amdgpu_bad_page_notifier,
4277 .priority = MCE_PRIO_UC,
4278};
4279
4280static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev)
4281{
4282 /*
4283 * Add the adev to the mce_adev_list.
4284 * During mode2 reset, amdgpu device is temporarily
4285 * removed from the mgpu_info list which can cause
4286 * page retirement to fail.
4287 * Use this list instead of mgpu_info to find the amdgpu
4288 * device on which the UMC error was reported.
4289 */
4290 if (mce_adev_list.num_gpu >= MAX_GPU_INSTANCE) {
4291 dev_warn_ratelimited(adev->dev,
4292 "mce_adev_list full, skip notifier registration (max=%d)\n",
4293 MAX_GPU_INSTANCE);
4294 return;
4295 }
4296
4297 mce_adev_list.devs[mce_adev_list.num_gpu++] = adev;
4298
4299 /*
4300 * Register the x86 notifier only once
4301 * with MCE subsystem.
4302 */
4303 if (notifier_registered == false) {
4304 mce_register_decode_chain(&amdgpu_bad_page_nb);
4305 notifier_registered = true;
4306 }
4307}
4308static void amdgpu_unregister_bad_pages_mca_notifier(struct amdgpu_device *adev)
4309{
4310 int i, j;
4311
4312 if (!notifier_registered && !mce_adev_list.num_gpu)
4313 return;
4314 for (i = 0, j = 0; i < mce_adev_list.num_gpu; i++) {
4315 if (mce_adev_list.devs[i] == adev)
4316 mce_adev_list.devs[i] = NULL;
4317 if (!mce_adev_list.devs[i])
4318 ++j;
4319 }
4320
4321 if (j == mce_adev_list.num_gpu) {
4322 mce_adev_list.num_gpu = 0;
4323 /* Unregister x86 notifier with MCE subsystem. */
4324 if (notifier_registered) {
4325 mce_unregister_decode_chain(&amdgpu_bad_page_nb);
4326 notifier_registered = false;
4327 }
4328 }
4329}
4330#endif
4331
4332struct amdgpu_ras *amdgpu_ras_get_context(struct amdgpu_device *adev)
4333{
4334 if (!adev)
4335 return NULL;
4336
4337 return adev->psp.ras_context.ras;
4338}
4339
4340int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con)
4341{
4342 if (!adev)
4343 return -EINVAL;
4344
4345 adev->psp.ras_context.ras = ras_con;
4346 return 0;
4347}
4348
4349/* check if ras is supported on block, say, sdma, gfx */
4350int amdgpu_ras_is_supported(struct amdgpu_device *adev,
4351 unsigned int block)
4352{
4353 int ret = 0;
4354 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
4355
4356 if (block >= AMDGPU_RAS_BLOCK_COUNT)
4357 return 0;
4358
4359 ret = ras && (adev->ras_enabled & (1 << block));
4360
4361 /* For the special asic with mem ecc enabled but sram ecc
4362 * not enabled, even if the ras block is not supported on
4363 * .ras_enabled, if the asic supports poison mode and the
4364 * ras block has ras configuration, it can be considered
4365 * that the ras block supports ras function.
4366 */
4367 if (!ret &&
4368 (block == AMDGPU_RAS_BLOCK__GFX ||
4369 block == AMDGPU_RAS_BLOCK__SDMA ||
4370 block == AMDGPU_RAS_BLOCK__VCN ||
4371 block == AMDGPU_RAS_BLOCK__JPEG) &&
4372 (amdgpu_ras_mask & (1 << block)) &&
4373 amdgpu_ras_is_poison_mode_supported(adev) &&
4374 amdgpu_ras_get_ras_block(adev, block, 0))
4375 ret = 1;
4376
4377 return ret;
4378}
4379
4380int amdgpu_ras_reset_gpu(struct amdgpu_device *adev)
4381{
4382 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
4383
4384 /* mode1 is the only selection for RMA status */
4385 if (amdgpu_ras_is_rma(adev)) {
4386 ras->gpu_reset_flags = 0;
4387 ras->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE1_RESET;
4388 }
4389
4390 if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0) {
4391 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
4392 int hive_ras_recovery = 0;
4393
4394 if (hive) {
4395 hive_ras_recovery = atomic_read(&hive->ras_recovery);
4396 amdgpu_put_xgmi_hive(hive);
4397 }
4398 /* In the case of multiple GPUs, after a GPU has started
4399 * resetting all GPUs on hive, other GPUs do not need to
4400 * trigger GPU reset again.
4401 */
4402 if (!hive_ras_recovery)
4403 amdgpu_reset_domain_schedule(ras->adev->reset_domain, &ras->recovery_work);
4404 else
4405 atomic_set(&ras->in_recovery, 0);
4406 } else {
4407 flush_work(&ras->recovery_work);
4408 amdgpu_reset_domain_schedule(ras->adev->reset_domain, &ras->recovery_work);
4409 }
4410
4411 return 0;
4412}
4413
4414bool amdgpu_ras_get_error_query_mode(struct amdgpu_device *adev,
4415 unsigned int *error_query_mode)
4416{
4417 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
4418
4419 if (!con) {
4420 *error_query_mode = AMDGPU_RAS_INVALID_ERROR_QUERY;
4421 return false;
4422 }
4423
4424 if (amdgpu_sriov_vf(adev)) {
4425 *error_query_mode = AMDGPU_RAS_VIRT_ERROR_COUNT_QUERY;
4426 } else if (amdgpu_uniras_enabled(adev)) {
4427 *error_query_mode = amdgpu_ras_mgr_get_debug_mode(adev) ?
4428 AMDGPU_RAS_DIRECT_ERROR_QUERY :
4429 AMDGPU_RAS_FIRMWARE_ERROR_QUERY;
4430 } else {
4431 *error_query_mode = AMDGPU_RAS_DIRECT_ERROR_QUERY;
4432 }
4433
4434 return true;
4435}
4436
4437/* Register each ip ras block into amdgpu ras */
4438int amdgpu_ras_register_ras_block(struct amdgpu_device *adev,
4439 struct amdgpu_ras_block_object *ras_block_obj)
4440{
4441 struct amdgpu_ras_block_list *ras_node;
4442 if (!adev || !ras_block_obj)
4443 return -EINVAL;
4444
4445 ras_node = kzalloc_obj(*ras_node);
4446 if (!ras_node)
4447 return -ENOMEM;
4448
4449 INIT_LIST_HEAD(&ras_node->node);
4450 ras_node->ras_obj = ras_block_obj;
4451 list_add_tail(&ras_node->node, &adev->ras_list);
4452
4453 return 0;
4454}
4455
4456void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name)
4457{
4458 if (!err_type_name)
4459 return;
4460
4461 switch (err_type) {
4462 case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE:
4463 sprintf(err_type_name, "correctable");
4464 break;
4465 case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE:
4466 sprintf(err_type_name, "uncorrectable");
4467 break;
4468 default:
4469 sprintf(err_type_name, "unknown");
4470 break;
4471 }
4472}
4473
4474bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev,
4475 const struct amdgpu_ras_err_status_reg_entry *reg_entry,
4476 uint32_t instance,
4477 uint32_t *memory_id)
4478{
4479 uint32_t err_status_lo_data, err_status_lo_offset;
4480
4481 if (!reg_entry)
4482 return false;
4483
4484 err_status_lo_offset =
4485 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance,
4486 reg_entry->seg_lo, reg_entry->reg_lo);
4487 err_status_lo_data = RREG32(err_status_lo_offset);
4488
4489 if ((reg_entry->flags & AMDGPU_RAS_ERR_STATUS_VALID) &&
4490 !REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, ERR_STATUS_VALID_FLAG))
4491 return false;
4492
4493 *memory_id = REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, MEMORY_ID);
4494
4495 return true;
4496}
4497
4498bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev,
4499 const struct amdgpu_ras_err_status_reg_entry *reg_entry,
4500 uint32_t instance,
4501 unsigned long *err_cnt)
4502{
4503 uint32_t err_status_hi_data, err_status_hi_offset;
4504
4505 if (!reg_entry)
4506 return false;
4507
4508 err_status_hi_offset =
4509 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance,
4510 reg_entry->seg_hi, reg_entry->reg_hi);
4511 err_status_hi_data = RREG32(err_status_hi_offset);
4512
4513 if ((reg_entry->flags & AMDGPU_RAS_ERR_INFO_VALID) &&
4514 !REG_GET_FIELD(err_status_hi_data, ERR_STATUS_HI, ERR_INFO_VALID_FLAG))
4515 /* keep the check here in case we need to refer to the result later */
4516 dev_dbg(adev->dev, "Invalid err_info field\n");
4517
4518 /* read err count */
4519 *err_cnt = REG_GET_FIELD(err_status_hi_data, ERR_STATUS, ERR_CNT);
4520
4521 return true;
4522}
4523
4524void amdgpu_ras_inst_query_ras_error_count(struct amdgpu_device *adev,
4525 const struct amdgpu_ras_err_status_reg_entry *reg_list,
4526 uint32_t reg_list_size,
4527 const struct amdgpu_ras_memory_id_entry *mem_list,
4528 uint32_t mem_list_size,
4529 uint32_t instance,
4530 uint32_t err_type,
4531 unsigned long *err_count)
4532{
4533 uint32_t memory_id;
4534 unsigned long err_cnt;
4535 char err_type_name[16];
4536 uint32_t i, j;
4537
4538 for (i = 0; i < reg_list_size; i++) {
4539 /* query memory_id from err_status_lo */
4540 if (!amdgpu_ras_inst_get_memory_id_field(adev, &reg_list[i],
4541 instance, &memory_id))
4542 continue;
4543
4544 /* query err_cnt from err_status_hi */
4545 if (!amdgpu_ras_inst_get_err_cnt_field(adev, &reg_list[i],
4546 instance, &err_cnt) ||
4547 !err_cnt)
4548 continue;
4549
4550 *err_count += err_cnt;
4551
4552 /* log the errors */
4553 amdgpu_ras_get_error_type_name(err_type, err_type_name);
4554 if (!mem_list) {
4555 /* memory_list is not supported */
4556 dev_info(adev->dev,
4557 "%ld %s hardware errors detected in %s, instance: %d, memory_id: %d\n",
4558 err_cnt, err_type_name,
4559 reg_list[i].block_name,
4560 instance, memory_id);
4561 } else {
4562 for (j = 0; j < mem_list_size; j++) {
4563 if (memory_id == mem_list[j].memory_id) {
4564 dev_info(adev->dev,
4565 "%ld %s hardware errors detected in %s, instance: %d, memory block: %s\n",
4566 err_cnt, err_type_name,
4567 reg_list[i].block_name,
4568 instance, mem_list[j].name);
4569 break;
4570 }
4571 }
4572 }
4573 }
4574}
4575
4576void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev,
4577 const struct amdgpu_ras_err_status_reg_entry *reg_list,
4578 uint32_t reg_list_size,
4579 uint32_t instance)
4580{
4581 uint32_t err_status_lo_offset, err_status_hi_offset;
4582 uint32_t i;
4583
4584 for (i = 0; i < reg_list_size; i++) {
4585 err_status_lo_offset =
4586 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance,
4587 reg_list[i].seg_lo, reg_list[i].reg_lo);
4588 err_status_hi_offset =
4589 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance,
4590 reg_list[i].seg_hi, reg_list[i].reg_hi);
4591 WREG32(err_status_lo_offset, 0);
4592 WREG32(err_status_hi_offset, 0);
4593 }
4594}
4595
4596int amdgpu_ras_error_data_init(struct ras_err_data *err_data)
4597{
4598 memset(err_data, 0, sizeof(*err_data));
4599
4600 INIT_LIST_HEAD(&err_data->err_node_list);
4601
4602 return 0;
4603}
4604
4605static void amdgpu_ras_error_node_release(struct ras_err_node *err_node)
4606{
4607 if (!err_node)
4608 return;
4609
4610 list_del(&err_node->node);
4611 kvfree(err_node);
4612}
4613
4614void amdgpu_ras_error_data_fini(struct ras_err_data *err_data)
4615{
4616 struct ras_err_node *err_node, *tmp;
4617
4618 list_for_each_entry_safe(err_node, tmp, &err_data->err_node_list, node)
4619 amdgpu_ras_error_node_release(err_node);
4620}
4621
4622static struct ras_err_node *amdgpu_ras_error_find_node_by_id(struct ras_err_data *err_data,
4623 struct amdgpu_smuio_mcm_config_info *mcm_info)
4624{
4625 struct ras_err_node *err_node;
4626 struct amdgpu_smuio_mcm_config_info *ref_id;
4627
4628 if (!err_data || !mcm_info)
4629 return NULL;
4630
4631 for_each_ras_error(err_node, err_data) {
4632 ref_id = &err_node->err_info.mcm_info;
4633
4634 if (mcm_info->socket_id == ref_id->socket_id &&
4635 mcm_info->die_id == ref_id->die_id)
4636 return err_node;
4637 }
4638
4639 return NULL;
4640}
4641
4642static struct ras_err_node *amdgpu_ras_error_node_new(void)
4643{
4644 struct ras_err_node *err_node;
4645
4646 err_node = kvzalloc_obj(*err_node);
4647 if (!err_node)
4648 return NULL;
4649
4650 INIT_LIST_HEAD(&err_node->node);
4651
4652 return err_node;
4653}
4654
4655static int ras_err_info_cmp(void *priv, const struct list_head *a, const struct list_head *b)
4656{
4657 struct ras_err_node *nodea = container_of(a, struct ras_err_node, node);
4658 struct ras_err_node *nodeb = container_of(b, struct ras_err_node, node);
4659 struct amdgpu_smuio_mcm_config_info *infoa = &nodea->err_info.mcm_info;
4660 struct amdgpu_smuio_mcm_config_info *infob = &nodeb->err_info.mcm_info;
4661
4662 if (unlikely(infoa->socket_id != infob->socket_id))
4663 return infoa->socket_id - infob->socket_id;
4664 else
4665 return infoa->die_id - infob->die_id;
4666
4667 return 0;
4668}
4669
4670static struct ras_err_info *amdgpu_ras_error_get_info(struct ras_err_data *err_data,
4671 struct amdgpu_smuio_mcm_config_info *mcm_info)
4672{
4673 struct ras_err_node *err_node;
4674
4675 err_node = amdgpu_ras_error_find_node_by_id(err_data, mcm_info);
4676 if (err_node)
4677 return &err_node->err_info;
4678
4679 err_node = amdgpu_ras_error_node_new();
4680 if (!err_node)
4681 return NULL;
4682
4683 memcpy(&err_node->err_info.mcm_info, mcm_info, sizeof(*mcm_info));
4684
4685 err_data->err_list_count++;
4686 list_add_tail(&err_node->node, &err_data->err_node_list);
4687 list_sort(NULL, &err_data->err_node_list, ras_err_info_cmp);
4688
4689 return &err_node->err_info;
4690}
4691
4692int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data,
4693 struct amdgpu_smuio_mcm_config_info *mcm_info,
4694 u64 count)
4695{
4696 struct ras_err_info *err_info;
4697
4698 if (!err_data || !mcm_info)
4699 return -EINVAL;
4700
4701 if (!count)
4702 return 0;
4703
4704 err_info = amdgpu_ras_error_get_info(err_data, mcm_info);
4705 if (!err_info)
4706 return -EINVAL;
4707
4708 err_info->ue_count += count;
4709 err_data->ue_count += count;
4710
4711 return 0;
4712}
4713
4714int amdgpu_ras_error_statistic_ce_count(struct ras_err_data *err_data,
4715 struct amdgpu_smuio_mcm_config_info *mcm_info,
4716 u64 count)
4717{
4718 struct ras_err_info *err_info;
4719
4720 if (!err_data || !mcm_info)
4721 return -EINVAL;
4722
4723 if (!count)
4724 return 0;
4725
4726 err_info = amdgpu_ras_error_get_info(err_data, mcm_info);
4727 if (!err_info)
4728 return -EINVAL;
4729
4730 err_info->ce_count += count;
4731 err_data->ce_count += count;
4732
4733 return 0;
4734}
4735
4736#define mmMP0_SMN_C2PMSG_92 0x1609C
4737#define mmMP0_SMN_C2PMSG_126 0x160BE
4738static void amdgpu_ras_boot_time_error_reporting(struct amdgpu_device *adev,
4739 u32 instance)
4740{
4741 u32 socket_id, aid_id, hbm_id;
4742 u32 fw_status;
4743 u32 boot_error;
4744 u64 reg_addr;
4745
4746 /* The pattern for smn addressing in other SOC could be different from
4747 * the one for aqua_vanjaram. We should revisit the code if the pattern
4748 * is changed. In such case, replace the aqua_vanjaram implementation
4749 * with more common helper */
4750 reg_addr = (mmMP0_SMN_C2PMSG_92 << 2) +
4751 amdgpu_reg_get_smn_base64(adev, MP0_HWIP, instance);
4752 fw_status = amdgpu_device_indirect_rreg_ext(adev, reg_addr);
4753
4754 reg_addr = (mmMP0_SMN_C2PMSG_126 << 2) +
4755 amdgpu_reg_get_smn_base64(adev, MP0_HWIP, instance);
4756 boot_error = amdgpu_device_indirect_rreg_ext(adev, reg_addr);
4757
4758 socket_id = AMDGPU_RAS_GPU_ERR_SOCKET_ID(boot_error);
4759 aid_id = AMDGPU_RAS_GPU_ERR_AID_ID(boot_error);
4760 hbm_id = ((1 == AMDGPU_RAS_GPU_ERR_HBM_ID(boot_error)) ? 0 : 1);
4761
4762 if (AMDGPU_RAS_GPU_ERR_MEM_TRAINING(boot_error))
4763 dev_info(adev->dev,
4764 "socket: %d, aid: %d, hbm: %d, fw_status: 0x%x, memory training failed\n",
4765 socket_id, aid_id, hbm_id, fw_status);
4766
4767 if (AMDGPU_RAS_GPU_ERR_FW_LOAD(boot_error))
4768 dev_info(adev->dev,
4769 "socket: %d, aid: %d, fw_status: 0x%x, firmware load failed at boot time\n",
4770 socket_id, aid_id, fw_status);
4771
4772 if (AMDGPU_RAS_GPU_ERR_WAFL_LINK_TRAINING(boot_error))
4773 dev_info(adev->dev,
4774 "socket: %d, aid: %d, fw_status: 0x%x, wafl link training failed\n",
4775 socket_id, aid_id, fw_status);
4776
4777 if (AMDGPU_RAS_GPU_ERR_XGMI_LINK_TRAINING(boot_error))
4778 dev_info(adev->dev,
4779 "socket: %d, aid: %d, fw_status: 0x%x, xgmi link training failed\n",
4780 socket_id, aid_id, fw_status);
4781
4782 if (AMDGPU_RAS_GPU_ERR_USR_CP_LINK_TRAINING(boot_error))
4783 dev_info(adev->dev,
4784 "socket: %d, aid: %d, fw_status: 0x%x, usr cp link training failed\n",
4785 socket_id, aid_id, fw_status);
4786
4787 if (AMDGPU_RAS_GPU_ERR_USR_DP_LINK_TRAINING(boot_error))
4788 dev_info(adev->dev,
4789 "socket: %d, aid: %d, fw_status: 0x%x, usr dp link training failed\n",
4790 socket_id, aid_id, fw_status);
4791
4792 if (AMDGPU_RAS_GPU_ERR_HBM_MEM_TEST(boot_error))
4793 dev_info(adev->dev,
4794 "socket: %d, aid: %d, hbm: %d, fw_status: 0x%x, hbm memory test failed\n",
4795 socket_id, aid_id, hbm_id, fw_status);
4796
4797 if (AMDGPU_RAS_GPU_ERR_HBM_BIST_TEST(boot_error))
4798 dev_info(adev->dev,
4799 "socket: %d, aid: %d, hbm: %d, fw_status: 0x%x, hbm bist test failed\n",
4800 socket_id, aid_id, hbm_id, fw_status);
4801
4802 if (AMDGPU_RAS_GPU_ERR_DATA_ABORT(boot_error))
4803 dev_info(adev->dev,
4804 "socket: %d, aid: %d, fw_status: 0x%x, data abort exception\n",
4805 socket_id, aid_id, fw_status);
4806
4807 if (AMDGPU_RAS_GPU_ERR_GENERIC(boot_error))
4808 dev_info(adev->dev,
4809 "socket: %d, aid: %d, fw_status: 0x%x, Boot Controller Generic Error\n",
4810 socket_id, aid_id, fw_status);
4811}
4812
4813static bool amdgpu_ras_boot_error_detected(struct amdgpu_device *adev,
4814 u32 instance)
4815{
4816 u64 reg_addr;
4817 u32 reg_data;
4818 int retry_loop;
4819
4820 reg_addr = (mmMP0_SMN_C2PMSG_92 << 2) +
4821 amdgpu_reg_get_smn_base64(adev, MP0_HWIP, instance);
4822
4823 for (retry_loop = 0; retry_loop < AMDGPU_RAS_BOOT_STATUS_POLLING_LIMIT; retry_loop++) {
4824 reg_data = amdgpu_device_indirect_rreg_ext(adev, reg_addr);
4825 if ((reg_data & AMDGPU_RAS_BOOT_STATUS_MASK) == AMDGPU_RAS_BOOT_STEADY_STATUS)
4826 return false;
4827 else
4828 msleep(1);
4829 }
4830
4831 return true;
4832}
4833
4834void amdgpu_ras_query_boot_status(struct amdgpu_device *adev, u32 num_instances)
4835{
4836 u32 i;
4837
4838 for (i = 0; i < num_instances; i++) {
4839 if (amdgpu_ras_boot_error_detected(adev, i))
4840 amdgpu_ras_boot_time_error_reporting(adev, i);
4841 }
4842}
4843
4844int amdgpu_ras_reserve_page(struct amdgpu_device *adev, uint64_t pfn)
4845{
4846 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
4847 struct amdgpu_vram_mgr *mgr = &adev->mman.vram_mgr;
4848 uint64_t start = pfn << AMDGPU_GPU_PAGE_SHIFT;
4849 int ret = 0;
4850
4851 if (pfn >= (adev->gmc.real_vram_size >> AMDGPU_GPU_PAGE_SHIFT)) {
4852 dev_warn(adev->dev, "Ignoring out-of-range bad page 0x%llx", start);
4853 return 0;
4854 }
4855
4856 if (amdgpu_ras_check_critical_address(adev, start))
4857 return 0;
4858
4859 mutex_lock(&con->page_rsv_lock);
4860 ret = amdgpu_vram_mgr_query_page_status(mgr, start);
4861 if (ret == -ENOENT)
4862 ret = amdgpu_vram_mgr_reserve_range(mgr, start, AMDGPU_GPU_PAGE_SIZE);
4863 mutex_unlock(&con->page_rsv_lock);
4864
4865 return ret;
4866}
4867
4868void amdgpu_ras_event_log_print(struct amdgpu_device *adev, u64 event_id,
4869 const char *fmt, ...)
4870{
4871 struct va_format vaf;
4872 va_list args;
4873
4874 va_start(args, fmt);
4875 vaf.fmt = fmt;
4876 vaf.va = &args;
4877
4878 if (RAS_EVENT_ID_IS_VALID(event_id))
4879 dev_printk(KERN_INFO, adev->dev, "{%llu}%pV", event_id, &vaf);
4880 else
4881 dev_printk(KERN_INFO, adev->dev, "%pV", &vaf);
4882
4883 va_end(args);
4884}
4885
4886bool amdgpu_ras_is_rma(struct amdgpu_device *adev)
4887{
4888 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
4889
4890 if (amdgpu_uniras_enabled(adev))
4891 return amdgpu_ras_mgr_is_rma(adev);
4892
4893 if (!con)
4894 return false;
4895
4896 return con->is_rma;
4897}
4898
4899int amdgpu_ras_add_critical_region(struct amdgpu_device *adev,
4900 struct amdgpu_bo *bo)
4901{
4902 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
4903 struct amdgpu_vram_mgr_resource *vres;
4904 struct ras_critical_region *region;
4905 struct gpu_buddy_block *block;
4906 int ret = 0;
4907
4908 if (!bo || !bo->tbo.resource)
4909 return -EINVAL;
4910
4911 vres = to_amdgpu_vram_mgr_resource(bo->tbo.resource);
4912
4913 mutex_lock(&con->critical_region_lock);
4914
4915 /* Check if the bo had been recorded */
4916 list_for_each_entry(region, &con->critical_region_head, node)
4917 if (region->bo == bo)
4918 goto out;
4919
4920 /* Record new critical amdgpu bo */
4921 list_for_each_entry(block, &vres->blocks, link) {
4922 region = kzalloc_obj(*region);
4923 if (!region) {
4924 ret = -ENOMEM;
4925 goto out;
4926 }
4927 region->bo = bo;
4928 region->start = amdgpu_vram_mgr_block_start(block);
4929 region->size = amdgpu_vram_mgr_block_size(block);
4930 list_add_tail(&region->node, &con->critical_region_head);
4931 }
4932
4933out:
4934 mutex_unlock(&con->critical_region_lock);
4935
4936 return ret;
4937}
4938
4939static void amdgpu_ras_critical_region_init(struct amdgpu_device *adev)
4940{
4941 amdgpu_ras_add_critical_region(adev, adev->mman.resv_region[AMDGPU_RESV_FW].bo);
4942}
4943
4944static void amdgpu_ras_critical_region_fini(struct amdgpu_device *adev)
4945{
4946 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
4947 struct ras_critical_region *region, *tmp;
4948
4949 mutex_lock(&con->critical_region_lock);
4950 list_for_each_entry_safe(region, tmp, &con->critical_region_head, node) {
4951 list_del(&region->node);
4952 kfree(region);
4953 }
4954 mutex_unlock(&con->critical_region_lock);
4955}
4956
4957bool amdgpu_ras_check_critical_address(struct amdgpu_device *adev, uint64_t addr)
4958{
4959 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
4960 struct ras_critical_region *region;
4961 bool ret = false;
4962
4963 mutex_lock(&con->critical_region_lock);
4964 list_for_each_entry(region, &con->critical_region_head, node) {
4965 if ((region->start <= addr) &&
4966 (addr < (region->start + region->size))) {
4967 ret = true;
4968 break;
4969 }
4970 }
4971 mutex_unlock(&con->critical_region_lock);
4972
4973 return ret;
4974}
4975
4976void amdgpu_ras_pre_reset(struct amdgpu_device *adev,
4977 struct list_head *device_list)
4978{
4979 struct amdgpu_device *tmp_adev = NULL;
4980
4981 list_for_each_entry(tmp_adev, device_list, reset_list) {
4982 if (amdgpu_uniras_enabled(tmp_adev))
4983 amdgpu_ras_mgr_pre_reset(tmp_adev);
4984 }
4985}
4986
4987void amdgpu_ras_post_reset(struct amdgpu_device *adev,
4988 struct list_head *device_list)
4989{
4990 struct amdgpu_device *tmp_adev = NULL;
4991
4992 list_for_each_entry(tmp_adev, device_list, reset_list) {
4993 if (amdgpu_uniras_enabled(tmp_adev))
4994 amdgpu_ras_mgr_post_reset(tmp_adev);
4995 }
4996}
4997
4998int amdgpu_ras_resume_after_reset(struct amdgpu_device *adev)
4999{
5000 int r;
5001
5002 r = amdgpu_ras_mgr_resume_after_reset(adev);
5003 if (r)
5004 return r;
5005
5006 return amdgpu_cper_deferred_init(adev);
5007}