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1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __AMDGPU_SDMA_H__
25#define __AMDGPU_SDMA_H__
26#include "amdgpu_ras.h"
27
28/* max number of IP instances */
29#define AMDGPU_MAX_SDMA_INSTANCES 16
30
31enum amdgpu_sdma_irq {
32 AMDGPU_SDMA_IRQ_INSTANCE0 = 0,
33 AMDGPU_SDMA_IRQ_INSTANCE1,
34 AMDGPU_SDMA_IRQ_INSTANCE2,
35 AMDGPU_SDMA_IRQ_INSTANCE3,
36 AMDGPU_SDMA_IRQ_INSTANCE4,
37 AMDGPU_SDMA_IRQ_INSTANCE5,
38 AMDGPU_SDMA_IRQ_INSTANCE6,
39 AMDGPU_SDMA_IRQ_INSTANCE7,
40 AMDGPU_SDMA_IRQ_INSTANCE8,
41 AMDGPU_SDMA_IRQ_INSTANCE9,
42 AMDGPU_SDMA_IRQ_INSTANCE10,
43 AMDGPU_SDMA_IRQ_INSTANCE11,
44 AMDGPU_SDMA_IRQ_INSTANCE12,
45 AMDGPU_SDMA_IRQ_INSTANCE13,
46 AMDGPU_SDMA_IRQ_INSTANCE14,
47 AMDGPU_SDMA_IRQ_INSTANCE15,
48 AMDGPU_SDMA_IRQ_LAST
49};
50
51#define NUM_SDMA(x) hweight32(x)
52
53struct amdgpu_sdma_csa_info {
54 u32 size;
55 u32 alignment;
56};
57
58struct amdgpu_sdma_funcs {
59 int (*stop_kernel_queue)(struct amdgpu_ring *ring);
60 int (*start_kernel_queue)(struct amdgpu_ring *ring);
61 int (*soft_reset_kernel_queue)(struct amdgpu_device *adev, u32 instance_id);
62};
63
64struct amdgpu_sdma_instance {
65 /* SDMA firmware */
66 const struct firmware *fw;
67 uint32_t fw_version;
68 uint32_t feature_version;
69
70 struct amdgpu_ring ring;
71 struct amdgpu_ring page;
72 bool burst_nop;
73 union {
74 uint32_t aid_id;
75 uint32_t xcc_id;
76 };
77
78 struct amdgpu_bo *sdma_fw_obj;
79 uint64_t sdma_fw_gpu_addr;
80 uint32_t *sdma_fw_ptr;
81 struct mutex engine_reset_mutex;
82 /* track guilty state of GFX and PAGE queues */
83 bool gfx_guilty;
84 bool page_guilty;
85 const struct amdgpu_sdma_funcs *funcs;
86};
87
88struct amdgpu_sdma_ras {
89 struct amdgpu_ras_block_object ras_block;
90};
91
92struct amdgpu_sdma {
93 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
94 struct amdgpu_irq_src trap_irq;
95 struct amdgpu_irq_src illegal_inst_irq;
96 struct amdgpu_irq_src fence_irq;
97 struct amdgpu_irq_src ecc_irq;
98 struct amdgpu_irq_src vm_hole_irq;
99 struct amdgpu_irq_src doorbell_invalid_irq;
100 struct amdgpu_irq_src pool_timeout_irq;
101 struct amdgpu_irq_src srbm_write_irq;
102 struct amdgpu_irq_src ctxt_empty_irq;
103
104 int num_instances;
105 uint32_t sdma_mask;
106 union {
107 int num_inst_per_aid;
108 int num_inst_per_xcc;
109 };
110 uint32_t srbm_soft_reset;
111 bool has_page_queue;
112 struct ras_common_if *ras_if;
113 struct amdgpu_sdma_ras *ras;
114 uint32_t *ip_dump;
115 uint32_t supported_reset;
116 struct list_head reset_callback_list;
117 bool no_user_submission;
118 bool disable_uq;
119 void (*get_csa_info)(struct amdgpu_device *adev,
120 struct amdgpu_sdma_csa_info *csa_info);
121};
122
123/*
124 * Provided by hw blocks that can move/clear data. e.g., gfx or sdma
125 * But currently, we use sdma to move data.
126 */
127struct amdgpu_buffer_funcs {
128 /* maximum bytes in a single operation */
129 uint32_t copy_max_bytes;
130
131 /* number of dw to reserve per operation */
132 unsigned copy_num_dw;
133
134 /* used for buffer migration */
135 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
136 /* src addr in bytes */
137 uint64_t src_offset,
138 /* dst addr in bytes */
139 uint64_t dst_offset,
140 /* number of byte to transfer */
141 uint32_t byte_count,
142 uint32_t copy_flags);
143
144 /* maximum bytes in a single operation */
145 uint32_t fill_max_bytes;
146
147 /* number of dw to reserve per operation */
148 unsigned fill_num_dw;
149
150 /* used for buffer clearing */
151 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
152 /* value to write to memory */
153 uint32_t src_data,
154 /* dst addr in bytes */
155 uint64_t dst_offset,
156 /* number of byte to fill */
157 uint32_t byte_count);
158};
159
160int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id,
161 bool caller_handles_kernel_queues);
162
163#define amdgpu_emit_copy_buffer(adev, ib, s, d, b, t) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b), (t))
164#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
165
166struct amdgpu_sdma_instance *
167amdgpu_sdma_get_instance_from_ring(struct amdgpu_ring *ring);
168int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index);
169uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring, unsigned vmid);
170int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev,
171 struct ras_common_if *ras_block);
172int amdgpu_sdma_process_ras_data_cb(struct amdgpu_device *adev,
173 void *err_data,
174 struct amdgpu_iv_entry *entry);
175int amdgpu_sdma_process_ecc_irq(struct amdgpu_device *adev,
176 struct amdgpu_irq_src *source,
177 struct amdgpu_iv_entry *entry);
178int amdgpu_sdma_init_microcode(struct amdgpu_device *adev, u32 instance,
179 bool duplicate);
180void amdgpu_sdma_destroy_inst_ctx(struct amdgpu_device *adev,
181 bool duplicate);
182int amdgpu_sdma_ras_sw_init(struct amdgpu_device *adev);
183void amdgpu_debugfs_sdma_sched_mask_init(struct amdgpu_device *adev);
184int amdgpu_sdma_sysfs_reset_mask_init(struct amdgpu_device *adev);
185void amdgpu_sdma_sysfs_reset_mask_fini(struct amdgpu_device *adev);
186bool amdgpu_sdma_is_shared_inv_eng(struct amdgpu_device *adev, struct amdgpu_ring *ring);
187struct amdgpu_ring *amdgpu_sdma_get_shared_ring(struct amdgpu_device *adev,
188 struct amdgpu_ring *ring);
189#endif