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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
25#include <linux/slab.h>
26#include <linux/module.h>
27
28#include "amdgpu.h"
29#include "amdgpu_ucode.h"
30
31#define AMDGPU_UCODE_NAME_MAX (128)
32
33static const struct kicker_device kicker_device_list[] = {
34 {0x744B, 0x00},
35 {0x7551, 0xC8}
36};
37
38static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr)
39{
40 DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes));
41 DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes));
42 DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major));
43 DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor));
44 DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major));
45 DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor));
46 DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version));
47 DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes));
48 DRM_DEBUG("ucode_array_offset_bytes: %u\n",
49 le32_to_cpu(hdr->ucode_array_offset_bytes));
50 DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32));
51}
52
53void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr)
54{
55 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
56 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
57
58 DRM_DEBUG("MC\n");
59 amdgpu_ucode_print_common_hdr(hdr);
60
61 if (version_major == 1) {
62 const struct mc_firmware_header_v1_0 *mc_hdr =
63 container_of(hdr, struct mc_firmware_header_v1_0, header);
64
65 DRM_DEBUG("io_debug_size_bytes: %u\n",
66 le32_to_cpu(mc_hdr->io_debug_size_bytes));
67 DRM_DEBUG("io_debug_array_offset_bytes: %u\n",
68 le32_to_cpu(mc_hdr->io_debug_array_offset_bytes));
69 } else {
70 DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor);
71 }
72}
73
74void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr)
75{
76 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
77 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
78 const struct smc_firmware_header_v1_0 *v1_0_hdr;
79 const struct smc_firmware_header_v2_0 *v2_0_hdr;
80 const struct smc_firmware_header_v2_1 *v2_1_hdr;
81
82 DRM_DEBUG("SMC\n");
83 amdgpu_ucode_print_common_hdr(hdr);
84
85 if (version_major == 1) {
86 v1_0_hdr = container_of(hdr, struct smc_firmware_header_v1_0, header);
87 DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(v1_0_hdr->ucode_start_addr));
88 } else if (version_major == 2) {
89 switch (version_minor) {
90 case 0:
91 v2_0_hdr = container_of(hdr, struct smc_firmware_header_v2_0, v1_0.header);
92 DRM_DEBUG("ppt_offset_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_offset_bytes));
93 DRM_DEBUG("ppt_size_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_size_bytes));
94 break;
95 case 1:
96 v2_1_hdr = container_of(hdr, struct smc_firmware_header_v2_1, v1_0.header);
97 DRM_DEBUG("pptable_count: %u\n", le32_to_cpu(v2_1_hdr->pptable_count));
98 DRM_DEBUG("pptable_entry_offset: %u\n", le32_to_cpu(v2_1_hdr->pptable_entry_offset));
99 break;
100 default:
101 break;
102 }
103
104 } else {
105 DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor);
106 }
107}
108
109void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr)
110{
111 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
112 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
113
114 DRM_DEBUG("GFX\n");
115 amdgpu_ucode_print_common_hdr(hdr);
116
117 if (version_major == 1) {
118 const struct gfx_firmware_header_v1_0 *gfx_hdr =
119 container_of(hdr, struct gfx_firmware_header_v1_0, header);
120
121 DRM_DEBUG("ucode_feature_version: %u\n",
122 le32_to_cpu(gfx_hdr->ucode_feature_version));
123 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset));
124 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size));
125 } else if (version_major == 2) {
126 const struct gfx_firmware_header_v2_0 *gfx_hdr =
127 container_of(hdr, struct gfx_firmware_header_v2_0, header);
128
129 DRM_DEBUG("ucode_feature_version: %u\n",
130 le32_to_cpu(gfx_hdr->ucode_feature_version));
131 } else {
132 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor);
133 }
134}
135
136void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr)
137{
138 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
139 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
140
141 DRM_DEBUG("RLC\n");
142 amdgpu_ucode_print_common_hdr(hdr);
143
144 if (version_major == 1) {
145 const struct rlc_firmware_header_v1_0 *rlc_hdr =
146 container_of(hdr, struct rlc_firmware_header_v1_0, header);
147
148 DRM_DEBUG("ucode_feature_version: %u\n",
149 le32_to_cpu(rlc_hdr->ucode_feature_version));
150 DRM_DEBUG("save_and_restore_offset: %u\n",
151 le32_to_cpu(rlc_hdr->save_and_restore_offset));
152 DRM_DEBUG("clear_state_descriptor_offset: %u\n",
153 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
154 DRM_DEBUG("avail_scratch_ram_locations: %u\n",
155 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
156 DRM_DEBUG("master_pkt_description_offset: %u\n",
157 le32_to_cpu(rlc_hdr->master_pkt_description_offset));
158 } else if (version_major == 2) {
159 const struct rlc_firmware_header_v2_0 *rlc_hdr =
160 container_of(hdr, struct rlc_firmware_header_v2_0, header);
161 const struct rlc_firmware_header_v2_1 *rlc_hdr_v2_1 =
162 container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0);
163 const struct rlc_firmware_header_v2_2 *rlc_hdr_v2_2 =
164 container_of(rlc_hdr_v2_1, struct rlc_firmware_header_v2_2, v2_1);
165 const struct rlc_firmware_header_v2_3 *rlc_hdr_v2_3 =
166 container_of(rlc_hdr_v2_2, struct rlc_firmware_header_v2_3, v2_2);
167 const struct rlc_firmware_header_v2_4 *rlc_hdr_v2_4 =
168 container_of(rlc_hdr_v2_3, struct rlc_firmware_header_v2_4, v2_3);
169 const struct rlc_firmware_header_v2_5 *rlc_hdr_v2_5 =
170 container_of(rlc_hdr_v2_2, struct rlc_firmware_header_v2_5, v2_2);
171
172 switch (version_minor) {
173 case 0:
174 /* rlc_hdr v2_0 */
175 DRM_DEBUG("ucode_feature_version: %u\n",
176 le32_to_cpu(rlc_hdr->ucode_feature_version));
177 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset));
178 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size));
179 DRM_DEBUG("save_and_restore_offset: %u\n",
180 le32_to_cpu(rlc_hdr->save_and_restore_offset));
181 DRM_DEBUG("clear_state_descriptor_offset: %u\n",
182 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
183 DRM_DEBUG("avail_scratch_ram_locations: %u\n",
184 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
185 DRM_DEBUG("reg_restore_list_size: %u\n",
186 le32_to_cpu(rlc_hdr->reg_restore_list_size));
187 DRM_DEBUG("reg_list_format_start: %u\n",
188 le32_to_cpu(rlc_hdr->reg_list_format_start));
189 DRM_DEBUG("reg_list_format_separate_start: %u\n",
190 le32_to_cpu(rlc_hdr->reg_list_format_separate_start));
191 DRM_DEBUG("starting_offsets_start: %u\n",
192 le32_to_cpu(rlc_hdr->starting_offsets_start));
193 DRM_DEBUG("reg_list_format_size_bytes: %u\n",
194 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes));
195 DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n",
196 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
197 DRM_DEBUG("reg_list_size_bytes: %u\n",
198 le32_to_cpu(rlc_hdr->reg_list_size_bytes));
199 DRM_DEBUG("reg_list_array_offset_bytes: %u\n",
200 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
201 DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n",
202 le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes));
203 DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n",
204 le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes));
205 DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
206 le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
207 DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n",
208 le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes));
209 break;
210 case 1:
211 /* rlc_hdr v2_1 */
212 DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n",
213 le32_to_cpu(rlc_hdr_v2_1->reg_list_format_direct_reg_list_length));
214 DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n",
215 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_ucode_ver));
216 DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n",
217 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_feature_ver));
218 DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n",
219 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_size_bytes));
220 DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n",
221 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_offset_bytes));
222 DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n",
223 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_ucode_ver));
224 DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n",
225 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_feature_ver));
226 DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n",
227 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_size_bytes));
228 DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n",
229 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_offset_bytes));
230 DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n",
231 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_ucode_ver));
232 DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n",
233 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_feature_ver));
234 DRM_DEBUG("save_restore_list_srm_size_bytes %u\n",
235 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_size_bytes));
236 DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n",
237 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_offset_bytes));
238 break;
239 case 2:
240 /* rlc_hdr v2_2 */
241 DRM_DEBUG("rlc_iram_ucode_size_bytes: %u\n",
242 le32_to_cpu(rlc_hdr_v2_2->rlc_iram_ucode_size_bytes));
243 DRM_DEBUG("rlc_iram_ucode_offset_bytes: %u\n",
244 le32_to_cpu(rlc_hdr_v2_2->rlc_iram_ucode_offset_bytes));
245 DRM_DEBUG("rlc_dram_ucode_size_bytes: %u\n",
246 le32_to_cpu(rlc_hdr_v2_2->rlc_dram_ucode_size_bytes));
247 DRM_DEBUG("rlc_dram_ucode_offset_bytes: %u\n",
248 le32_to_cpu(rlc_hdr_v2_2->rlc_dram_ucode_offset_bytes));
249 break;
250 case 3:
251 /* rlc_hdr v2_3 */
252 DRM_DEBUG("rlcp_ucode_version: %u\n",
253 le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_version));
254 DRM_DEBUG("rlcp_ucode_feature_version: %u\n",
255 le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_feature_version));
256 DRM_DEBUG("rlcp_ucode_size_bytes: %u\n",
257 le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_size_bytes));
258 DRM_DEBUG("rlcp_ucode_offset_bytes: %u\n",
259 le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_offset_bytes));
260 DRM_DEBUG("rlcv_ucode_version: %u\n",
261 le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_version));
262 DRM_DEBUG("rlcv_ucode_feature_version: %u\n",
263 le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_feature_version));
264 DRM_DEBUG("rlcv_ucode_size_bytes: %u\n",
265 le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_size_bytes));
266 DRM_DEBUG("rlcv_ucode_offset_bytes: %u\n",
267 le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_offset_bytes));
268 break;
269 case 4:
270 /* rlc_hdr v2_4 */
271 DRM_DEBUG("global_tap_delays_ucode_size_bytes :%u\n",
272 le32_to_cpu(rlc_hdr_v2_4->global_tap_delays_ucode_size_bytes));
273 DRM_DEBUG("global_tap_delays_ucode_offset_bytes: %u\n",
274 le32_to_cpu(rlc_hdr_v2_4->global_tap_delays_ucode_offset_bytes));
275 DRM_DEBUG("se0_tap_delays_ucode_size_bytes :%u\n",
276 le32_to_cpu(rlc_hdr_v2_4->se0_tap_delays_ucode_size_bytes));
277 DRM_DEBUG("se0_tap_delays_ucode_offset_bytes: %u\n",
278 le32_to_cpu(rlc_hdr_v2_4->se0_tap_delays_ucode_offset_bytes));
279 DRM_DEBUG("se1_tap_delays_ucode_size_bytes :%u\n",
280 le32_to_cpu(rlc_hdr_v2_4->se1_tap_delays_ucode_size_bytes));
281 DRM_DEBUG("se1_tap_delays_ucode_offset_bytes: %u\n",
282 le32_to_cpu(rlc_hdr_v2_4->se1_tap_delays_ucode_offset_bytes));
283 DRM_DEBUG("se2_tap_delays_ucode_size_bytes :%u\n",
284 le32_to_cpu(rlc_hdr_v2_4->se2_tap_delays_ucode_size_bytes));
285 DRM_DEBUG("se2_tap_delays_ucode_offset_bytes: %u\n",
286 le32_to_cpu(rlc_hdr_v2_4->se2_tap_delays_ucode_offset_bytes));
287 DRM_DEBUG("se3_tap_delays_ucode_size_bytes :%u\n",
288 le32_to_cpu(rlc_hdr_v2_4->se3_tap_delays_ucode_size_bytes));
289 DRM_DEBUG("se3_tap_delays_ucode_offset_bytes: %u\n",
290 le32_to_cpu(rlc_hdr_v2_4->se3_tap_delays_ucode_offset_bytes));
291 break;
292 case 5:
293 /* rlc_hdr v2_5 */
294 DRM_DEBUG("rlc_iram_ucode_size_bytes: %u\n",
295 le32_to_cpu(rlc_hdr_v2_5->v2_2.rlc_iram_ucode_size_bytes));
296 DRM_DEBUG("rlc_iram_ucode_offset_bytes: %u\n",
297 le32_to_cpu(rlc_hdr_v2_5->v2_2.rlc_iram_ucode_offset_bytes));
298 DRM_DEBUG("rlc_dram_ucode_size_bytes: %u\n",
299 le32_to_cpu(rlc_hdr_v2_5->v2_2.rlc_dram_ucode_size_bytes));
300 DRM_DEBUG("rlc_dram_ucode_offset_bytes: %u\n",
301 le32_to_cpu(rlc_hdr_v2_5->v2_2.rlc_dram_ucode_offset_bytes));
302 /* rlc_hdr v2_5 */
303 DRM_DEBUG("rlc_1_iram_ucode_size_bytes: %u\n",
304 le32_to_cpu(rlc_hdr_v2_5->rlc_1_iram_ucode_size_bytes));
305 DRM_DEBUG("rlc_1_iram_ucode_offset_bytes: %u\n",
306 le32_to_cpu(rlc_hdr_v2_5->rlc_1_iram_ucode_offset_bytes));
307 DRM_DEBUG("rlc_1_dram_ucode_size_bytes: %u\n",
308 le32_to_cpu(rlc_hdr_v2_5->rlc_1_dram_ucode_size_bytes));
309 DRM_DEBUG("rlc_1_dram_ucode_offset_bytes: %u\n",
310 le32_to_cpu(rlc_hdr_v2_5->rlc_1_dram_ucode_offset_bytes));
311 break;
312 default:
313 DRM_ERROR("Unknown RLC v2 ucode: v2.%u\n", version_minor);
314 break;
315 }
316 } else {
317 DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor);
318 }
319}
320
321void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr)
322{
323 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
324 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
325
326 DRM_DEBUG("SDMA\n");
327 amdgpu_ucode_print_common_hdr(hdr);
328
329 if (version_major == 1) {
330 const struct sdma_firmware_header_v1_0 *sdma_hdr =
331 container_of(hdr, struct sdma_firmware_header_v1_0, header);
332
333 DRM_DEBUG("ucode_feature_version: %u\n",
334 le32_to_cpu(sdma_hdr->ucode_feature_version));
335 DRM_DEBUG("ucode_change_version: %u\n",
336 le32_to_cpu(sdma_hdr->ucode_change_version));
337 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset));
338 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size));
339 if (version_minor >= 1) {
340 const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr =
341 container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0);
342 DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size));
343 }
344 } else if (version_major == 2) {
345 const struct sdma_firmware_header_v2_0 *sdma_hdr =
346 container_of(hdr, struct sdma_firmware_header_v2_0, header);
347
348 DRM_DEBUG("ucode_feature_version: %u\n",
349 le32_to_cpu(sdma_hdr->ucode_feature_version));
350 DRM_DEBUG("ctx_jt_offset: %u\n", le32_to_cpu(sdma_hdr->ctx_jt_offset));
351 DRM_DEBUG("ctx_jt_size: %u\n", le32_to_cpu(sdma_hdr->ctx_jt_size));
352 DRM_DEBUG("ctl_ucode_offset: %u\n", le32_to_cpu(sdma_hdr->ctl_ucode_offset));
353 DRM_DEBUG("ctl_jt_offset: %u\n", le32_to_cpu(sdma_hdr->ctl_jt_offset));
354 DRM_DEBUG("ctl_jt_size: %u\n", le32_to_cpu(sdma_hdr->ctl_jt_size));
355 } else if (version_major == 3) {
356 const struct sdma_firmware_header_v3_0 *sdma_hdr =
357 container_of(hdr, struct sdma_firmware_header_v3_0, header);
358
359 DRM_DEBUG("ucode_reversion: %u\n",
360 le32_to_cpu(sdma_hdr->ucode_feature_version));
361 } else {
362 DRM_ERROR("Unknown SDMA ucode version: %u.%u\n",
363 version_major, version_minor);
364 }
365}
366
367void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr)
368{
369 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
370 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
371 uint32_t fw_index;
372 const struct psp_fw_bin_desc *desc;
373
374 DRM_DEBUG("PSP\n");
375 amdgpu_ucode_print_common_hdr(hdr);
376
377 if (version_major == 1) {
378 const struct psp_firmware_header_v1_0 *psp_hdr =
379 container_of(hdr, struct psp_firmware_header_v1_0, header);
380
381 DRM_DEBUG("ucode_feature_version: %u\n",
382 le32_to_cpu(psp_hdr->sos.fw_version));
383 DRM_DEBUG("sos_offset_bytes: %u\n",
384 le32_to_cpu(psp_hdr->sos.offset_bytes));
385 DRM_DEBUG("sos_size_bytes: %u\n",
386 le32_to_cpu(psp_hdr->sos.size_bytes));
387 if (version_minor == 1) {
388 const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 =
389 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0);
390 DRM_DEBUG("toc_header_version: %u\n",
391 le32_to_cpu(psp_hdr_v1_1->toc.fw_version));
392 DRM_DEBUG("toc_offset_bytes: %u\n",
393 le32_to_cpu(psp_hdr_v1_1->toc.offset_bytes));
394 DRM_DEBUG("toc_size_bytes: %u\n",
395 le32_to_cpu(psp_hdr_v1_1->toc.size_bytes));
396 DRM_DEBUG("kdb_header_version: %u\n",
397 le32_to_cpu(psp_hdr_v1_1->kdb.fw_version));
398 DRM_DEBUG("kdb_offset_bytes: %u\n",
399 le32_to_cpu(psp_hdr_v1_1->kdb.offset_bytes));
400 DRM_DEBUG("kdb_size_bytes: %u\n",
401 le32_to_cpu(psp_hdr_v1_1->kdb.size_bytes));
402 }
403 if (version_minor == 2) {
404 const struct psp_firmware_header_v1_2 *psp_hdr_v1_2 =
405 container_of(psp_hdr, struct psp_firmware_header_v1_2, v1_0);
406 DRM_DEBUG("kdb_header_version: %u\n",
407 le32_to_cpu(psp_hdr_v1_2->kdb.fw_version));
408 DRM_DEBUG("kdb_offset_bytes: %u\n",
409 le32_to_cpu(psp_hdr_v1_2->kdb.offset_bytes));
410 DRM_DEBUG("kdb_size_bytes: %u\n",
411 le32_to_cpu(psp_hdr_v1_2->kdb.size_bytes));
412 }
413 if (version_minor == 3) {
414 const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 =
415 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0);
416 const struct psp_firmware_header_v1_3 *psp_hdr_v1_3 =
417 container_of(psp_hdr_v1_1, struct psp_firmware_header_v1_3, v1_1);
418 DRM_DEBUG("toc_header_version: %u\n",
419 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.fw_version));
420 DRM_DEBUG("toc_offset_bytes: %u\n",
421 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.offset_bytes));
422 DRM_DEBUG("toc_size_bytes: %u\n",
423 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.size_bytes));
424 DRM_DEBUG("kdb_header_version: %u\n",
425 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.fw_version));
426 DRM_DEBUG("kdb_offset_bytes: %u\n",
427 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.offset_bytes));
428 DRM_DEBUG("kdb_size_bytes: %u\n",
429 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.size_bytes));
430 DRM_DEBUG("spl_header_version: %u\n",
431 le32_to_cpu(psp_hdr_v1_3->spl.fw_version));
432 DRM_DEBUG("spl_offset_bytes: %u\n",
433 le32_to_cpu(psp_hdr_v1_3->spl.offset_bytes));
434 DRM_DEBUG("spl_size_bytes: %u\n",
435 le32_to_cpu(psp_hdr_v1_3->spl.size_bytes));
436 }
437 } else if (version_major == 2) {
438 const struct psp_firmware_header_v2_0 *psp_hdr_v2_0 =
439 container_of(hdr, struct psp_firmware_header_v2_0, header);
440 for (fw_index = 0; fw_index < le32_to_cpu(psp_hdr_v2_0->psp_fw_bin_count); fw_index++) {
441 desc = &(psp_hdr_v2_0->psp_fw_bin[fw_index]);
442 switch (desc->fw_type) {
443 case PSP_FW_TYPE_PSP_SOS:
444 DRM_DEBUG("psp_sos_version: %u\n",
445 le32_to_cpu(desc->fw_version));
446 DRM_DEBUG("psp_sos_size_bytes: %u\n",
447 le32_to_cpu(desc->size_bytes));
448 break;
449 case PSP_FW_TYPE_PSP_SYS_DRV:
450 DRM_DEBUG("psp_sys_drv_version: %u\n",
451 le32_to_cpu(desc->fw_version));
452 DRM_DEBUG("psp_sys_drv_size_bytes: %u\n",
453 le32_to_cpu(desc->size_bytes));
454 break;
455 case PSP_FW_TYPE_PSP_KDB:
456 DRM_DEBUG("psp_kdb_version: %u\n",
457 le32_to_cpu(desc->fw_version));
458 DRM_DEBUG("psp_kdb_size_bytes: %u\n",
459 le32_to_cpu(desc->size_bytes));
460 break;
461 case PSP_FW_TYPE_PSP_TOC:
462 DRM_DEBUG("psp_toc_version: %u\n",
463 le32_to_cpu(desc->fw_version));
464 DRM_DEBUG("psp_toc_size_bytes: %u\n",
465 le32_to_cpu(desc->size_bytes));
466 break;
467 case PSP_FW_TYPE_PSP_SPL:
468 DRM_DEBUG("psp_spl_version: %u\n",
469 le32_to_cpu(desc->fw_version));
470 DRM_DEBUG("psp_spl_size_bytes: %u\n",
471 le32_to_cpu(desc->size_bytes));
472 break;
473 case PSP_FW_TYPE_PSP_RL:
474 DRM_DEBUG("psp_rl_version: %u\n",
475 le32_to_cpu(desc->fw_version));
476 DRM_DEBUG("psp_rl_size_bytes: %u\n",
477 le32_to_cpu(desc->size_bytes));
478 break;
479 case PSP_FW_TYPE_PSP_SOC_DRV:
480 DRM_DEBUG("psp_soc_drv_version: %u\n",
481 le32_to_cpu(desc->fw_version));
482 DRM_DEBUG("psp_soc_drv_size_bytes: %u\n",
483 le32_to_cpu(desc->size_bytes));
484 break;
485 case PSP_FW_TYPE_PSP_INTF_DRV:
486 DRM_DEBUG("psp_intf_drv_version: %u\n",
487 le32_to_cpu(desc->fw_version));
488 DRM_DEBUG("psp_intf_drv_size_bytes: %u\n",
489 le32_to_cpu(desc->size_bytes));
490 break;
491 case PSP_FW_TYPE_PSP_DBG_DRV:
492 DRM_DEBUG("psp_dbg_drv_version: %u\n",
493 le32_to_cpu(desc->fw_version));
494 DRM_DEBUG("psp_dbg_drv_size_bytes: %u\n",
495 le32_to_cpu(desc->size_bytes));
496 break;
497 case PSP_FW_TYPE_PSP_RAS_DRV:
498 DRM_DEBUG("psp_ras_drv_version: %u\n",
499 le32_to_cpu(desc->fw_version));
500 DRM_DEBUG("psp_ras_drv_size_bytes: %u\n",
501 le32_to_cpu(desc->size_bytes));
502 break;
503 default:
504 DRM_DEBUG("Unsupported PSP fw type: %d\n", desc->fw_type);
505 break;
506 }
507 }
508 } else {
509 DRM_ERROR("Unknown PSP ucode version: %u.%u\n",
510 version_major, version_minor);
511 }
512}
513
514void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr)
515{
516 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
517 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
518
519 DRM_DEBUG("GPU_INFO\n");
520 amdgpu_ucode_print_common_hdr(hdr);
521
522 if (version_major == 1) {
523 const struct gpu_info_firmware_header_v1_0 *gpu_info_hdr =
524 container_of(hdr, struct gpu_info_firmware_header_v1_0, header);
525
526 DRM_DEBUG("version_major: %u\n",
527 le16_to_cpu(gpu_info_hdr->version_major));
528 DRM_DEBUG("version_minor: %u\n",
529 le16_to_cpu(gpu_info_hdr->version_minor));
530 } else {
531 DRM_ERROR("Unknown gpu_info ucode version: %u.%u\n", version_major, version_minor);
532 }
533}
534
535static int amdgpu_ucode_validate(const struct firmware *fw)
536{
537 const struct common_firmware_header *hdr =
538 (const struct common_firmware_header *)fw->data;
539
540 if (fw->size == le32_to_cpu(hdr->size_bytes))
541 return 0;
542
543 return -EINVAL;
544}
545
546bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
547 uint16_t hdr_major, uint16_t hdr_minor)
548{
549 if ((hdr->common.header_version_major == hdr_major) &&
550 (hdr->common.header_version_minor == hdr_minor))
551 return true;
552 return false;
553}
554
555enum amdgpu_firmware_load_type
556amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
557{
558 switch (adev->asic_type) {
559#ifdef CONFIG_DRM_AMDGPU_SI
560 case CHIP_TAHITI:
561 case CHIP_PITCAIRN:
562 case CHIP_VERDE:
563 case CHIP_OLAND:
564 case CHIP_HAINAN:
565 return AMDGPU_FW_LOAD_DIRECT;
566#endif
567#ifdef CONFIG_DRM_AMDGPU_CIK
568 case CHIP_BONAIRE:
569 case CHIP_KAVERI:
570 case CHIP_KABINI:
571 case CHIP_HAWAII:
572 case CHIP_MULLINS:
573 return AMDGPU_FW_LOAD_DIRECT;
574#endif
575 case CHIP_TOPAZ:
576 case CHIP_TONGA:
577 case CHIP_FIJI:
578 case CHIP_CARRIZO:
579 case CHIP_STONEY:
580 case CHIP_POLARIS10:
581 case CHIP_POLARIS11:
582 case CHIP_POLARIS12:
583 case CHIP_VEGAM:
584 return AMDGPU_FW_LOAD_SMU;
585 case CHIP_CYAN_SKILLFISH:
586 if (!(load_type &&
587 adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2))
588 return AMDGPU_FW_LOAD_DIRECT;
589 else
590 return AMDGPU_FW_LOAD_PSP;
591 default:
592 if (!load_type)
593 return AMDGPU_FW_LOAD_DIRECT;
594 else if (load_type == 3)
595 return AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO;
596 else
597 return AMDGPU_FW_LOAD_PSP;
598 }
599}
600
601const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id)
602{
603 switch (ucode_id) {
604 case AMDGPU_UCODE_ID_SDMA0:
605 return "SDMA0";
606 case AMDGPU_UCODE_ID_SDMA1:
607 return "SDMA1";
608 case AMDGPU_UCODE_ID_SDMA2:
609 return "SDMA2";
610 case AMDGPU_UCODE_ID_SDMA3:
611 return "SDMA3";
612 case AMDGPU_UCODE_ID_SDMA4:
613 return "SDMA4";
614 case AMDGPU_UCODE_ID_SDMA5:
615 return "SDMA5";
616 case AMDGPU_UCODE_ID_SDMA6:
617 return "SDMA6";
618 case AMDGPU_UCODE_ID_SDMA7:
619 return "SDMA7";
620 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
621 return "SDMA_CTX";
622 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
623 return "SDMA_CTL";
624 case AMDGPU_UCODE_ID_CP_CE:
625 return "CP_CE";
626 case AMDGPU_UCODE_ID_CP_PFP:
627 return "CP_PFP";
628 case AMDGPU_UCODE_ID_CP_ME:
629 return "CP_ME";
630 case AMDGPU_UCODE_ID_CP_MEC1:
631 return "CP_MEC1";
632 case AMDGPU_UCODE_ID_CP_MEC1_JT:
633 return "CP_MEC1_JT";
634 case AMDGPU_UCODE_ID_CP_MEC2:
635 return "CP_MEC2";
636 case AMDGPU_UCODE_ID_CP_MEC2_JT:
637 return "CP_MEC2_JT";
638 case AMDGPU_UCODE_ID_CP_MES:
639 return "CP_MES";
640 case AMDGPU_UCODE_ID_CP_MES_DATA:
641 return "CP_MES_DATA";
642 case AMDGPU_UCODE_ID_CP_MES1:
643 return "CP_MES_KIQ";
644 case AMDGPU_UCODE_ID_CP_MES1_DATA:
645 return "CP_MES_KIQ_DATA";
646 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
647 return "RLC_RESTORE_LIST_CNTL";
648 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
649 return "RLC_RESTORE_LIST_GPM_MEM";
650 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
651 return "RLC_RESTORE_LIST_SRM_MEM";
652 case AMDGPU_UCODE_ID_RLC_IRAM:
653 return "RLC_IRAM";
654 case AMDGPU_UCODE_ID_RLC_DRAM:
655 return "RLC_DRAM";
656 case AMDGPU_UCODE_ID_RLC_IRAM_1:
657 return "RLC_IRAM_1";
658 case AMDGPU_UCODE_ID_RLC_DRAM_1:
659 return "RLC_DRAM_1";
660 case AMDGPU_UCODE_ID_RLC_G:
661 return "RLC_G";
662 case AMDGPU_UCODE_ID_RLC_P:
663 return "RLC_P";
664 case AMDGPU_UCODE_ID_RLC_V:
665 return "RLC_V";
666 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
667 return "GLOBAL_TAP_DELAYS";
668 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS:
669 return "SE0_TAP_DELAYS";
670 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS:
671 return "SE1_TAP_DELAYS";
672 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS:
673 return "SE2_TAP_DELAYS";
674 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS:
675 return "SE3_TAP_DELAYS";
676 case AMDGPU_UCODE_ID_IMU_I:
677 return "IMU_I";
678 case AMDGPU_UCODE_ID_IMU_D:
679 return "IMU_D";
680 case AMDGPU_UCODE_ID_STORAGE:
681 return "STORAGE";
682 case AMDGPU_UCODE_ID_SMC:
683 return "SMC";
684 case AMDGPU_UCODE_ID_PPTABLE:
685 return "PPTABLE";
686 case AMDGPU_UCODE_ID_P2S_TABLE:
687 return "P2STABLE";
688 case AMDGPU_UCODE_ID_UVD:
689 return "UVD";
690 case AMDGPU_UCODE_ID_UVD1:
691 return "UVD1";
692 case AMDGPU_UCODE_ID_VCE:
693 return "VCE";
694 case AMDGPU_UCODE_ID_VCN:
695 return "VCN";
696 case AMDGPU_UCODE_ID_VCN1:
697 return "VCN1";
698 case AMDGPU_UCODE_ID_DMCU_ERAM:
699 return "DMCU_ERAM";
700 case AMDGPU_UCODE_ID_DMCU_INTV:
701 return "DMCU_INTV";
702 case AMDGPU_UCODE_ID_VCN0_RAM:
703 return "VCN0_RAM";
704 case AMDGPU_UCODE_ID_VCN1_RAM:
705 return "VCN1_RAM";
706 case AMDGPU_UCODE_ID_DMCUB:
707 return "DMCUB";
708 case AMDGPU_UCODE_ID_CAP:
709 return "CAP";
710 case AMDGPU_UCODE_ID_VPE_CTX:
711 return "VPE_CTX";
712 case AMDGPU_UCODE_ID_VPE_CTL:
713 return "VPE_CTL";
714 case AMDGPU_UCODE_ID_VPE:
715 return "VPE";
716 case AMDGPU_UCODE_ID_UMSCH_MM_UCODE:
717 return "UMSCH_MM_UCODE";
718 case AMDGPU_UCODE_ID_UMSCH_MM_DATA:
719 return "UMSCH_MM_DATA";
720 case AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER:
721 return "UMSCH_MM_CMD_BUFFER";
722 case AMDGPU_UCODE_ID_JPEG_RAM:
723 return "JPEG";
724 case AMDGPU_UCODE_ID_SDMA_RS64:
725 return "RS64_SDMA";
726 case AMDGPU_UCODE_ID_CP_RS64_PFP:
727 return "RS64_PFP";
728 case AMDGPU_UCODE_ID_CP_RS64_ME:
729 return "RS64_ME";
730 case AMDGPU_UCODE_ID_CP_RS64_MEC:
731 return "RS64_MEC";
732 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
733 return "RS64_PFP_P0_STACK";
734 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
735 return "RS64_PFP_P1_STACK";
736 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
737 return "RS64_ME_P0_STACK";
738 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
739 return "RS64_ME_P1_STACK";
740 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
741 return "RS64_MEC_P0_STACK";
742 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
743 return "RS64_MEC_P1_STACK";
744 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
745 return "RS64_MEC_P2_STACK";
746 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
747 return "RS64_MEC_P3_STACK";
748 case AMDGPU_UCODE_ID_ISP:
749 return "ISP";
750 default:
751 return "UNKNOWN UCODE";
752 }
753}
754
755static inline int amdgpu_ucode_is_valid(uint32_t fw_version)
756{
757 if (!fw_version)
758 return -EINVAL;
759
760 return 0;
761}
762
763#define FW_VERSION_ATTR(name, mode, field) \
764static ssize_t show_##name(struct device *dev, \
765 struct device_attribute *attr, char *buf) \
766{ \
767 struct drm_device *ddev = dev_get_drvdata(dev); \
768 struct amdgpu_device *adev = drm_to_adev(ddev); \
769 \
770 if (!buf) \
771 return amdgpu_ucode_is_valid(adev->field); \
772 \
773 return sysfs_emit(buf, "0x%08x\n", adev->field); \
774} \
775static DEVICE_ATTR(name, mode, show_##name, NULL)
776
777FW_VERSION_ATTR(vce_fw_version, 0444, vce.fw_version);
778FW_VERSION_ATTR(uvd_fw_version, 0444, uvd.fw_version);
779FW_VERSION_ATTR(mc_fw_version, 0444, gmc.fw_version);
780FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version);
781FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version);
782FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version);
783FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version);
784FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version);
785FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version);
786FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version);
787FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version);
788FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version);
789FW_VERSION_ATTR(imu_fw_version, 0444, gfx.imu_fw_version);
790FW_VERSION_ATTR(sos_fw_version, 0444, psp.sos.fw_version);
791FW_VERSION_ATTR(asd_fw_version, 0444, psp.asd_context.bin_desc.fw_version);
792FW_VERSION_ATTR(ta_ras_fw_version, 0444, psp.ras_context.context.bin_desc.fw_version);
793FW_VERSION_ATTR(ta_xgmi_fw_version, 0444, psp.xgmi_context.context.bin_desc.fw_version);
794FW_VERSION_ATTR(smc_fw_version, 0444, pm.fw_version);
795FW_VERSION_ATTR(sdma_fw_version, 0444, sdma.instance[0].fw_version);
796FW_VERSION_ATTR(sdma2_fw_version, 0444, sdma.instance[1].fw_version);
797FW_VERSION_ATTR(vcn_fw_version, 0444, vcn.fw_version);
798FW_VERSION_ATTR(dmcu_fw_version, 0444, dm.dmcu_fw_version);
799FW_VERSION_ATTR(dmcub_fw_version, 0444, dm.dmcub_fw_version);
800FW_VERSION_ATTR(mes_fw_version, 0444, mes.sched_version & AMDGPU_MES_VERSION_MASK);
801FW_VERSION_ATTR(mes_kiq_fw_version, 0444, mes.kiq_version & AMDGPU_MES_VERSION_MASK);
802FW_VERSION_ATTR(pldm_fw_version, 0444, firmware.pldm_version);
803
804static struct attribute *fw_attrs[] = {
805 &dev_attr_vce_fw_version.attr, &dev_attr_uvd_fw_version.attr,
806 &dev_attr_mc_fw_version.attr, &dev_attr_me_fw_version.attr,
807 &dev_attr_pfp_fw_version.attr, &dev_attr_ce_fw_version.attr,
808 &dev_attr_rlc_fw_version.attr, &dev_attr_rlc_srlc_fw_version.attr,
809 &dev_attr_rlc_srlg_fw_version.attr, &dev_attr_rlc_srls_fw_version.attr,
810 &dev_attr_mec_fw_version.attr, &dev_attr_mec2_fw_version.attr,
811 &dev_attr_sos_fw_version.attr, &dev_attr_asd_fw_version.attr,
812 &dev_attr_ta_ras_fw_version.attr, &dev_attr_ta_xgmi_fw_version.attr,
813 &dev_attr_smc_fw_version.attr, &dev_attr_sdma_fw_version.attr,
814 &dev_attr_sdma2_fw_version.attr, &dev_attr_vcn_fw_version.attr,
815 &dev_attr_dmcu_fw_version.attr, &dev_attr_dmcub_fw_version.attr,
816 &dev_attr_imu_fw_version.attr, &dev_attr_mes_fw_version.attr,
817 &dev_attr_mes_kiq_fw_version.attr, &dev_attr_pldm_fw_version.attr,
818 NULL
819};
820
821#define to_dev_attr(x) container_of(x, struct device_attribute, attr)
822
823static umode_t amdgpu_ucode_sys_visible(struct kobject *kobj,
824 struct attribute *attr, int idx)
825{
826 struct device_attribute *dev_attr = to_dev_attr(attr);
827 struct device *dev = kobj_to_dev(kobj);
828
829 if (dev_attr->show(dev, dev_attr, NULL) == -EINVAL)
830 return 0;
831
832 return attr->mode;
833}
834
835static const struct attribute_group fw_attr_group = {
836 .name = "fw_version",
837 .attrs = fw_attrs,
838 .is_visible = amdgpu_ucode_sys_visible
839};
840
841int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev)
842{
843 return sysfs_create_group(&adev->dev->kobj, &fw_attr_group);
844}
845
846void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev)
847{
848 sysfs_remove_group(&adev->dev->kobj, &fw_attr_group);
849}
850
851static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
852 struct amdgpu_firmware_info *ucode,
853 uint64_t mc_addr, void *kptr)
854{
855 const struct common_firmware_header *header = NULL;
856 const struct gfx_firmware_header_v1_0 *cp_hdr = NULL;
857 const struct gfx_firmware_header_v2_0 *cpv2_hdr = NULL;
858 const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL;
859 const struct dmcub_firmware_header_v1_0 *dmcub_hdr = NULL;
860 const struct mes_firmware_header_v1_0 *mes_hdr = NULL;
861 const struct sdma_firmware_header_v2_0 *sdma_hdr = NULL;
862 const struct sdma_firmware_header_v3_0 *sdmav3_hdr = NULL;
863 const struct imu_firmware_header_v1_0 *imu_hdr = NULL;
864 const struct vpe_firmware_header_v1_0 *vpe_hdr = NULL;
865 const struct umsch_mm_firmware_header_v1_0 *umsch_mm_hdr = NULL;
866 u8 *ucode_addr;
867
868 if (!ucode->fw)
869 return 0;
870
871 ucode->mc_addr = mc_addr;
872 ucode->kaddr = kptr;
873
874 if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE)
875 return 0;
876
877 header = (const struct common_firmware_header *)ucode->fw->data;
878 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
879 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)ucode->fw->data;
880 dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data;
881 dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data;
882 mes_hdr = (const struct mes_firmware_header_v1_0 *)ucode->fw->data;
883 sdma_hdr = (const struct sdma_firmware_header_v2_0 *)ucode->fw->data;
884 sdmav3_hdr = (const struct sdma_firmware_header_v3_0 *)ucode->fw->data;
885 imu_hdr = (const struct imu_firmware_header_v1_0 *)ucode->fw->data;
886 vpe_hdr = (const struct vpe_firmware_header_v1_0 *)ucode->fw->data;
887 umsch_mm_hdr = (const struct umsch_mm_firmware_header_v1_0 *)ucode->fw->data;
888
889 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
890 switch (ucode->ucode_id) {
891 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
892 ucode->ucode_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes);
893 ucode_addr = (u8 *)ucode->fw->data +
894 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes);
895 break;
896 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
897 ucode->ucode_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes);
898 ucode_addr = (u8 *)ucode->fw->data +
899 le32_to_cpu(sdma_hdr->ctl_ucode_offset);
900 break;
901 case AMDGPU_UCODE_ID_SDMA_RS64:
902 ucode->ucode_size = le32_to_cpu(sdmav3_hdr->ucode_size_bytes);
903 ucode_addr = (u8 *)ucode->fw->data +
904 le32_to_cpu(sdmav3_hdr->header.ucode_array_offset_bytes);
905 break;
906 case AMDGPU_UCODE_ID_CP_MEC1:
907 case AMDGPU_UCODE_ID_CP_MEC2:
908 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
909 le32_to_cpu(cp_hdr->jt_size) * 4;
910 ucode_addr = (u8 *)ucode->fw->data +
911 le32_to_cpu(header->ucode_array_offset_bytes);
912 break;
913 case AMDGPU_UCODE_ID_CP_MEC1_JT:
914 case AMDGPU_UCODE_ID_CP_MEC2_JT:
915 ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4;
916 ucode_addr = (u8 *)ucode->fw->data +
917 le32_to_cpu(header->ucode_array_offset_bytes) +
918 le32_to_cpu(cp_hdr->jt_offset) * 4;
919 break;
920 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
921 ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes;
922 ucode_addr = adev->gfx.rlc.save_restore_list_cntl;
923 break;
924 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
925 ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes;
926 ucode_addr = adev->gfx.rlc.save_restore_list_gpm;
927 break;
928 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
929 ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes;
930 ucode_addr = adev->gfx.rlc.save_restore_list_srm;
931 break;
932 case AMDGPU_UCODE_ID_RLC_IRAM:
933 ucode->ucode_size = adev->gfx.rlc.rlc_iram_ucode_size_bytes;
934 ucode_addr = adev->gfx.rlc.rlc_iram_ucode;
935 break;
936 case AMDGPU_UCODE_ID_RLC_DRAM:
937 ucode->ucode_size = adev->gfx.rlc.rlc_dram_ucode_size_bytes;
938 ucode_addr = adev->gfx.rlc.rlc_dram_ucode;
939 break;
940 case AMDGPU_UCODE_ID_RLC_IRAM_1:
941 ucode->ucode_size = adev->gfx.rlc.rlc_1_iram_ucode_size_bytes;
942 ucode_addr = adev->gfx.rlc.rlc_1_iram_ucode;
943 break;
944 case AMDGPU_UCODE_ID_RLC_DRAM_1:
945 ucode->ucode_size = adev->gfx.rlc.rlc_1_dram_ucode_size_bytes;
946 ucode_addr = adev->gfx.rlc.rlc_1_dram_ucode;
947 break;
948 case AMDGPU_UCODE_ID_RLC_P:
949 ucode->ucode_size = adev->gfx.rlc.rlcp_ucode_size_bytes;
950 ucode_addr = adev->gfx.rlc.rlcp_ucode;
951 break;
952 case AMDGPU_UCODE_ID_RLC_V:
953 ucode->ucode_size = adev->gfx.rlc.rlcv_ucode_size_bytes;
954 ucode_addr = adev->gfx.rlc.rlcv_ucode;
955 break;
956 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
957 ucode->ucode_size = adev->gfx.rlc.global_tap_delays_ucode_size_bytes;
958 ucode_addr = adev->gfx.rlc.global_tap_delays_ucode;
959 break;
960 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS:
961 ucode->ucode_size = adev->gfx.rlc.se0_tap_delays_ucode_size_bytes;
962 ucode_addr = adev->gfx.rlc.se0_tap_delays_ucode;
963 break;
964 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS:
965 ucode->ucode_size = adev->gfx.rlc.se1_tap_delays_ucode_size_bytes;
966 ucode_addr = adev->gfx.rlc.se1_tap_delays_ucode;
967 break;
968 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS:
969 ucode->ucode_size = adev->gfx.rlc.se2_tap_delays_ucode_size_bytes;
970 ucode_addr = adev->gfx.rlc.se2_tap_delays_ucode;
971 break;
972 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS:
973 ucode->ucode_size = adev->gfx.rlc.se3_tap_delays_ucode_size_bytes;
974 ucode_addr = adev->gfx.rlc.se3_tap_delays_ucode;
975 break;
976 case AMDGPU_UCODE_ID_CP_MES:
977 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
978 ucode_addr = (u8 *)ucode->fw->data +
979 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes);
980 break;
981 case AMDGPU_UCODE_ID_CP_MES_DATA:
982 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
983 ucode_addr = (u8 *)ucode->fw->data +
984 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes);
985 break;
986 case AMDGPU_UCODE_ID_CP_MES1:
987 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
988 ucode_addr = (u8 *)ucode->fw->data +
989 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes);
990 break;
991 case AMDGPU_UCODE_ID_CP_MES1_DATA:
992 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
993 ucode_addr = (u8 *)ucode->fw->data +
994 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes);
995 break;
996 case AMDGPU_UCODE_ID_DMCU_ERAM:
997 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
998 le32_to_cpu(dmcu_hdr->intv_size_bytes);
999 ucode_addr = (u8 *)ucode->fw->data +
1000 le32_to_cpu(header->ucode_array_offset_bytes);
1001 break;
1002 case AMDGPU_UCODE_ID_DMCU_INTV:
1003 ucode->ucode_size = le32_to_cpu(dmcu_hdr->intv_size_bytes);
1004 ucode_addr = (u8 *)ucode->fw->data +
1005 le32_to_cpu(header->ucode_array_offset_bytes) +
1006 le32_to_cpu(dmcu_hdr->intv_offset_bytes);
1007 break;
1008 case AMDGPU_UCODE_ID_DMCUB:
1009 ucode->ucode_size = le32_to_cpu(dmcub_hdr->inst_const_bytes);
1010 ucode_addr = (u8 *)ucode->fw->data +
1011 le32_to_cpu(header->ucode_array_offset_bytes);
1012 break;
1013 case AMDGPU_UCODE_ID_PPTABLE:
1014 ucode->ucode_size = ucode->fw->size;
1015 ucode_addr = (u8 *)ucode->fw->data;
1016 break;
1017 case AMDGPU_UCODE_ID_P2S_TABLE:
1018 ucode->ucode_size = ucode->fw->size;
1019 ucode_addr = (u8 *)ucode->fw->data;
1020 break;
1021 case AMDGPU_UCODE_ID_IMU_I:
1022 ucode->ucode_size = le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes);
1023 ucode_addr = (u8 *)ucode->fw->data +
1024 le32_to_cpu(imu_hdr->header.ucode_array_offset_bytes);
1025 break;
1026 case AMDGPU_UCODE_ID_IMU_D:
1027 ucode->ucode_size = le32_to_cpu(imu_hdr->imu_dram_ucode_size_bytes);
1028 ucode_addr = (u8 *)ucode->fw->data +
1029 le32_to_cpu(imu_hdr->header.ucode_array_offset_bytes) +
1030 le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes);
1031 break;
1032 case AMDGPU_UCODE_ID_CP_RS64_PFP:
1033 ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1034 ucode_addr = (u8 *)ucode->fw->data +
1035 le32_to_cpu(header->ucode_array_offset_bytes);
1036 break;
1037 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
1038 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1039 ucode_addr = (u8 *)ucode->fw->data +
1040 le32_to_cpu(cpv2_hdr->data_offset_bytes);
1041 break;
1042 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
1043 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1044 ucode_addr = (u8 *)ucode->fw->data +
1045 le32_to_cpu(cpv2_hdr->data_offset_bytes);
1046 break;
1047 case AMDGPU_UCODE_ID_CP_RS64_ME:
1048 ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1049 ucode_addr = (u8 *)ucode->fw->data +
1050 le32_to_cpu(header->ucode_array_offset_bytes);
1051 break;
1052 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
1053 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1054 ucode_addr = (u8 *)ucode->fw->data +
1055 le32_to_cpu(cpv2_hdr->data_offset_bytes);
1056 break;
1057 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
1058 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1059 ucode_addr = (u8 *)ucode->fw->data +
1060 le32_to_cpu(cpv2_hdr->data_offset_bytes);
1061 break;
1062 case AMDGPU_UCODE_ID_CP_RS64_MEC:
1063 ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1064 ucode_addr = (u8 *)ucode->fw->data +
1065 le32_to_cpu(header->ucode_array_offset_bytes);
1066 break;
1067 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
1068 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1069 ucode_addr = (u8 *)ucode->fw->data +
1070 le32_to_cpu(cpv2_hdr->data_offset_bytes);
1071 break;
1072 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
1073 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1074 ucode_addr = (u8 *)ucode->fw->data +
1075 le32_to_cpu(cpv2_hdr->data_offset_bytes);
1076 break;
1077 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
1078 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1079 ucode_addr = (u8 *)ucode->fw->data +
1080 le32_to_cpu(cpv2_hdr->data_offset_bytes);
1081 break;
1082 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
1083 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1084 ucode_addr = (u8 *)ucode->fw->data +
1085 le32_to_cpu(cpv2_hdr->data_offset_bytes);
1086 break;
1087 case AMDGPU_UCODE_ID_VPE_CTX:
1088 ucode->ucode_size = le32_to_cpu(vpe_hdr->ctx_ucode_size_bytes);
1089 ucode_addr = (u8 *)ucode->fw->data +
1090 le32_to_cpu(vpe_hdr->header.ucode_array_offset_bytes);
1091 break;
1092 case AMDGPU_UCODE_ID_VPE_CTL:
1093 ucode->ucode_size = le32_to_cpu(vpe_hdr->ctl_ucode_size_bytes);
1094 ucode_addr = (u8 *)ucode->fw->data +
1095 le32_to_cpu(vpe_hdr->ctl_ucode_offset);
1096 break;
1097 case AMDGPU_UCODE_ID_UMSCH_MM_UCODE:
1098 ucode->ucode_size = le32_to_cpu(umsch_mm_hdr->umsch_mm_ucode_size_bytes);
1099 ucode_addr = (u8 *)ucode->fw->data +
1100 le32_to_cpu(umsch_mm_hdr->header.ucode_array_offset_bytes);
1101 break;
1102 case AMDGPU_UCODE_ID_UMSCH_MM_DATA:
1103 ucode->ucode_size = le32_to_cpu(umsch_mm_hdr->umsch_mm_ucode_data_size_bytes);
1104 ucode_addr = (u8 *)ucode->fw->data +
1105 le32_to_cpu(umsch_mm_hdr->umsch_mm_ucode_data_offset_bytes);
1106 break;
1107 default:
1108 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
1109 ucode_addr = (u8 *)ucode->fw->data +
1110 le32_to_cpu(header->ucode_array_offset_bytes);
1111 break;
1112 }
1113 } else {
1114 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
1115 ucode_addr = (u8 *)ucode->fw->data +
1116 le32_to_cpu(header->ucode_array_offset_bytes);
1117 }
1118
1119 memcpy(ucode->kaddr, ucode_addr, ucode->ucode_size);
1120
1121 return 0;
1122}
1123
1124static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode,
1125 uint64_t mc_addr, void *kptr)
1126{
1127 const struct gfx_firmware_header_v1_0 *header = NULL;
1128 const struct common_firmware_header *comm_hdr = NULL;
1129 uint8_t *src_addr = NULL;
1130 uint8_t *dst_addr = NULL;
1131
1132 if (!ucode->fw)
1133 return 0;
1134
1135 comm_hdr = (const struct common_firmware_header *)ucode->fw->data;
1136 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
1137 dst_addr = ucode->kaddr +
1138 ALIGN(le32_to_cpu(comm_hdr->ucode_size_bytes),
1139 PAGE_SIZE);
1140 src_addr = (uint8_t *)ucode->fw->data +
1141 le32_to_cpu(comm_hdr->ucode_array_offset_bytes) +
1142 (le32_to_cpu(header->jt_offset) * 4);
1143 memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4);
1144
1145 return 0;
1146}
1147
1148int amdgpu_ucode_create_bo(struct amdgpu_device *adev)
1149{
1150 if ((adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) &&
1151 (adev->firmware.load_type != AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)) {
1152 amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE,
1153 (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf || adev->gmc.xgmi.connected_to_cpu) ?
1154 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
1155 &adev->firmware.fw_buf,
1156 &adev->firmware.fw_buf_mc,
1157 &adev->firmware.fw_buf_ptr);
1158 if (!adev->firmware.fw_buf) {
1159 dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n");
1160 return -ENOMEM;
1161 } else if (amdgpu_sriov_vf(adev)) {
1162 memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size);
1163 }
1164 }
1165 return 0;
1166}
1167
1168void amdgpu_ucode_free_bo(struct amdgpu_device *adev)
1169{
1170 amdgpu_bo_free_kernel(&adev->firmware.fw_buf,
1171 &adev->firmware.fw_buf_mc,
1172 &adev->firmware.fw_buf_ptr);
1173}
1174
1175int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
1176{
1177 uint64_t fw_offset = 0;
1178 int i;
1179 struct amdgpu_firmware_info *ucode = NULL;
1180
1181 /* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo when reset/suspend */
1182 if (!amdgpu_sriov_vf(adev) && (amdgpu_in_reset(adev) || adev->in_suspend))
1183 return 0;
1184 /*
1185 * if SMU loaded firmware, it needn't add SMC, UVD, and VCE
1186 * ucode info here
1187 */
1188 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1189 if (amdgpu_sriov_vf(adev))
1190 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 3;
1191 else
1192 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 4;
1193 } else {
1194 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM;
1195 }
1196
1197 if (amdgpu_virt_xgmi_migrate_enabled(adev) && adev->firmware.fw_buf)
1198 adev->firmware.fw_buf_mc = amdgpu_bo_fb_aper_addr(adev->firmware.fw_buf);
1199
1200 for (i = 0; i < adev->firmware.max_ucodes; i++) {
1201 ucode = &adev->firmware.ucode[i];
1202 if (ucode->fw) {
1203 amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset,
1204 adev->firmware.fw_buf_ptr + fw_offset);
1205 if (i == AMDGPU_UCODE_ID_CP_MEC1 &&
1206 adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1207 const struct gfx_firmware_header_v1_0 *cp_hdr;
1208
1209 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
1210 amdgpu_ucode_patch_jt(ucode, adev->firmware.fw_buf_mc + fw_offset,
1211 adev->firmware.fw_buf_ptr + fw_offset);
1212 fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
1213 }
1214 fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE);
1215 }
1216 }
1217 return 0;
1218}
1219
1220static const char *amdgpu_ucode_legacy_naming(struct amdgpu_device *adev, int block_type)
1221{
1222 if (block_type == MP0_HWIP) {
1223 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
1224 case IP_VERSION(9, 0, 0):
1225 switch (adev->asic_type) {
1226 case CHIP_VEGA10:
1227 return "vega10";
1228 case CHIP_VEGA12:
1229 return "vega12";
1230 default:
1231 return NULL;
1232 }
1233 case IP_VERSION(10, 0, 0):
1234 case IP_VERSION(10, 0, 1):
1235 if (adev->asic_type == CHIP_RAVEN) {
1236 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1237 return "raven2";
1238 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1239 return "picasso";
1240 return "raven";
1241 }
1242 break;
1243 case IP_VERSION(11, 0, 0):
1244 return "navi10";
1245 case IP_VERSION(11, 0, 2):
1246 return "vega20";
1247 case IP_VERSION(11, 0, 3):
1248 return "renoir";
1249 case IP_VERSION(11, 0, 4):
1250 return "arcturus";
1251 case IP_VERSION(11, 0, 5):
1252 return "navi14";
1253 case IP_VERSION(11, 0, 7):
1254 return "sienna_cichlid";
1255 case IP_VERSION(11, 0, 9):
1256 return "navi12";
1257 case IP_VERSION(11, 0, 11):
1258 return "navy_flounder";
1259 case IP_VERSION(11, 0, 12):
1260 return "dimgrey_cavefish";
1261 case IP_VERSION(11, 0, 13):
1262 return "beige_goby";
1263 case IP_VERSION(11, 5, 0):
1264 case IP_VERSION(11, 5, 2):
1265 return "vangogh";
1266 case IP_VERSION(12, 0, 1):
1267 return "green_sardine";
1268 case IP_VERSION(13, 0, 2):
1269 return "aldebaran";
1270 case IP_VERSION(13, 0, 1):
1271 case IP_VERSION(13, 0, 3):
1272 return "yellow_carp";
1273 }
1274 } else if (block_type == MP1_HWIP) {
1275 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
1276 case IP_VERSION(9, 0, 0):
1277 case IP_VERSION(10, 0, 0):
1278 case IP_VERSION(10, 0, 1):
1279 case IP_VERSION(11, 0, 2):
1280 if (adev->asic_type == CHIP_ARCTURUS)
1281 return "arcturus_smc";
1282 return NULL;
1283 case IP_VERSION(11, 0, 0):
1284 return "navi10_smc";
1285 case IP_VERSION(11, 0, 5):
1286 return "navi14_smc";
1287 case IP_VERSION(11, 0, 9):
1288 return "navi12_smc";
1289 case IP_VERSION(11, 0, 7):
1290 return "sienna_cichlid_smc";
1291 case IP_VERSION(11, 0, 11):
1292 return "navy_flounder_smc";
1293 case IP_VERSION(11, 0, 12):
1294 return "dimgrey_cavefish_smc";
1295 case IP_VERSION(11, 0, 13):
1296 return "beige_goby_smc";
1297 case IP_VERSION(13, 0, 2):
1298 return "aldebaran_smc";
1299 }
1300 } else if (block_type == SDMA0_HWIP) {
1301 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
1302 case IP_VERSION(4, 0, 0):
1303 return "vega10_sdma";
1304 case IP_VERSION(4, 0, 1):
1305 return "vega12_sdma";
1306 case IP_VERSION(4, 1, 0):
1307 case IP_VERSION(4, 1, 1):
1308 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1309 return "raven2_sdma";
1310 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1311 return "picasso_sdma";
1312 return "raven_sdma";
1313 case IP_VERSION(4, 1, 2):
1314 if (adev->apu_flags & AMD_APU_IS_RENOIR)
1315 return "renoir_sdma";
1316 return "green_sardine_sdma";
1317 case IP_VERSION(4, 2, 0):
1318 return "vega20_sdma";
1319 case IP_VERSION(4, 2, 2):
1320 return "arcturus_sdma";
1321 case IP_VERSION(4, 4, 0):
1322 return "aldebaran_sdma";
1323 case IP_VERSION(5, 0, 0):
1324 return "navi10_sdma";
1325 case IP_VERSION(5, 0, 1):
1326 return "cyan_skillfish2_sdma";
1327 case IP_VERSION(5, 0, 2):
1328 return "navi14_sdma";
1329 case IP_VERSION(5, 0, 5):
1330 return "navi12_sdma";
1331 case IP_VERSION(5, 2, 0):
1332 return "sienna_cichlid_sdma";
1333 case IP_VERSION(5, 2, 2):
1334 return "navy_flounder_sdma";
1335 case IP_VERSION(5, 2, 4):
1336 return "dimgrey_cavefish_sdma";
1337 case IP_VERSION(5, 2, 5):
1338 return "beige_goby_sdma";
1339 case IP_VERSION(5, 2, 3):
1340 return "yellow_carp_sdma";
1341 case IP_VERSION(5, 2, 1):
1342 return "vangogh_sdma";
1343 }
1344 } else if (block_type == UVD_HWIP) {
1345 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
1346 case IP_VERSION(1, 0, 0):
1347 case IP_VERSION(1, 0, 1):
1348 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1349 return "raven2_vcn";
1350 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1351 return "picasso_vcn";
1352 return "raven_vcn";
1353 case IP_VERSION(2, 5, 0):
1354 return "arcturus_vcn";
1355 case IP_VERSION(2, 2, 0):
1356 if (adev->apu_flags & AMD_APU_IS_RENOIR)
1357 return "renoir_vcn";
1358 return "green_sardine_vcn";
1359 case IP_VERSION(2, 6, 0):
1360 return "aldebaran_vcn";
1361 case IP_VERSION(2, 0, 0):
1362 return "navi10_vcn";
1363 case IP_VERSION(2, 0, 2):
1364 if (adev->asic_type == CHIP_NAVI12)
1365 return "navi12_vcn";
1366 return "navi14_vcn";
1367 case IP_VERSION(3, 0, 0):
1368 case IP_VERSION(3, 0, 64):
1369 case IP_VERSION(3, 0, 192):
1370 if (amdgpu_ip_version(adev, GC_HWIP, 0) ==
1371 IP_VERSION(10, 3, 0))
1372 return "sienna_cichlid_vcn";
1373 return "navy_flounder_vcn";
1374 case IP_VERSION(3, 0, 2):
1375 return "vangogh_vcn";
1376 case IP_VERSION(3, 0, 16):
1377 return "dimgrey_cavefish_vcn";
1378 case IP_VERSION(3, 0, 33):
1379 return "beige_goby_vcn";
1380 case IP_VERSION(3, 1, 1):
1381 return "yellow_carp_vcn";
1382 }
1383 } else if (block_type == GC_HWIP) {
1384 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1385 case IP_VERSION(9, 0, 1):
1386 return "vega10";
1387 case IP_VERSION(9, 2, 1):
1388 return "vega12";
1389 case IP_VERSION(9, 4, 0):
1390 return "vega20";
1391 case IP_VERSION(9, 2, 2):
1392 case IP_VERSION(9, 1, 0):
1393 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1394 return "raven2";
1395 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1396 return "picasso";
1397 return "raven";
1398 case IP_VERSION(9, 4, 1):
1399 return "arcturus";
1400 case IP_VERSION(9, 3, 0):
1401 if (adev->apu_flags & AMD_APU_IS_RENOIR)
1402 return "renoir";
1403 return "green_sardine";
1404 case IP_VERSION(9, 4, 2):
1405 return "aldebaran";
1406 case IP_VERSION(10, 1, 10):
1407 return "navi10";
1408 case IP_VERSION(10, 1, 1):
1409 return "navi14";
1410 case IP_VERSION(10, 1, 2):
1411 return "navi12";
1412 case IP_VERSION(10, 3, 0):
1413 return "sienna_cichlid";
1414 case IP_VERSION(10, 3, 2):
1415 return "navy_flounder";
1416 case IP_VERSION(10, 3, 1):
1417 return "vangogh";
1418 case IP_VERSION(10, 3, 4):
1419 return "dimgrey_cavefish";
1420 case IP_VERSION(10, 3, 5):
1421 return "beige_goby";
1422 case IP_VERSION(10, 3, 3):
1423 return "yellow_carp";
1424 case IP_VERSION(10, 1, 3):
1425 case IP_VERSION(10, 1, 4):
1426 return "cyan_skillfish2";
1427 }
1428 }
1429 return NULL;
1430}
1431
1432bool amdgpu_is_kicker_fw(struct amdgpu_device *adev)
1433{
1434 int i;
1435
1436 for (i = 0; i < ARRAY_SIZE(kicker_device_list); i++) {
1437 if (adev->pdev->device == kicker_device_list[i].device &&
1438 adev->pdev->revision == kicker_device_list[i].revision)
1439 return true;
1440 }
1441
1442 return false;
1443}
1444
1445void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len)
1446{
1447 int maj, min, rev;
1448 char *ip_name;
1449 const char *legacy;
1450 uint32_t version = amdgpu_ip_version(adev, block_type, 0);
1451
1452 legacy = amdgpu_ucode_legacy_naming(adev, block_type);
1453 if (legacy) {
1454 snprintf(ucode_prefix, len, "%s", legacy);
1455 return;
1456 }
1457
1458 switch (block_type) {
1459 case GC_HWIP:
1460 ip_name = "gc";
1461 break;
1462 case SDMA0_HWIP:
1463 ip_name = "sdma";
1464 break;
1465 case MP0_HWIP:
1466 ip_name = "psp";
1467 break;
1468 case MP1_HWIP:
1469 ip_name = "smu";
1470 break;
1471 case UVD_HWIP:
1472 ip_name = "vcn";
1473 break;
1474 case VPE_HWIP:
1475 ip_name = "vpe";
1476 break;
1477 case ISP_HWIP:
1478 ip_name = "isp";
1479 break;
1480 default:
1481 WARN(1, "invalid HWIP %d\n", block_type);
1482 return;
1483 }
1484
1485 maj = IP_VERSION_MAJ(version);
1486 min = IP_VERSION_MIN(version);
1487 rev = IP_VERSION_REV(version);
1488
1489 snprintf(ucode_prefix, len, "%s_%d_%d_%d", ip_name, maj, min, rev);
1490}
1491
1492/*
1493 * amdgpu_ucode_request - Fetch and validate amdgpu microcode
1494 *
1495 * @adev: amdgpu device
1496 * @fw: pointer to load firmware to
1497 * @required: whether the firmware is required
1498 * @fmt: firmware name format string
1499 * @...: variable arguments
1500 *
1501 * This is a helper that will use request_firmware and amdgpu_ucode_validate
1502 * to load and run basic validation on firmware. If the load fails, remap
1503 * the error code to -ENODEV, so that early_init functions will fail to load.
1504 */
1505int amdgpu_ucode_request(struct amdgpu_device *adev, const struct firmware **fw,
1506 enum amdgpu_ucode_required required, const char *fmt, ...)
1507{
1508 char fname[AMDGPU_UCODE_NAME_MAX];
1509 va_list ap;
1510 int r;
1511
1512 va_start(ap, fmt);
1513 r = vsnprintf(fname, sizeof(fname), fmt, ap);
1514 va_end(ap);
1515 if (r == sizeof(fname)) {
1516 dev_warn(adev->dev, "amdgpu firmware name buffer overflow\n");
1517 return -EOVERFLOW;
1518 }
1519
1520 if (required == AMDGPU_UCODE_REQUIRED)
1521 r = request_firmware(fw, fname, adev->dev);
1522 else {
1523 r = firmware_request_nowarn(fw, fname, adev->dev);
1524 if (r)
1525 drm_info(&adev->ddev, "Optional firmware \"%s\" was not found\n", fname);
1526 }
1527 if (r)
1528 return -ENODEV;
1529
1530 r = amdgpu_ucode_validate(*fw);
1531 if (r)
1532 /*
1533 * The amdgpu_ucode_request() should be paired with amdgpu_ucode_release()
1534 * regardless of success/failure, and the amdgpu_ucode_release() takes care of
1535 * firmware release and need to avoid redundant release FW operation here.
1536 */
1537 dev_dbg(adev->dev, "\"%s\" failed to validate\n", fname);
1538
1539 return r;
1540}
1541
1542/*
1543 * amdgpu_ucode_release - Release firmware microcode
1544 *
1545 * @fw: pointer to firmware to release
1546 */
1547void amdgpu_ucode_release(const struct firmware **fw)
1548{
1549 release_firmware(*fw);
1550 *fw = NULL;
1551}