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1/*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/ioctl.h>
24
25/*
26 * MMIO debugfs IOCTL structure
27 */
28struct amdgpu_debugfs_regs2_iocdata {
29 __u32 use_srbm, use_grbm, pg_lock;
30 struct {
31 __u32 se, sh, instance;
32 } grbm;
33 struct {
34 __u32 me, pipe, queue, vmid;
35 } srbm;
36};
37
38struct amdgpu_debugfs_regs2_iocdata_v2 {
39 __u32 use_srbm, use_grbm, pg_lock;
40 struct {
41 __u32 se, sh, instance;
42 } grbm;
43 struct {
44 __u32 me, pipe, queue, vmid;
45 } srbm;
46 u32 xcc_id;
47};
48
49struct amdgpu_debugfs_gprwave_iocdata {
50 u32 gpr_or_wave, se, sh, cu, wave, simd, xcc_id;
51 struct {
52 u32 thread, vpgr_or_sgpr;
53 } gpr;
54};
55
56/*
57 * MMIO debugfs state data (per file* handle)
58 */
59struct amdgpu_debugfs_regs2_data {
60 struct amdgpu_device *adev;
61 struct mutex lock;
62 struct amdgpu_debugfs_regs2_iocdata_v2 id;
63};
64
65struct amdgpu_debugfs_gprwave_data {
66 struct amdgpu_device *adev;
67 struct mutex lock;
68 struct amdgpu_debugfs_gprwave_iocdata id;
69};
70
71enum AMDGPU_DEBUGFS_REGS2_CMDS {
72 AMDGPU_DEBUGFS_REGS2_CMD_SET_STATE = 0,
73 AMDGPU_DEBUGFS_REGS2_CMD_SET_STATE_V2,
74};
75
76enum AMDGPU_DEBUGFS_GPRWAVE_CMDS {
77 AMDGPU_DEBUGFS_GPRWAVE_CMD_SET_STATE = 0,
78};
79
80//reg2 interface
81#define AMDGPU_DEBUGFS_REGS2_IOC_SET_STATE _IOWR(0x20, AMDGPU_DEBUGFS_REGS2_CMD_SET_STATE, struct amdgpu_debugfs_regs2_iocdata)
82#define AMDGPU_DEBUGFS_REGS2_IOC_SET_STATE_V2 _IOWR(0x20, AMDGPU_DEBUGFS_REGS2_CMD_SET_STATE_V2, struct amdgpu_debugfs_regs2_iocdata_v2)
83
84//gprwave interface
85#define AMDGPU_DEBUGFS_GPRWAVE_IOC_SET_STATE _IOWR(0x20, AMDGPU_DEBUGFS_GPRWAVE_CMD_SET_STATE, struct amdgpu_debugfs_gprwave_iocdata)