| 1 | |
| 2 | * Copyright 2014 Advanced Micro Devices, Inc.
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| 3 | *
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a
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| 5 | * copy of this software and associated documentation files (the "Software"),
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| 6 | * to deal in the Software without restriction, including without limitation
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the
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| 9 | * Software is furnished to do so, subject to the following conditions:
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| 10 | *
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| 11 | * The above copyright notice and this permission notice shall be included in
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| 12 | * all copies or substantial portions of the Software.
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| 13 | *
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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| 20 | * OTHER DEALINGS IN THE SOFTWARE.
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| 21 | *
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| 22 |
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| 23 |
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| 24 | #ifndef __AMDGPU_VCE_H__
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| 25 | #define __AMDGPU_VCE_H__
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| 26 |
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| 27 | #define AMDGPU_MAX_VCE_HANDLES 16
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| 28 | #define AMDGPU_VCE_FIRMWARE_OFFSET 256
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| 29 |
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| 30 | #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
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| 31 | #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
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| 32 |
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| 33 | #define AMDGPU_VCE_FW_53_45 ((53 << 24) | (45 << 16))
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| 34 |
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| 35 | struct amdgpu_vce {
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| 36 | struct amdgpu_bo *vcpu_bo;
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| 37 | uint64_t gpu_addr;
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| 38 | void *cpu_addr;
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| 39 | void *saved_bo;
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| 40 | unsigned fw_version;
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| 41 | unsigned fb_version;
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| 42 | atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
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| 43 | struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
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| 44 | uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
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| 45 | struct delayed_work idle_work;
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| 46 | struct mutex idle_mutex;
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| 47 | const struct firmware *fw;
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| 48 | struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
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| 49 | struct amdgpu_irq_src irq;
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| 50 | unsigned harvest_config;
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| 51 | struct drm_sched_entity entity;
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| 52 | uint32_t srbm_soft_reset;
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| 53 | unsigned num_rings;
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| 54 | uint32_t keyselect;
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| 55 | struct drm_mm_node gart_node;
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| 56 | };
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| 57 |
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| 58 | int amdgpu_vce_early_init(struct amdgpu_device *adev);
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| 59 | int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size);
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| 60 | int amdgpu_vce_sw_fini(struct amdgpu_device *adev);
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| 61 | int amdgpu_vce_entity_init(struct amdgpu_device *adev, struct amdgpu_ring *ring);
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| 62 | int amdgpu_vce_suspend(struct amdgpu_device *adev);
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| 63 | int amdgpu_vce_resume(struct amdgpu_device *adev);
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| 64 | void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp);
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| 65 | int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, struct amdgpu_job *job,
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| 66 | struct amdgpu_ib *ib);
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| 67 | int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p,
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| 68 | struct amdgpu_job *job,
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| 69 | struct amdgpu_ib *ib);
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| 70 | void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
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| 71 | struct amdgpu_ib *ib, uint32_t flags);
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| 72 | void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
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| 73 | unsigned flags);
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| 74 | int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring);
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| 75 | int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring, long timeout);
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| 76 | void amdgpu_vce_ring_begin_use(struct amdgpu_ring *ring);
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| 77 | void amdgpu_vce_ring_end_use(struct amdgpu_ring *ring);
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| 78 | unsigned amdgpu_vce_ring_get_emit_ib_size(struct amdgpu_ring *ring);
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| 79 | unsigned amdgpu_vce_ring_get_dma_frame_size(struct amdgpu_ring *ring);
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| 80 | enum amdgpu_ring_priority_level amdgpu_vce_get_ring_prio(int ring);
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| 81 |
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| 82 | #endif
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