| 1 | |
| 2 | * Copyright 2019 Advanced Micro Devices, Inc.
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| 3 | *
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a
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| 5 | * copy of this software and associated documentation files (the "Software"),
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| 6 | * to deal in the Software without restriction, including without limitation
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the
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| 9 | * Software is furnished to do so, subject to the following conditions:
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| 10 | *
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| 11 | * The above copyright notice and this permission notice shall be included in
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| 12 | * all copies or substantial portions of the Software.
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| 13 | *
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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| 20 | * OTHER DEALINGS IN THE SOFTWARE.
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| 21 |
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| 22 |
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| 23 | #include "amdgpu_vm.h"
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| 24 | #include "amdgpu.h"
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| 25 | #include "amdgpu_reset.h"
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| 26 | #include "amdgpu_object.h"
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| 27 | #include "amdgpu_trace.h"
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| 28 |
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| 29 | |
| 30 | * amdgpu_vm_cpu_map_table - make sure new PDs/PTs are kmapped
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| 31 | *
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| 32 | * @table: newly allocated or validated PD/PT
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| 33 |
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| 34 | static int amdgpu_vm_cpu_map_table(struct amdgpu_bo_vm *table)
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| 35 | {
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| 36 | table->bo.flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
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| 37 | return amdgpu_bo_kmap(&table->bo, NULL);
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| 38 | }
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| 39 |
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| 40 | |
| 41 | * amdgpu_vm_cpu_prepare - prepare page table update with the CPU
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| 42 | *
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| 43 | * @p: see amdgpu_vm_update_params definition
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| 44 | * @sync: sync obj with fences to wait on
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| 45 | * @k_job_id: the id for tracing/debug purposes
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| 46 | *
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| 47 | * Returns:
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| 48 | * Negativ errno, 0 for success.
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| 49 |
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| 50 | static int amdgpu_vm_cpu_prepare(struct amdgpu_vm_update_params *p,
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| 51 | struct amdgpu_sync *sync,
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| 52 | u64 k_job_id)
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| 53 | {
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| 54 | if (!sync)
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| 55 | return 0;
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| 56 |
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| 57 | return amdgpu_sync_wait(sync, true);
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| 58 | }
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| 59 |
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| 60 | |
| 61 | * amdgpu_vm_cpu_update - helper to update page tables via CPU
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| 62 | *
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| 63 | * @p: see amdgpu_vm_update_params definition
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| 64 | * @vmbo: PD/PT to update
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| 65 | * @pe: byte offset of the PDE/PTE, relative to start of PDB/PTB
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| 66 | * @addr: dst addr to write into pe
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| 67 | * @count: number of page entries to update
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| 68 | * @incr: increase next addr by incr bytes
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| 69 | * @flags: hw access flags
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| 70 | *
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| 71 | * Write count number of PT/PD entries directly.
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| 72 |
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| 73 | static int amdgpu_vm_cpu_update(struct amdgpu_vm_update_params *p,
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| 74 | struct amdgpu_bo_vm *vmbo, uint64_t pe,
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| 75 | uint64_t addr, unsigned count, uint32_t incr,
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| 76 | uint64_t flags)
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| 77 | {
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| 78 | unsigned int i;
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| 79 | uint64_t value;
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| 80 | long r;
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| 81 |
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| 82 | r = dma_resv_wait_timeout(vmbo->bo.tbo.base.resv, DMA_RESV_USAGE_KERNEL,
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| 83 | true, MAX_SCHEDULE_TIMEOUT);
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| 84 | if (r < 0)
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| 85 | return r;
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| 86 |
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| 87 | pe += (unsigned long)amdgpu_bo_kptr(&vmbo->bo);
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| 88 |
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| 89 | trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags, p->immediate);
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| 90 |
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| 91 | if (!p->pages_addr && p->override_pte)
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| 92 | amdgpu_gmc_override_vm_pte_flags(p->adev, p->vm, addr, &flags);
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| 93 |
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| 94 | for (i = 0; i < count; i++) {
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| 95 | u64 oflags = flags;
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| 96 |
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| 97 | value = p->pages_addr ?
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| 98 | amdgpu_vm_map_gart(p->pages_addr, addr) :
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| 99 | addr;
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| 100 |
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| 101 | if (p->pages_addr && p->override_pte)
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| 102 | amdgpu_gmc_override_vm_pte_flags(p->adev, p->vm, value, &oflags);
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| 103 |
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| 104 | amdgpu_gmc_set_pte_pde(p->adev, (void *)(uintptr_t)pe,
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| 105 | i, value, oflags);
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| 106 | addr += incr;
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| 107 | }
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| 108 | return 0;
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| 109 | }
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| 110 |
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| 111 | |
| 112 | * amdgpu_vm_cpu_commit - commit page table update to the HW
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| 113 | *
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| 114 | * @p: see amdgpu_vm_update_params definition
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| 115 | * @fence: unused
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| 116 | *
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| 117 | * Make sure that the hardware sees the page table updates.
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| 118 |
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| 119 | static int amdgpu_vm_cpu_commit(struct amdgpu_vm_update_params *p,
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| 120 | struct dma_fence **fence)
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| 121 | {
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| 122 | struct amdgpu_device *adev = p->adev;
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| 123 |
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| 124 | if (p->needs_flush)
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| 125 | atomic64_inc(&p->vm->tlb_seq);
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| 126 |
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| 127 | mb();
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| 128 |
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| 129 | if (!down_read_trylock(&adev->reset_domain->sem))
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| 130 | return 0;
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| 131 |
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| 132 | amdgpu_device_flush_hdp(adev, NULL);
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| 133 | up_read(&adev->reset_domain->sem);
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| 134 |
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| 135 | return 0;
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| 136 | }
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| 137 |
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| 138 | const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs = {
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| 139 | .map_table = amdgpu_vm_cpu_map_table,
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| 140 | .prepare = amdgpu_vm_cpu_prepare,
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| 141 | .update = amdgpu_vm_cpu_update,
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| 142 | .commit = amdgpu_vm_cpu_commit
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| 143 | };
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