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1/*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include <linux/firmware.h>
24#include <drm/drm_drv.h>
25
26#include "amdgpu.h"
27#include "amdgpu_ucode.h"
28#include "amdgpu_vpe.h"
29#include "amdgpu_smu.h"
30#include "soc15_common.h"
31#include "vpe_v6_1.h"
32#include "vpe_v2_0.h"
33
34#define AMDGPU_CSA_VPE_SIZE 64
35/* VPE CSA resides in the 4th page of CSA */
36#define AMDGPU_CSA_VPE_OFFSET (4096 * 3)
37
38/* 1 second timeout */
39#define VPE_IDLE_TIMEOUT msecs_to_jiffies(1000)
40
41#define VPE_MAX_DPM_LEVEL 4
42#define FIXED1_8_BITS_PER_FRACTIONAL_PART 8
43#define GET_PRATIO_INTEGER_PART(x) ((x) >> FIXED1_8_BITS_PER_FRACTIONAL_PART)
44
45static void vpe_set_ring_funcs(struct amdgpu_device *adev);
46
47static inline uint16_t div16_u16_rem(uint16_t dividend, uint16_t divisor, uint16_t *remainder)
48{
49 *remainder = dividend % divisor;
50 return dividend / divisor;
51}
52
53static inline uint16_t complete_integer_division_u16(
54 uint16_t dividend,
55 uint16_t divisor,
56 uint16_t *remainder)
57{
58 return div16_u16_rem(dividend, divisor, (uint16_t *)remainder);
59}
60
61static uint16_t vpe_u1_8_from_fraction(uint16_t numerator, uint16_t denominator)
62{
63 u16 arg1_value = numerator;
64 u16 arg2_value = denominator;
65
66 uint16_t remainder;
67
68 /* determine integer part */
69 uint16_t res_value = complete_integer_division_u16(
70 arg1_value, arg2_value, &remainder);
71
72 if (res_value > 127 /* CHAR_MAX */)
73 return 0;
74
75 /* determine fractional part */
76 {
77 unsigned int i = FIXED1_8_BITS_PER_FRACTIONAL_PART;
78
79 do {
80 remainder <<= 1;
81
82 res_value <<= 1;
83
84 if (remainder >= arg2_value) {
85 res_value |= 1;
86 remainder -= arg2_value;
87 }
88 } while (--i != 0);
89 }
90
91 /* round up LSB */
92 {
93 uint16_t summand = (remainder << 1) >= arg2_value;
94
95 if ((res_value + summand) > 32767 /* SHRT_MAX */)
96 return 0;
97
98 res_value += summand;
99 }
100
101 return res_value;
102}
103
104static uint16_t vpe_internal_get_pratio(uint16_t from_frequency, uint16_t to_frequency)
105{
106 uint16_t pratio = vpe_u1_8_from_fraction(from_frequency, to_frequency);
107
108 if (GET_PRATIO_INTEGER_PART(pratio) > 1)
109 pratio = 0;
110
111 return pratio;
112}
113
114/*
115 * VPE has 4 DPM levels from level 0 (lowerest) to 3 (highest),
116 * VPE FW will dynamically decide which level should be used according to current loading.
117 *
118 * Get VPE and SOC clocks from PM, and select the appropriate four clock values,
119 * calculate the ratios of adjusting from one clock to another.
120 * The VPE FW can then request the appropriate frequency from the PMFW.
121 */
122int amdgpu_vpe_configure_dpm(struct amdgpu_vpe *vpe)
123{
124 struct amdgpu_device *adev = vpe->ring.adev;
125 uint32_t dpm_ctl;
126
127 if (adev->pm.dpm_enabled) {
128 struct dpm_clocks clock_table = { 0 };
129 struct dpm_clock *VPEClks;
130 struct dpm_clock *SOCClks;
131 uint32_t idx;
132 uint32_t vpeclk_enalbled_num = 0;
133 uint32_t pratio_vmax_vnorm = 0, pratio_vnorm_vmid = 0, pratio_vmid_vmin = 0;
134 uint16_t pratio_vmin_freq = 0, pratio_vmid_freq = 0, pratio_vnorm_freq = 0, pratio_vmax_freq = 0;
135
136 dpm_ctl = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable));
137 dpm_ctl |= 1; /* DPM enablement */
138 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable), dpm_ctl);
139
140 /* Get VPECLK and SOCCLK */
141 if (amdgpu_dpm_get_dpm_clock_table(adev, &clock_table)) {
142 dev_dbg(adev->dev, "%s: get clock failed!\n", __func__);
143 goto disable_dpm;
144 }
145
146 SOCClks = clock_table.SocClocks;
147 VPEClks = clock_table.VPEClocks;
148
149 /* Comfirm enabled vpe clk num
150 * Enabled VPE clocks are ordered from low to high in VPEClks
151 * The highest valid clock index+1 is the number of VPEClks
152 */
153 for (idx = PP_SMU_NUM_VPECLK_DPM_LEVELS; idx && !vpeclk_enalbled_num; idx--)
154 if (VPEClks[idx-1].Freq)
155 vpeclk_enalbled_num = idx;
156
157 /* vpe dpm only cares 4 levels. */
158 for (idx = 0; idx < VPE_MAX_DPM_LEVEL; idx++) {
159 uint32_t soc_dpm_level;
160 uint32_t min_freq;
161
162 if (idx == 0)
163 soc_dpm_level = 0;
164 else
165 soc_dpm_level = (idx * 2) + 1;
166
167 /* clamp the max level */
168 if (soc_dpm_level > vpeclk_enalbled_num - 1)
169 soc_dpm_level = vpeclk_enalbled_num - 1;
170
171 min_freq = (SOCClks[soc_dpm_level].Freq < VPEClks[soc_dpm_level].Freq) ?
172 SOCClks[soc_dpm_level].Freq : VPEClks[soc_dpm_level].Freq;
173
174 switch (idx) {
175 case 0:
176 pratio_vmin_freq = min_freq;
177 break;
178 case 1:
179 pratio_vmid_freq = min_freq;
180 break;
181 case 2:
182 pratio_vnorm_freq = min_freq;
183 break;
184 case 3:
185 pratio_vmax_freq = min_freq;
186 break;
187 default:
188 break;
189 }
190 }
191
192 if (pratio_vmin_freq && pratio_vmid_freq && pratio_vnorm_freq && pratio_vmax_freq) {
193 uint32_t pratio_ctl;
194
195 pratio_vmax_vnorm = (uint32_t)vpe_internal_get_pratio(pratio_vmax_freq, pratio_vnorm_freq);
196 pratio_vnorm_vmid = (uint32_t)vpe_internal_get_pratio(pratio_vnorm_freq, pratio_vmid_freq);
197 pratio_vmid_vmin = (uint32_t)vpe_internal_get_pratio(pratio_vmid_freq, pratio_vmin_freq);
198
199 pratio_ctl = pratio_vmax_vnorm | (pratio_vnorm_vmid << 9) | (pratio_vmid_vmin << 18);
200 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_pratio), pratio_ctl); /* PRatio */
201 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_request_interval), 24000); /* 1ms, unit=1/24MHz */
202 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_decision_threshold), 1200000); /* 50ms */
203 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_busy_clamp_threshold), 1200000);/* 50ms */
204 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_idle_clamp_threshold), 1200000);/* 50ms */
205 dev_dbg(adev->dev, "%s: configure vpe dpm pratio done!\n", __func__);
206 } else {
207 dev_dbg(adev->dev, "%s: invalid pratio parameters!\n", __func__);
208 goto disable_dpm;
209 }
210 }
211 return 0;
212
213disable_dpm:
214 dpm_ctl = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable));
215 dpm_ctl &= 0xfffffffe; /* Disable DPM */
216 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable), dpm_ctl);
217 dev_dbg(adev->dev, "%s: disable vpe dpm\n", __func__);
218 return -EINVAL;
219}
220
221int amdgpu_vpe_psp_update_sram(struct amdgpu_device *adev)
222{
223 struct amdgpu_firmware_info ucode = {
224 .ucode_id = AMDGPU_UCODE_ID_VPE,
225 .mc_addr = adev->vpe.cmdbuf_gpu_addr,
226 .ucode_size = 8,
227 };
228
229 return psp_execute_ip_fw_load(&adev->psp, &ucode);
230}
231
232int amdgpu_vpe_init_microcode(struct amdgpu_vpe *vpe)
233{
234 struct amdgpu_device *adev = vpe->ring.adev;
235 const struct vpe_firmware_header_v1_0 *vpe_hdr;
236 char fw_prefix[32];
237 int ret;
238
239 amdgpu_ucode_ip_version_decode(adev, VPE_HWIP, fw_prefix, sizeof(fw_prefix));
240 ret = amdgpu_ucode_request(adev, &adev->vpe.fw, AMDGPU_UCODE_REQUIRED,
241 "amdgpu/%s.bin", fw_prefix);
242 if (ret)
243 goto out;
244
245 vpe_hdr = (const struct vpe_firmware_header_v1_0 *)adev->vpe.fw->data;
246 adev->vpe.fw_version = le32_to_cpu(vpe_hdr->header.ucode_version);
247 adev->vpe.feature_version = le32_to_cpu(vpe_hdr->ucode_feature_version);
248
249 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
250 struct amdgpu_firmware_info *info;
251
252 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_VPE_CTX];
253 info->ucode_id = AMDGPU_UCODE_ID_VPE_CTX;
254 info->fw = adev->vpe.fw;
255 adev->firmware.fw_size +=
256 ALIGN(le32_to_cpu(vpe_hdr->ctx_ucode_size_bytes), PAGE_SIZE);
257
258 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_VPE_CTL];
259 info->ucode_id = AMDGPU_UCODE_ID_VPE_CTL;
260 info->fw = adev->vpe.fw;
261 adev->firmware.fw_size +=
262 ALIGN(le32_to_cpu(vpe_hdr->ctl_ucode_size_bytes), PAGE_SIZE);
263 }
264
265 return 0;
266out:
267 dev_err(adev->dev, "fail to initialize vpe microcode\n");
268 release_firmware(adev->vpe.fw);
269 adev->vpe.fw = NULL;
270 return ret;
271}
272
273int amdgpu_vpe_ring_init(struct amdgpu_vpe *vpe)
274{
275 struct amdgpu_device *adev = container_of(vpe, struct amdgpu_device, vpe);
276 struct amdgpu_ring *ring = &vpe->ring;
277 int ret;
278
279 ring->ring_obj = NULL;
280 ring->use_doorbell = true;
281 ring->vm_hub = AMDGPU_MMHUB0(0);
282 ring->doorbell_index = (adev->doorbell_index.vpe_ring << 1);
283 snprintf(ring->name, 4, "vpe");
284
285 ret = amdgpu_ring_init(adev, ring, 1024, &vpe->trap_irq, 0,
286 AMDGPU_RING_PRIO_DEFAULT, NULL);
287 if (ret)
288 return ret;
289
290 return 0;
291}
292
293int amdgpu_vpe_ring_fini(struct amdgpu_vpe *vpe)
294{
295 amdgpu_ring_fini(&vpe->ring);
296
297 return 0;
298}
299
300static int vpe_early_init(struct amdgpu_ip_block *ip_block)
301{
302 struct amdgpu_device *adev = ip_block->adev;
303 struct amdgpu_vpe *vpe = &adev->vpe;
304
305 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) {
306 case IP_VERSION(6, 1, 0):
307 case IP_VERSION(6, 1, 3):
308 vpe_v6_1_set_funcs(vpe);
309 break;
310 case IP_VERSION(6, 1, 1):
311 vpe_v6_1_set_funcs(vpe);
312 vpe->collaborate_mode = true;
313 break;
314 case IP_VERSION(2, 0, 0):
315 case IP_VERSION(2, 2, 0):
316 vpe_v2_0_set_funcs(vpe);
317 break;
318 default:
319 return -EINVAL;
320 }
321
322 vpe_set_ring_funcs(adev);
323 vpe_set_regs(vpe);
324
325 dev_info(adev->dev, "VPE: collaborate mode %s", vpe->collaborate_mode ? "true" : "false");
326
327 return 0;
328}
329
330static bool vpe_need_dpm0_at_power_down(struct amdgpu_device *adev)
331{
332 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) {
333 case IP_VERSION(6, 1, 1):
334 return adev->pm.fw_version < 0x0a640500;
335 default:
336 return false;
337 }
338}
339
340static int vpe_get_dpm_level(struct amdgpu_device *adev)
341{
342 struct amdgpu_vpe *vpe = &adev->vpe;
343
344 if (!adev->pm.dpm_enabled)
345 return 0;
346
347 return RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_request_lv));
348}
349
350static void vpe_idle_work_handler(struct work_struct *work)
351{
352 struct amdgpu_device *adev =
353 container_of(work, struct amdgpu_device, vpe.idle_work.work);
354 unsigned int fences = 0;
355
356 fences += amdgpu_fence_count_emitted(&adev->vpe.ring);
357 if (fences)
358 goto reschedule;
359
360 if (vpe_need_dpm0_at_power_down(adev) && vpe_get_dpm_level(adev) != 0)
361 goto reschedule;
362
363 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_GATE);
364 return;
365
366reschedule:
367 schedule_delayed_work(&adev->vpe.idle_work, VPE_IDLE_TIMEOUT);
368}
369
370static int vpe_common_init(struct amdgpu_vpe *vpe)
371{
372 struct amdgpu_device *adev = container_of(vpe, struct amdgpu_device, vpe);
373 int r;
374
375 r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
376 AMDGPU_GEM_DOMAIN_GTT,
377 &adev->vpe.cmdbuf_obj,
378 &adev->vpe.cmdbuf_gpu_addr,
379 (void **)&adev->vpe.cmdbuf_cpu_addr);
380 if (r) {
381 dev_err(adev->dev, "VPE: failed to allocate cmdbuf bo %d\n", r);
382 return r;
383 }
384
385 vpe->context_started = false;
386 INIT_DELAYED_WORK(&adev->vpe.idle_work, vpe_idle_work_handler);
387
388 return 0;
389}
390
391static int vpe_sw_init(struct amdgpu_ip_block *ip_block)
392{
393 struct amdgpu_device *adev = ip_block->adev;
394 struct amdgpu_vpe *vpe = &adev->vpe;
395 int ret;
396
397 ret = vpe_common_init(vpe);
398 if (ret)
399 goto out;
400
401 ret = vpe_irq_init(vpe);
402 if (ret)
403 goto out;
404
405 ret = vpe_ring_init(vpe);
406 if (ret)
407 goto out;
408
409 ret = vpe_init_microcode(vpe);
410 if (ret)
411 goto out;
412
413 adev->vpe.supported_reset =
414 amdgpu_get_soft_full_reset_mask(&adev->vpe.ring);
415 if (!amdgpu_sriov_vf(adev))
416 adev->vpe.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
417 ret = amdgpu_vpe_sysfs_reset_mask_init(adev);
418 if (ret)
419 goto out;
420out:
421 return ret;
422}
423
424static int vpe_sw_fini(struct amdgpu_ip_block *ip_block)
425{
426 struct amdgpu_device *adev = ip_block->adev;
427 struct amdgpu_vpe *vpe = &adev->vpe;
428
429 release_firmware(vpe->fw);
430 vpe->fw = NULL;
431
432 amdgpu_vpe_sysfs_reset_mask_fini(adev);
433 vpe_ring_fini(vpe);
434
435 amdgpu_bo_free_kernel(&adev->vpe.cmdbuf_obj,
436 &adev->vpe.cmdbuf_gpu_addr,
437 (void **)&adev->vpe.cmdbuf_cpu_addr);
438
439 return 0;
440}
441
442static int vpe_hw_init(struct amdgpu_ip_block *ip_block)
443{
444 struct amdgpu_device *adev = ip_block->adev;
445 struct amdgpu_vpe *vpe = &adev->vpe;
446 int ret;
447
448 /* Power on VPE */
449 ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE,
450 AMD_PG_STATE_UNGATE);
451 if (ret)
452 return ret;
453
454 ret = vpe_load_microcode(vpe);
455 if (ret)
456 return ret;
457
458 ret = vpe_ring_start(vpe);
459 if (ret)
460 return ret;
461
462 return 0;
463}
464
465static int vpe_hw_fini(struct amdgpu_ip_block *ip_block)
466{
467 struct amdgpu_device *adev = ip_block->adev;
468 struct amdgpu_vpe *vpe = &adev->vpe;
469
470 cancel_delayed_work_sync(&adev->vpe.idle_work);
471
472 vpe_ring_stop(vpe);
473
474 /* Power off VPE */
475 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_GATE);
476
477 return 0;
478}
479
480static int vpe_suspend(struct amdgpu_ip_block *ip_block)
481{
482 return vpe_hw_fini(ip_block);
483}
484
485static int vpe_resume(struct amdgpu_ip_block *ip_block)
486{
487 return vpe_hw_init(ip_block);
488}
489
490static void vpe_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
491{
492 int i;
493
494 for (i = 0; i < count; i++)
495 if (i == 0)
496 amdgpu_ring_write(ring, ring->funcs->nop |
497 VPE_CMD_NOP_HEADER_COUNT(count - 1));
498 else
499 amdgpu_ring_write(ring, ring->funcs->nop);
500}
501
502static uint64_t vpe_get_csa_mc_addr(struct amdgpu_ring *ring, uint32_t vmid)
503{
504 struct amdgpu_device *adev = ring->adev;
505 uint32_t index = 0;
506 uint64_t csa_mc_addr;
507
508 if (amdgpu_sriov_vf(adev) || vmid == 0 || !adev->gfx.mcbp)
509 return 0;
510
511 csa_mc_addr = amdgpu_csa_vaddr(adev) + AMDGPU_CSA_VPE_OFFSET +
512 index * AMDGPU_CSA_VPE_SIZE;
513
514 return csa_mc_addr;
515}
516
517static void vpe_ring_emit_pred_exec(struct amdgpu_ring *ring,
518 uint32_t device_select,
519 uint32_t exec_count)
520{
521 if (!ring->adev->vpe.collaborate_mode)
522 return;
523
524 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_PRED_EXE, 0) |
525 (device_select << 16));
526 amdgpu_ring_write(ring, exec_count & 0x1fff);
527}
528
529static void vpe_ring_emit_ib(struct amdgpu_ring *ring,
530 struct amdgpu_job *job,
531 struct amdgpu_ib *ib,
532 uint32_t flags)
533{
534 uint32_t vmid = AMDGPU_JOB_GET_VMID(job);
535 uint64_t csa_mc_addr = vpe_get_csa_mc_addr(ring, vmid);
536
537 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_INDIRECT, 0) |
538 VPE_CMD_INDIRECT_HEADER_VMID(vmid & 0xf));
539
540 /* base must be 32 byte aligned */
541 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0);
542 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
543 amdgpu_ring_write(ring, ib->length_dw);
544 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
545 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
546}
547
548static void vpe_ring_emit_fence(struct amdgpu_ring *ring, uint64_t addr,
549 uint64_t seq, unsigned int flags)
550{
551 int i = 0;
552
553 do {
554 /* write the fence */
555 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_FENCE, 0));
556 /* zero in first two bits */
557 WARN_ON_ONCE(addr & 0x3);
558 amdgpu_ring_write(ring, lower_32_bits(addr));
559 amdgpu_ring_write(ring, upper_32_bits(addr));
560 amdgpu_ring_write(ring, i == 0 ? lower_32_bits(seq) : upper_32_bits(seq));
561 addr += 4;
562 } while ((flags & AMDGPU_FENCE_FLAG_64BIT) && (i++ < 1));
563
564 if (flags & AMDGPU_FENCE_FLAG_INT) {
565 /* generate an interrupt */
566 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_TRAP, 0));
567 amdgpu_ring_write(ring, 0);
568 }
569
570 /* WA: Force sync after TRAP to avoid VPE1 fail to power off */
571 if (ring->adev->vpe.collaborate_mode) {
572 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_COLLAB_SYNC, 0));
573 amdgpu_ring_write(ring, 0xabcd);
574 }
575}
576
577static void vpe_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
578{
579 uint32_t seq = ring->fence_drv.sync_seq;
580 uint64_t addr = ring->fence_drv.gpu_addr;
581
582 vpe_ring_emit_pred_exec(ring, 0, 6);
583
584 /* wait for idle */
585 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_POLL_REGMEM,
586 VPE_POLL_REGMEM_SUBOP_REGMEM) |
587 VPE_CMD_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
588 VPE_CMD_POLL_REGMEM_HEADER_MEM(1));
589 amdgpu_ring_write(ring, addr & 0xfffffffc);
590 amdgpu_ring_write(ring, upper_32_bits(addr));
591 amdgpu_ring_write(ring, seq); /* reference */
592 amdgpu_ring_write(ring, 0xffffffff); /* mask */
593 amdgpu_ring_write(ring, VPE_CMD_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
594 VPE_CMD_POLL_REGMEM_DW5_INTERVAL(4));
595}
596
597static void vpe_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
598{
599 vpe_ring_emit_pred_exec(ring, 0, 3);
600
601 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_REG_WRITE, 0));
602 amdgpu_ring_write(ring, reg << 2);
603 amdgpu_ring_write(ring, val);
604}
605
606static void vpe_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
607 uint32_t val, uint32_t mask)
608{
609 vpe_ring_emit_pred_exec(ring, 0, 6);
610
611 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_POLL_REGMEM,
612 VPE_POLL_REGMEM_SUBOP_REGMEM) |
613 VPE_CMD_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
614 VPE_CMD_POLL_REGMEM_HEADER_MEM(0));
615 amdgpu_ring_write(ring, reg << 2);
616 amdgpu_ring_write(ring, 0);
617 amdgpu_ring_write(ring, val); /* reference */
618 amdgpu_ring_write(ring, mask); /* mask */
619 amdgpu_ring_write(ring, VPE_CMD_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
620 VPE_CMD_POLL_REGMEM_DW5_INTERVAL(10));
621}
622
623static void vpe_ring_emit_vm_flush(struct amdgpu_ring *ring, unsigned int vmid,
624 uint64_t pd_addr)
625{
626 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
627}
628
629static unsigned int vpe_ring_init_cond_exec(struct amdgpu_ring *ring,
630 uint64_t addr)
631{
632 unsigned int ret;
633
634 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_COND_EXE, 0));
635 amdgpu_ring_write(ring, lower_32_bits(addr));
636 amdgpu_ring_write(ring, upper_32_bits(addr));
637 amdgpu_ring_write(ring, 1);
638 ret = ring->wptr & ring->buf_mask;
639 amdgpu_ring_write(ring, 0);
640
641 return ret;
642}
643
644static int vpe_ring_preempt_ib(struct amdgpu_ring *ring)
645{
646 struct amdgpu_device *adev = ring->adev;
647 struct amdgpu_vpe *vpe = &adev->vpe;
648 uint32_t preempt_reg = vpe->regs.queue0_preempt;
649 int i, r = 0;
650
651 /* assert preemption condition */
652 amdgpu_ring_set_preempt_cond_exec(ring, false);
653
654 /* emit the trailing fence */
655 ring->trail_seq += 1;
656 amdgpu_ring_alloc(ring, 10);
657 vpe_ring_emit_fence(ring, ring->trail_fence_gpu_addr, ring->trail_seq, 0);
658 amdgpu_ring_commit(ring);
659
660 /* assert IB preemption */
661 WREG32(vpe_get_reg_offset(vpe, ring->me, preempt_reg), 1);
662
663 /* poll the trailing fence */
664 for (i = 0; i < adev->usec_timeout; i++) {
665 if (ring->trail_seq ==
666 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
667 break;
668 udelay(1);
669 }
670
671 if (i >= adev->usec_timeout) {
672 r = -EINVAL;
673 dev_err(adev->dev, "ring %d failed to be preempted\n", ring->idx);
674 }
675
676 /* deassert IB preemption */
677 WREG32(vpe_get_reg_offset(vpe, ring->me, preempt_reg), 0);
678
679 /* deassert the preemption condition */
680 amdgpu_ring_set_preempt_cond_exec(ring, true);
681
682 return r;
683}
684
685static int vpe_set_clockgating_state(struct amdgpu_ip_block *ip_block,
686 enum amd_clockgating_state state)
687{
688 return 0;
689}
690
691static int vpe_set_powergating_state(struct amdgpu_ip_block *ip_block,
692 enum amd_powergating_state state)
693{
694 struct amdgpu_device *adev = ip_block->adev;
695 struct amdgpu_vpe *vpe = &adev->vpe;
696
697 if (!adev->pm.dpm_enabled)
698 dev_err(adev->dev, "Without PM, cannot support powergating\n");
699
700 dev_dbg(adev->dev, "%s: %s!\n", __func__, (state == AMD_PG_STATE_GATE) ? "GATE":"UNGATE");
701
702 if (state == AMD_PG_STATE_GATE) {
703 amdgpu_dpm_enable_vpe(adev, false);
704 vpe->context_started = false;
705 } else {
706 amdgpu_dpm_enable_vpe(adev, true);
707 }
708
709 return 0;
710}
711
712static uint64_t vpe_ring_get_rptr(struct amdgpu_ring *ring)
713{
714 struct amdgpu_device *adev = ring->adev;
715 struct amdgpu_vpe *vpe = &adev->vpe;
716 uint64_t rptr;
717
718 if (ring->use_doorbell) {
719 rptr = atomic64_read((atomic64_t *)ring->rptr_cpu_addr);
720 dev_dbg(adev->dev, "rptr/doorbell before shift == 0x%016llx\n", rptr);
721 } else {
722 rptr = RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_rptr_hi));
723 rptr = rptr << 32;
724 rptr |= RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_rptr_lo));
725 dev_dbg(adev->dev, "rptr before shift [%i] == 0x%016llx\n", ring->me, rptr);
726 }
727
728 return (rptr >> 2);
729}
730
731static uint64_t vpe_ring_get_wptr(struct amdgpu_ring *ring)
732{
733 struct amdgpu_device *adev = ring->adev;
734 struct amdgpu_vpe *vpe = &adev->vpe;
735 uint64_t wptr;
736
737 if (ring->use_doorbell) {
738 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
739 dev_dbg(adev->dev, "wptr/doorbell before shift == 0x%016llx\n", wptr);
740 } else {
741 wptr = RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_wptr_hi));
742 wptr = wptr << 32;
743 wptr |= RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_wptr_lo));
744 dev_dbg(adev->dev, "wptr before shift [%i] == 0x%016llx\n", ring->me, wptr);
745 }
746
747 return (wptr >> 2);
748}
749
750static void vpe_ring_set_wptr(struct amdgpu_ring *ring)
751{
752 struct amdgpu_device *adev = ring->adev;
753 struct amdgpu_vpe *vpe = &adev->vpe;
754
755 if (ring->use_doorbell) {
756 dev_dbg(adev->dev, "Using doorbell, \
757 wptr_offs == 0x%08x, \
758 lower_32_bits(ring->wptr) << 2 == 0x%08x, \
759 upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
760 ring->wptr_offs,
761 lower_32_bits(ring->wptr << 2),
762 upper_32_bits(ring->wptr << 2));
763 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr << 2);
764 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
765 if (vpe->collaborate_mode)
766 WDOORBELL64(ring->doorbell_index + 4, ring->wptr << 2);
767 } else {
768 int i;
769
770 for (i = 0; i < vpe->num_instances; i++) {
771 dev_dbg(adev->dev, "Not using doorbell, \
772 regVPEC_QUEUE0_RB_WPTR == 0x%08x, \
773 regVPEC_QUEUE0_RB_WPTR_HI == 0x%08x\n",
774 lower_32_bits(ring->wptr << 2),
775 upper_32_bits(ring->wptr << 2));
776 WREG32(vpe_get_reg_offset(vpe, i, vpe->regs.queue0_rb_wptr_lo),
777 lower_32_bits(ring->wptr << 2));
778 WREG32(vpe_get_reg_offset(vpe, i, vpe->regs.queue0_rb_wptr_hi),
779 upper_32_bits(ring->wptr << 2));
780 }
781 }
782}
783
784static int vpe_ring_test_ring(struct amdgpu_ring *ring)
785{
786 struct amdgpu_device *adev = ring->adev;
787 const uint32_t test_pattern = 0xdeadbeef;
788 uint32_t index, i;
789 uint64_t wb_addr;
790 int ret;
791
792 ret = amdgpu_wb_get(adev, &index);
793 if (ret) {
794 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", ret);
795 return ret;
796 }
797
798 adev->wb.wb[index] = 0;
799 wb_addr = adev->wb.gpu_addr + (index * 4);
800
801 ret = amdgpu_ring_alloc(ring, 4);
802 if (ret) {
803 dev_err(adev->dev, "dma failed to lock ring %d (%d).\n", ring->idx, ret);
804 goto out;
805 }
806
807 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_FENCE, 0));
808 amdgpu_ring_write(ring, lower_32_bits(wb_addr));
809 amdgpu_ring_write(ring, upper_32_bits(wb_addr));
810 amdgpu_ring_write(ring, test_pattern);
811 amdgpu_ring_commit(ring);
812
813 for (i = 0; i < adev->usec_timeout; i++) {
814 if (le32_to_cpu(adev->wb.wb[index]) == test_pattern)
815 goto out;
816 udelay(1);
817 }
818
819 ret = -ETIMEDOUT;
820out:
821 amdgpu_wb_free(adev, index);
822
823 return ret;
824}
825
826static int vpe_ring_test_ib(struct amdgpu_ring *ring, long timeout)
827{
828 struct amdgpu_device *adev = ring->adev;
829 const uint32_t test_pattern = 0xdeadbeef;
830 struct amdgpu_ib ib = {};
831 struct dma_fence *f = NULL;
832 uint32_t index;
833 uint64_t wb_addr;
834 int ret;
835
836 ret = amdgpu_wb_get(adev, &index);
837 if (ret) {
838 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", ret);
839 return ret;
840 }
841
842 adev->wb.wb[index] = 0;
843 wb_addr = adev->wb.gpu_addr + (index * 4);
844
845 ret = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
846 if (ret)
847 goto err0;
848
849 ib.ptr[0] = VPE_CMD_HEADER(VPE_CMD_OPCODE_FENCE, 0);
850 ib.ptr[1] = lower_32_bits(wb_addr);
851 ib.ptr[2] = upper_32_bits(wb_addr);
852 ib.ptr[3] = test_pattern;
853 ib.ptr[4] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0);
854 ib.ptr[5] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0);
855 ib.ptr[6] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0);
856 ib.ptr[7] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0);
857 ib.length_dw = 8;
858
859 ret = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
860 if (ret)
861 goto err1;
862
863 ret = dma_fence_wait_timeout(f, false, timeout);
864 if (ret <= 0) {
865 ret = ret ? : -ETIMEDOUT;
866 goto err1;
867 }
868
869 ret = (le32_to_cpu(adev->wb.wb[index]) == test_pattern) ? 0 : -EINVAL;
870
871err1:
872 amdgpu_ib_free(&ib, NULL);
873 dma_fence_put(f);
874err0:
875 amdgpu_wb_free(adev, index);
876
877 return ret;
878}
879
880static void vpe_ring_begin_use(struct amdgpu_ring *ring)
881{
882 struct amdgpu_device *adev = ring->adev;
883 struct amdgpu_vpe *vpe = &adev->vpe;
884
885 cancel_delayed_work_sync(&adev->vpe.idle_work);
886
887 /* Power on VPE and notify VPE of new context */
888 if (!vpe->context_started) {
889 uint32_t context_notify;
890
891 /* Power on VPE */
892 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_UNGATE);
893
894 /* Indicates that a job from a new context has been submitted. */
895 context_notify = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.context_indicator));
896 if ((context_notify & 0x1) == 0)
897 context_notify |= 0x1;
898 else
899 context_notify &= ~(0x1);
900 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.context_indicator), context_notify);
901 vpe->context_started = true;
902 }
903}
904
905static void vpe_ring_end_use(struct amdgpu_ring *ring)
906{
907 struct amdgpu_device *adev = ring->adev;
908
909 schedule_delayed_work(&adev->vpe.idle_work, VPE_IDLE_TIMEOUT);
910}
911
912static int vpe_ring_reset(struct amdgpu_ring *ring,
913 unsigned int vmid,
914 struct amdgpu_fence *timedout_fence)
915{
916 struct amdgpu_device *adev = ring->adev;
917 int r;
918
919 amdgpu_ring_reset_helper_begin(ring, timedout_fence);
920
921 r = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE,
922 AMD_PG_STATE_GATE);
923 if (r)
924 return r;
925 r = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE,
926 AMD_PG_STATE_UNGATE);
927 if (r)
928 return r;
929
930 return amdgpu_ring_reset_helper_end(ring, timedout_fence);
931}
932
933static ssize_t amdgpu_get_vpe_reset_mask(struct device *dev,
934 struct device_attribute *attr,
935 char *buf)
936{
937 struct drm_device *ddev = dev_get_drvdata(dev);
938 struct amdgpu_device *adev = drm_to_adev(ddev);
939
940 if (!adev)
941 return -ENODEV;
942
943 return amdgpu_show_reset_mask(buf, adev->vpe.supported_reset);
944}
945
946static DEVICE_ATTR(vpe_reset_mask, 0444,
947 amdgpu_get_vpe_reset_mask, NULL);
948
949int amdgpu_vpe_sysfs_reset_mask_init(struct amdgpu_device *adev)
950{
951 int r = 0;
952
953 if (adev->vpe.num_instances) {
954 r = device_create_file(adev->dev, &dev_attr_vpe_reset_mask);
955 if (r)
956 return r;
957 }
958
959 return r;
960}
961
962void amdgpu_vpe_sysfs_reset_mask_fini(struct amdgpu_device *adev)
963{
964 if (adev->dev->kobj.sd) {
965 if (adev->vpe.num_instances)
966 device_remove_file(adev->dev, &dev_attr_vpe_reset_mask);
967 }
968}
969
970static const struct amdgpu_ring_funcs vpe_ring_funcs = {
971 .type = AMDGPU_RING_TYPE_VPE,
972 .align_mask = 0xf,
973 .nop = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0),
974 .support_64bit_ptrs = true,
975 .get_rptr = vpe_ring_get_rptr,
976 .get_wptr = vpe_ring_get_wptr,
977 .set_wptr = vpe_ring_set_wptr,
978 .emit_frame_size =
979 5 + /* vpe_ring_init_cond_exec */
980 6 + /* vpe_ring_emit_pipeline_sync */
981 12 + 12 + 12 + /* vpe_ring_emit_fence */
982 /* vpe_ring_emit_vm_flush */
983 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
984 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6,
985 .emit_ib_size = 7 + 6,
986 .emit_ib = vpe_ring_emit_ib,
987 .emit_pipeline_sync = vpe_ring_emit_pipeline_sync,
988 .emit_fence = vpe_ring_emit_fence,
989 .emit_vm_flush = vpe_ring_emit_vm_flush,
990 .emit_wreg = vpe_ring_emit_wreg,
991 .emit_reg_wait = vpe_ring_emit_reg_wait,
992 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
993 .insert_nop = vpe_ring_insert_nop,
994 .pad_ib = amdgpu_ring_generic_pad_ib,
995 .test_ring = vpe_ring_test_ring,
996 .test_ib = vpe_ring_test_ib,
997 .init_cond_exec = vpe_ring_init_cond_exec,
998 .preempt_ib = vpe_ring_preempt_ib,
999 .begin_use = vpe_ring_begin_use,
1000 .end_use = vpe_ring_end_use,
1001 .reset = vpe_ring_reset,
1002};
1003
1004static void vpe_set_ring_funcs(struct amdgpu_device *adev)
1005{
1006 adev->vpe.ring.funcs = &vpe_ring_funcs;
1007}
1008
1009const struct amd_ip_funcs vpe_ip_funcs = {
1010 .name = "vpe_v6_1",
1011 .early_init = vpe_early_init,
1012 .sw_init = vpe_sw_init,
1013 .sw_fini = vpe_sw_fini,
1014 .hw_init = vpe_hw_init,
1015 .hw_fini = vpe_hw_fini,
1016 .suspend = vpe_suspend,
1017 .resume = vpe_resume,
1018 .set_clockgating_state = vpe_set_clockgating_state,
1019 .set_powergating_state = vpe_set_powergating_state,
1020};
1021
1022const struct amd_ip_funcs vpe2_ip_funcs = {
1023 .name = "vpe_v2_0",
1024 .early_init = vpe_early_init,
1025 .sw_init = vpe_sw_init,
1026 .sw_fini = vpe_sw_fini,
1027 .hw_init = vpe_hw_init,
1028 .hw_fini = vpe_hw_fini,
1029 .suspend = vpe_suspend,
1030 .resume = vpe_resume,
1031 .set_clockgating_state = vpe_set_clockgating_state,
1032 .set_powergating_state = vpe_set_powergating_state,
1033};
1034
1035const struct amdgpu_ip_block_version vpe_v6_1_ip_block = {
1036 .type = AMD_IP_BLOCK_TYPE_VPE,
1037 .major = 6,
1038 .minor = 1,
1039 .rev = 0,
1040 .funcs = &vpe_ip_funcs,
1041};
1042
1043const struct amdgpu_ip_block_version vpe_v2_0_ip_block = {
1044 .type = AMD_IP_BLOCK_TYPE_VPE,
1045 .major = 2,
1046 .minor = 0,
1047 .rev = 0,
1048 .funcs = &vpe2_ip_funcs,
1049};