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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright 2024 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24#include <drm/drm_drv.h>
25#include "amdgpu.h"
26#include "amdgpu_gfx.h"
27#include "mes_userqueue.h"
28#include "amdgpu_userq_fence.h"
29#include "amdgpu_trace.h"
30
31#define AMDGPU_USERQ_PROC_CTX_SZ PAGE_SIZE
32#define AMDGPU_USERQ_GANG_CTX_SZ PAGE_SIZE
33
34static int
35mes_userq_create_wptr_mapping(struct amdgpu_device *adev,
36 struct amdgpu_userq_mgr *uq_mgr,
37 struct amdgpu_usermode_queue *queue,
38 uint64_t wptr)
39{
40 struct amdgpu_bo_va_mapping *wptr_mapping;
41 struct amdgpu_userq_obj *wptr_obj = &queue->wptr_obj;
42 struct amdgpu_bo *obj;
43 struct amdgpu_vm *vm = queue->vm;
44 struct drm_exec exec;
45 int ret;
46
47 wptr &= AMDGPU_GMC_HOLE_MASK;
48
49 drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 2);
50 drm_exec_until_all_locked(&exec) {
51 ret = amdgpu_vm_lock_pd(vm, &exec, 1);
52 drm_exec_retry_on_contention(&exec);
53 if (unlikely(ret))
54 goto fail_lock;
55
56 wptr_mapping = amdgpu_vm_bo_lookup_mapping(vm, wptr >> PAGE_SHIFT);
57 if (!wptr_mapping) {
58 ret = -EINVAL;
59 goto fail_lock;
60 }
61
62 obj = wptr_mapping->bo_va->base.bo;
63 ret = drm_exec_lock_obj(&exec, &obj->tbo.base);
64 drm_exec_retry_on_contention(&exec);
65 if (unlikely(ret))
66 goto fail_lock;
67 }
68
69 wptr_obj->obj = amdgpu_bo_ref(wptr_mapping->bo_va->base.bo);
70 if (wptr_obj->obj->tbo.base.size > PAGE_SIZE) {
71 ret = -EINVAL;
72 goto fail_map;
73 }
74 /* Keep WPTR BO under eviction-fence control instead of pinning. */
75 ret = amdgpu_evf_mgr_attach_fence(&uq_mgr_to_fpriv(uq_mgr)->evf_mgr, wptr_obj->obj);
76 if (ret) {
77 DRM_ERROR("Failed to attach eviction fence to wptr bo. ret %d\n", ret);
78 goto fail_map;
79 }
80
81 ret = amdgpu_ttm_alloc_gart(&wptr_obj->obj->tbo);
82 if (ret) {
83 DRM_ERROR("Failed to bind wptr bo to GART. ret %d\n", ret);
84 goto fail_map;
85 }
86
87 queue->wptr_obj.gpu_addr = amdgpu_bo_gpu_offset(wptr_obj->obj);
88
89 drm_exec_fini(&exec);
90 return 0;
91fail_map:
92 amdgpu_bo_unref(&wptr_obj->obj);
93fail_lock:
94 drm_exec_fini(&exec);
95 return ret;
96
97}
98
99static int convert_to_mes_priority(int priority)
100{
101 switch (priority) {
102 case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_LOW:
103 default:
104 return AMDGPU_MES_PRIORITY_LEVEL_NORMAL;
105 case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_LOW:
106 return AMDGPU_MES_PRIORITY_LEVEL_LOW;
107 case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_HIGH:
108 return AMDGPU_MES_PRIORITY_LEVEL_MEDIUM;
109 case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_HIGH:
110 return AMDGPU_MES_PRIORITY_LEVEL_HIGH;
111 }
112}
113
114static int mes_userq_map(struct amdgpu_usermode_queue *queue)
115{
116 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr;
117 struct amdgpu_device *adev = uq_mgr->adev;
118 struct amdgpu_userq_obj *ctx = &queue->fw_obj;
119 struct amdgpu_mqd_prop *userq_props = queue->userq_prop;
120 struct mes_add_queue_input queue_input;
121 struct amdgpu_mes *mes = &adev->mes;
122 int r;
123
124 memset(&queue_input, 0x0, sizeof(struct mes_add_queue_input));
125
126 queue_input.process_va_start = 0;
127 queue_input.process_va_end = adev->vm_manager.max_pfn - 1;
128
129 /* set process quantum to 10 ms and gang quantum to 1 ms as default */
130 queue_input.process_quantum = 100000;
131 queue_input.gang_quantum = 10000;
132 queue_input.paging = false;
133
134 queue_input.process_context_addr = uq_mgr->proc_ctx_obj.gpu_addr;
135 queue_input.gang_context_addr = ctx->gpu_addr;
136 queue_input.inprocess_gang_priority = AMDGPU_MES_PRIORITY_LEVEL_NORMAL;
137 queue_input.gang_global_priority_level = convert_to_mes_priority(queue->priority);
138
139 queue_input.process_id = queue->vm->pasid;
140 queue_input.queue_type = queue->queue_type;
141 queue_input.mqd_addr = queue->mqd.gpu_addr;
142 queue_input.wptr_addr = userq_props->wptr_gpu_addr;
143 queue_input.queue_size = userq_props->queue_size >> 2;
144 queue_input.doorbell_offset = userq_props->doorbell_index;
145 queue_input.page_table_base_addr = amdgpu_gmc_pd_addr(queue->vm->root.bo);
146 queue_input.wptr_mc_addr = queue->wptr_obj.gpu_addr;
147
148 if (mes->use_rs64mem) {
149 if (!uq_mgr->proc_ctx_allocated) {
150 r = amdgpu_mes_alloc_proc_ctx_index(mes, &uq_mgr->proc_ctx_array_index);
151 if (r) {
152 DRM_ERROR("Failed to allocate userq process index err:%d\n", r);
153 return r;
154 }
155 uq_mgr->proc_ctx_allocated = true;
156 }
157
158 r = amdgpu_mes_alloc_gang_ctx_index(mes, &queue->gang_ctx_array_index);
159 if (r) {
160 DRM_ERROR("Failed to allocate userq gang index err:%d\n", r);
161 return r;
162 }
163 queue_input.process_context_array_index = uq_mgr->proc_ctx_array_index;
164 queue_input.gang_context_array_index = queue->gang_ctx_array_index;
165 }
166 amdgpu_mes_lock(&adev->mes);
167 r = adev->mes.funcs->add_hw_queue(&adev->mes, &queue_input);
168 amdgpu_mes_unlock(&adev->mes);
169 if (r) {
170 DRM_ERROR("Failed to map queue in HW, err (%d)\n", r);
171 return r;
172 }
173
174 DRM_DEBUG_DRIVER("Queue (doorbell:%d) mapped successfully\n", userq_props->doorbell_index);
175 return 0;
176}
177
178static int mes_userq_unmap(struct amdgpu_usermode_queue *queue)
179{
180 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr;
181 struct amdgpu_device *adev = uq_mgr->adev;
182 struct mes_remove_queue_input queue_input;
183 struct amdgpu_userq_obj *ctx = &queue->fw_obj;
184 struct amdgpu_mes *mes = &adev->mes;
185 int r;
186
187 memset(&queue_input, 0x0, sizeof(struct mes_remove_queue_input));
188 queue_input.gang_context_array_index = queue->gang_ctx_array_index;
189 queue_input.doorbell_offset = queue->doorbell_index;
190 queue_input.gang_context_addr = ctx->gpu_addr;
191 queue_input.queue_type = queue->queue_type;
192
193 amdgpu_mes_lock(&adev->mes);
194 r = adev->mes.funcs->remove_hw_queue(&adev->mes, &queue_input);
195 amdgpu_mes_unlock(&adev->mes);
196 if (mes->use_rs64mem)
197 amdgpu_mes_free_gang_ctx_index(mes, queue->gang_ctx_array_index);
198 if (r)
199 DRM_ERROR("Failed to unmap queue in HW, err (%d)\n", r);
200 return r;
201}
202
203int mes_userq_reset(struct amdgpu_usermode_queue *queue)
204{
205 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr;
206 struct amdgpu_device *adev = uq_mgr->adev;
207 struct mes_reset_queue_input queue_input;
208 int r;
209
210 /* XXX: add a FW version check for SDMA per queue reset */
211 memset(&queue_input, 0x0, sizeof(struct mes_reset_queue_input));
212 queue_input.doorbell_offset = queue->doorbell_index;
213 queue_input.queue_type = queue->queue_type;
214
215 amdgpu_mes_lock(&adev->mes);
216 r = adev->mes.funcs->reset_hw_queue(&adev->mes, &queue_input);
217 amdgpu_mes_unlock(&adev->mes);
218 if (r)
219 return r;
220
221 /* mes_userq_unmap() does not update queue->state; mark it UNMAPPED so the
222 * destroy path does not issue a second REMOVE_QUEUE for the removed queue.
223 */
224 r = mes_userq_unmap(queue);
225 if (!r) {
226 trace_amdgpu_userq_state_changed(queue, AMDGPU_USERQ_STATE_UNMAPPED);
227 queue->state = AMDGPU_USERQ_STATE_UNMAPPED;
228 }
229 return r;
230}
231
232int mes_userq_reset_queue(struct amdgpu_device *adev,
233 struct amdgpu_usermode_queue *guilty_uq,
234 int queue_type,
235 unsigned int pipe,
236 unsigned int queue,
237 unsigned int db)
238{
239 struct amdgpu_usermode_queue *uq;
240 bool use_mmio = adev->gfx.mec.use_mmio_for_reset;
241 unsigned long uq_id;
242 int r;
243
244 xa_for_each(&adev->userq_doorbell_xa, uq_id, uq) {
245 if (uq->queue_type == queue_type) {
246 if (uq == guilty_uq)
247 continue;
248 if (uq->doorbell_index == db) {
249 uq->state = AMDGPU_USERQ_STATE_HUNG;
250 if (use_mmio)
251 r = amdgpu_mes_reset_queue_mmio(adev, queue_type, 0, 1, pipe, queue, 0);
252 else
253 r = amdgpu_mes_reset_user_queue(adev, queue_type, db, 0);
254 if (r)
255 return r;
256 r = mes_userq_unmap(uq);
257 if (r)
258 return r;
259 amdgpu_userq_fence_driver_force_completion(uq);
260 break;
261 }
262 }
263 }
264 return 0;
265}
266
267static int mes_userq_create_ctx_space(struct amdgpu_userq_mgr *uq_mgr,
268 struct amdgpu_usermode_queue *queue,
269 struct drm_amdgpu_userq_in *mqd_user)
270{
271 struct amdgpu_userq_obj *ctx = &queue->fw_obj;
272 int r, size;
273
274 /* The FW expects at least one page space allocated for gang ctx. */
275 size = AMDGPU_USERQ_GANG_CTX_SZ;
276 r = amdgpu_bo_create_kernel(uq_mgr->adev, size, 0,
277 AMDGPU_GEM_DOMAIN_GTT,
278 &ctx->obj, &ctx->gpu_addr,
279 &ctx->cpu_ptr);
280 if (r) {
281 DRM_ERROR("Failed to allocate ctx space bo for userqueue, err:%d\n", r);
282 return r;
283 }
284
285 memset(ctx->cpu_ptr, 0, size);
286 return 0;
287}
288
289static int mes_userq_create_proc_ctx_space(struct amdgpu_userq_mgr *uq_mgr)
290{
291 int r = 0;
292
293 mutex_lock(&uq_mgr->proc_ctx_lock);
294 /* This check is a necessary because amdgpu_bo_create_kernel()
295 * calls helpers like amdgpu_bo_pin() and memset() unconditionally
296 */
297 if (!uq_mgr->proc_ctx_obj.obj) {
298 r = amdgpu_bo_create_kernel(uq_mgr->adev, AMDGPU_USERQ_PROC_CTX_SZ,
299 0, AMDGPU_GEM_DOMAIN_GTT,
300 &uq_mgr->proc_ctx_obj.obj,
301 &uq_mgr->proc_ctx_obj.gpu_addr,
302 &uq_mgr->proc_ctx_obj.cpu_ptr);
303
304 if (!r)
305 memset(uq_mgr->proc_ctx_obj.cpu_ptr, 0, AMDGPU_USERQ_PROC_CTX_SZ);
306 }
307
308 mutex_unlock(&uq_mgr->proc_ctx_lock);
309
310 return r;
311}
312
313static int mes_userq_mqd_create(struct amdgpu_usermode_queue *queue,
314 struct drm_amdgpu_userq_in *args_in)
315{
316 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr;
317 struct amdgpu_device *adev = uq_mgr->adev;
318 struct amdgpu_mqd *mqd_hw_default = &adev->mqds[queue->queue_type];
319 struct drm_amdgpu_userq_in *mqd_user = args_in;
320 struct amdgpu_mqd_prop *userq_props;
321 int r;
322
323 /* Structure to initialize MQD for userqueue using generic MQD init function */
324 userq_props = kzalloc_obj(struct amdgpu_mqd_prop);
325 if (!userq_props) {
326 DRM_ERROR("Failed to allocate memory for userq_props\n");
327 return -ENOMEM;
328 }
329
330 r = amdgpu_bo_create_kernel(adev,
331 AMDGPU_MQD_SIZE_ALIGN(mqd_hw_default->mqd_size),
332 0, AMDGPU_GEM_DOMAIN_GTT,
333 &queue->mqd.obj, &queue->mqd.gpu_addr,
334 &queue->mqd.cpu_ptr);
335 if (r) {
336 DRM_ERROR("Failed to create MQD object for userqueue\n");
337 goto free_props;
338 }
339
340 memset(queue->mqd.cpu_ptr, 0,
341 AMDGPU_MQD_SIZE_ALIGN(mqd_hw_default->mqd_size));
342
343 /* Initialize the MQD BO with user given values */
344 userq_props->wptr_gpu_addr = mqd_user->wptr_va;
345 userq_props->rptr_gpu_addr = mqd_user->rptr_va;
346 userq_props->queue_size = mqd_user->queue_size;
347 userq_props->hqd_base_gpu_addr = mqd_user->queue_va;
348 userq_props->mqd_gpu_addr = queue->mqd.gpu_addr;
349 userq_props->use_doorbell = true;
350 userq_props->doorbell_index = queue->doorbell_index;
351 userq_props->fence_address = queue->fence_drv->gpu_addr;
352
353 if (queue->queue_type == AMDGPU_HW_IP_COMPUTE) {
354 struct drm_amdgpu_userq_mqd_compute_gfx11 *compute_mqd;
355
356 if (mqd_user->mqd_size != sizeof(*compute_mqd)) {
357 DRM_ERROR("Invalid compute IP MQD size\n");
358 r = -EINVAL;
359 goto free_mqd;
360 }
361
362 compute_mqd = memdup_user(u64_to_user_ptr(mqd_user->mqd), mqd_user->mqd_size);
363 if (IS_ERR(compute_mqd)) {
364 r = PTR_ERR(compute_mqd);
365 goto free_mqd;
366 }
367
368 r = amdgpu_bo_reserve(queue->vm->root.bo, false);
369 if (r) {
370 kfree(compute_mqd);
371 goto free_mqd;
372 }
373 r = amdgpu_userq_input_va_validate(adev, queue,
374 compute_mqd->eop_va, 2048,
375 &queue->userq_vas.va.eop);
376 amdgpu_bo_unreserve(queue->vm->root.bo);
377 if (r) {
378 kfree(compute_mqd);
379 goto free_mqd;
380 }
381
382 userq_props->eop_gpu_addr = compute_mqd->eop_va;
383 userq_props->hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_NORMAL;
384 userq_props->hqd_queue_priority = AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM;
385 userq_props->hqd_active = false;
386 userq_props->tmz_queue =
387 mqd_user->flags & AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE;
388 kfree(compute_mqd);
389 } else if (queue->queue_type == AMDGPU_HW_IP_GFX) {
390 struct drm_amdgpu_userq_mqd_gfx11 *mqd_gfx_v11;
391 struct amdgpu_gfx_shadow_info shadow_info;
392
393 if (adev->gfx.funcs->get_gfx_shadow_info) {
394 adev->gfx.funcs->get_gfx_shadow_info(adev, &shadow_info, true);
395 } else {
396 r = -EINVAL;
397 goto free_mqd;
398 }
399
400 if (mqd_user->mqd_size != sizeof(*mqd_gfx_v11) || !mqd_user->mqd) {
401 DRM_ERROR("Invalid GFX MQD\n");
402 r = -EINVAL;
403 goto free_mqd;
404 }
405
406 mqd_gfx_v11 = memdup_user(u64_to_user_ptr(mqd_user->mqd), mqd_user->mqd_size);
407 if (IS_ERR(mqd_gfx_v11)) {
408 r = PTR_ERR(mqd_gfx_v11);
409 goto free_mqd;
410 }
411
412 userq_props->shadow_addr = mqd_gfx_v11->shadow_va;
413 userq_props->csa_addr = mqd_gfx_v11->csa_va;
414 userq_props->tmz_queue =
415 mqd_user->flags & AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE;
416
417 r = amdgpu_bo_reserve(queue->vm->root.bo, false);
418 if (r) {
419 kfree(mqd_gfx_v11);
420 goto free_mqd;
421 }
422 r = amdgpu_userq_input_va_validate(adev, queue, mqd_gfx_v11->shadow_va,
423 shadow_info.shadow_size,
424 &queue->userq_vas.va.shadow);
425 if (r) {
426 amdgpu_bo_unreserve(queue->vm->root.bo);
427 kfree(mqd_gfx_v11);
428 goto free_mqd;
429 }
430
431 r = amdgpu_userq_input_va_validate(adev, queue, mqd_gfx_v11->csa_va,
432 shadow_info.csa_size,
433 &queue->userq_vas.va.csa);
434 amdgpu_bo_unreserve(queue->vm->root.bo);
435 if (r) {
436 kfree(mqd_gfx_v11);
437 goto free_mqd;
438 }
439
440 kfree(mqd_gfx_v11);
441 } else if (queue->queue_type == AMDGPU_HW_IP_DMA) {
442 struct drm_amdgpu_userq_mqd_sdma_gfx11 *mqd_sdma_v11;
443
444 if (mqd_user->mqd_size != sizeof(*mqd_sdma_v11) || !mqd_user->mqd) {
445 DRM_ERROR("Invalid SDMA MQD\n");
446 r = -EINVAL;
447 goto free_mqd;
448 }
449
450 mqd_sdma_v11 = memdup_user(u64_to_user_ptr(mqd_user->mqd), mqd_user->mqd_size);
451 if (IS_ERR(mqd_sdma_v11)) {
452 r = PTR_ERR(mqd_sdma_v11);
453 goto free_mqd;
454 }
455
456 r = amdgpu_bo_reserve(queue->vm->root.bo, false);
457 if (r) {
458 kfree(mqd_sdma_v11);
459 goto free_mqd;
460 }
461 r = amdgpu_userq_input_va_validate(adev, queue, mqd_sdma_v11->csa_va,
462 32,
463 &queue->userq_vas.va.csa);
464 amdgpu_bo_unreserve(queue->vm->root.bo);
465 if (r) {
466 kfree(mqd_sdma_v11);
467 goto free_mqd;
468 }
469
470 userq_props->csa_addr = mqd_sdma_v11->csa_va;
471 kfree(mqd_sdma_v11);
472 }
473
474 queue->userq_prop = userq_props;
475
476 r = mqd_hw_default->init_mqd(adev, (void *)queue->mqd.cpu_ptr, userq_props);
477 if (r) {
478 DRM_ERROR("Failed to initialize MQD for userqueue\n");
479 goto free_mqd;
480 }
481
482 /* Create per-process MES process context BO */
483 r = mes_userq_create_proc_ctx_space(uq_mgr);
484 if (r) {
485 DRM_ERROR("Failed to allocate MES process context space bo, error: %d\n", r);
486 goto free_mqd;
487 }
488
489 /* Create BO of a gang for FW operations */
490 r = mes_userq_create_ctx_space(uq_mgr, queue, mqd_user);
491 if (r) {
492 DRM_ERROR("Failed to allocate BO for userqueue (%d)", r);
493 goto free_mqd;
494 }
495
496 /* FW expects WPTR BOs to be mapped into GART */
497 r = mes_userq_create_wptr_mapping(adev, uq_mgr, queue, userq_props->wptr_gpu_addr);
498 if (r) {
499 DRM_ERROR("Failed to create WPTR mapping\n");
500 goto free_ctx;
501 }
502
503 return 0;
504
505free_ctx:
506 amdgpu_bo_free_kernel(&queue->fw_obj.obj, &queue->fw_obj.gpu_addr,
507 &queue->fw_obj.cpu_ptr);
508
509free_mqd:
510 amdgpu_bo_free_kernel(&queue->mqd.obj, &queue->mqd.gpu_addr,
511 &queue->mqd.cpu_ptr);
512
513free_props:
514 kfree(userq_props);
515
516 return r;
517}
518
519static void mes_userq_mqd_destroy(struct amdgpu_usermode_queue *queue)
520{
521
522 amdgpu_bo_free_kernel(&queue->fw_obj.obj, &queue->fw_obj.gpu_addr,
523 &queue->fw_obj.cpu_ptr);
524 kfree(queue->userq_prop);
525 amdgpu_bo_free_kernel(&queue->mqd.obj, &queue->mqd.gpu_addr,
526 &queue->mqd.cpu_ptr);
527
528 amdgpu_bo_unref(&queue->wptr_obj.obj);
529}
530
531static int mes_userq_preempt(struct amdgpu_usermode_queue *queue)
532{
533 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr;
534 struct amdgpu_device *adev = uq_mgr->adev;
535 struct mes_suspend_gang_input queue_input;
536 struct amdgpu_userq_obj *ctx = &queue->fw_obj;
537 signed long timeout = 2100000; /* 2100 ms */
538 u64 fence_gpu_addr;
539 u32 fence_offset;
540 u64 *fence_ptr;
541 int i, r;
542
543 if (queue->state != AMDGPU_USERQ_STATE_MAPPED)
544 return 0;
545 r = amdgpu_wb_get(adev, &fence_offset);
546 if (r)
547 return r;
548
549 fence_gpu_addr = adev->wb.gpu_addr + (fence_offset * 4);
550 fence_ptr = (u64 *)&adev->wb.wb[fence_offset];
551 *fence_ptr = 0;
552
553 memset(&queue_input, 0x0, sizeof(struct mes_suspend_gang_input));
554 queue_input.gang_context_addr = ctx->gpu_addr;
555 queue_input.suspend_fence_addr = fence_gpu_addr;
556 queue_input.suspend_fence_value = 1;
557 amdgpu_mes_lock(&adev->mes);
558 r = adev->mes.funcs->suspend_gang(&adev->mes, &queue_input);
559 amdgpu_mes_unlock(&adev->mes);
560 if (r) {
561 DRM_ERROR("Failed to suspend gang: %d\n", r);
562 goto out;
563 }
564
565 for (i = 0; i < timeout; i++) {
566 if (*fence_ptr == 1)
567 goto out;
568 udelay(1);
569 }
570 r = -ETIMEDOUT;
571
572out:
573 amdgpu_wb_free(adev, fence_offset);
574 return r;
575}
576
577static int mes_userq_restore(struct amdgpu_usermode_queue *queue)
578{
579 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr;
580 struct amdgpu_device *adev = uq_mgr->adev;
581 struct mes_resume_gang_input queue_input;
582 struct amdgpu_userq_obj *ctx = &queue->fw_obj;
583 int r;
584
585 if (queue->state == AMDGPU_USERQ_STATE_HUNG)
586 return -EINVAL;
587 if (queue->state != AMDGPU_USERQ_STATE_PREEMPTED)
588 return 0;
589
590 memset(&queue_input, 0x0, sizeof(struct mes_resume_gang_input));
591 queue_input.gang_context_addr = ctx->gpu_addr;
592
593 amdgpu_mes_lock(&adev->mes);
594 r = adev->mes.funcs->resume_gang(&adev->mes, &queue_input);
595 amdgpu_mes_unlock(&adev->mes);
596 if (r)
597 dev_err(adev->dev, "Failed to resume queue, err (%d)\n", r);
598 return r;
599}
600
601const struct amdgpu_userq_funcs userq_mes_funcs = {
602 .mqd_create = mes_userq_mqd_create,
603 .mqd_destroy = mes_userq_mqd_destroy,
604 .unmap = mes_userq_unmap,
605 .map = mes_userq_map,
606 .preempt = mes_userq_preempt,
607 .restore = mes_userq_restore,
608 .reset = mes_userq_reset,
609};