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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "amdgpu.h"
25#include "nbio/nbio_2_3_offset.h"
26#include "nbio/nbio_2_3_sh_mask.h"
27#include "gc/gc_10_1_0_offset.h"
28#include "gc/gc_10_1_0_sh_mask.h"
29#include "soc15.h"
30#include "navi10_ih.h"
31#include "soc15_common.h"
32#include "mxgpu_nv.h"
33
34#include "amdgpu_reset.h"
35
36static void xgpu_nv_mailbox_send_ack(struct amdgpu_device *adev)
37{
38 WREG8(NV_MAIBOX_CONTROL_RCV_OFFSET_BYTE, 2);
39}
40
41static void xgpu_nv_mailbox_set_valid(struct amdgpu_device *adev, bool val)
42{
43 WREG8(NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE, val ? 1 : 0);
44}
45
46/*
47 * this peek_msg could *only* be called in IRQ routine becuase in IRQ routine
48 * RCV_MSG_VALID filed of BIF_BX_PF_MAILBOX_CONTROL must already be set to 1
49 * by host.
50 *
51 * if called no in IRQ routine, this peek_msg cannot guaranteed to return the
52 * correct value since it doesn't return the RCV_DW0 under the case that
53 * RCV_MSG_VALID is set by host.
54 */
55static enum idh_event xgpu_nv_mailbox_peek_msg(struct amdgpu_device *adev)
56{
57 return RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0);
58}
59
60
61static int xgpu_nv_mailbox_rcv_msg(struct amdgpu_device *adev,
62 enum idh_event event)
63{
64 int r = 0;
65 u32 reg;
66
67 reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0);
68 if (reg == IDH_FAIL)
69 r = -EINVAL;
70 if (reg == IDH_UNRECOV_ERR_NOTIFICATION)
71 r = -ENODEV;
72 else if (reg != event)
73 return -ENOENT;
74
75 xgpu_nv_mailbox_send_ack(adev);
76
77 return r;
78}
79
80static uint8_t xgpu_nv_peek_ack(struct amdgpu_device *adev)
81{
82 return RREG8(NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE) & 2;
83}
84
85static int xgpu_nv_poll_ack(struct amdgpu_device *adev)
86{
87 int timeout = NV_MAILBOX_POLL_ACK_TIMEDOUT;
88 u8 reg;
89
90 do {
91 reg = RREG8(NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE);
92 if (reg & 2)
93 return 0;
94
95 mdelay(5);
96 timeout -= 5;
97 } while (timeout > 1);
98
99 dev_err(adev->dev,
100 "Doesn't get TRN_MSG_ACK from pf in %d msec\n",
101 NV_MAILBOX_POLL_ACK_TIMEDOUT);
102
103 return -ETIME;
104}
105
106static int xgpu_nv_poll_msg(struct amdgpu_device *adev, enum idh_event event)
107{
108 int r;
109 uint64_t timeout, now;
110 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
111
112 now = (uint64_t)ktime_to_ms(ktime_get());
113 timeout = now + NV_MAILBOX_POLL_MSG_TIMEDOUT;
114
115 do {
116 r = xgpu_nv_mailbox_rcv_msg(adev, event);
117 if (!r) {
118 dev_dbg(adev->dev, "rcv_msg 0x%x after %llu ms\n",
119 event, NV_MAILBOX_POLL_MSG_TIMEDOUT - timeout + now);
120 return 0;
121 } else if (r == -ENODEV) {
122 if (!amdgpu_ras_is_rma(adev)) {
123 ras->is_rma = true;
124 dev_err(adev->dev, "VF is in an unrecoverable state. "
125 "Runtime Services are halted.\n");
126 }
127 return r;
128 }
129
130 msleep(10);
131 now = (uint64_t)ktime_to_ms(ktime_get());
132 } while (timeout > now);
133
134 dev_dbg(adev->dev, "nv_poll_msg timed out\n");
135
136 return -ETIME;
137}
138
139static void xgpu_nv_mailbox_trans_msg (struct amdgpu_device *adev,
140 enum idh_request req, u32 data1, u32 data2, u32 data3)
141{
142 int r;
143 uint8_t trn;
144
145 /* IMPORTANT:
146 * clear TRN_MSG_VALID valid to clear host's RCV_MSG_ACK
147 * and with host's RCV_MSG_ACK cleared hw automatically clear host's RCV_MSG_ACK
148 * which lead to VF's TRN_MSG_ACK cleared, otherwise below xgpu_nv_poll_ack()
149 * will return immediatly
150 */
151 do {
152 xgpu_nv_mailbox_set_valid(adev, false);
153 trn = xgpu_nv_peek_ack(adev);
154 if (trn) {
155 dev_err_ratelimited(adev->dev, "trn=%x ACK should not assert! wait again !\n", trn);
156 msleep(1);
157 }
158 } while (trn);
159
160 dev_dbg(adev->dev, "trans_msg req = 0x%x, data1 = 0x%x\n", req, data1);
161 WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0, req);
162 WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW1, data1);
163 WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW2, data2);
164 WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW3, data3);
165 xgpu_nv_mailbox_set_valid(adev, true);
166
167 /* start to poll ack */
168 r = xgpu_nv_poll_ack(adev);
169 if (r)
170 dev_err(adev->dev, "Doesn't get ack from pf, continue\n");
171
172 xgpu_nv_mailbox_set_valid(adev, false);
173}
174
175static int xgpu_nv_send_access_requests_with_param(struct amdgpu_device *adev,
176 enum idh_request req, u32 data1, u32 data2, u32 data3)
177{
178 struct amdgpu_virt *virt = &adev->virt;
179 int r = 0, retry = 1;
180 enum idh_event event = -1;
181
182 mutex_lock(&virt->access_req_mutex);
183send_request:
184
185 if (amdgpu_ras_is_rma(adev)) {
186 r = -ENODEV;
187 goto out;
188 }
189
190 xgpu_nv_mailbox_trans_msg(adev, req, data1, data2, data3);
191
192 switch (req) {
193 case IDH_REQ_GPU_INIT_ACCESS:
194 case IDH_REQ_GPU_FINI_ACCESS:
195 case IDH_REQ_GPU_RESET_ACCESS:
196 event = IDH_READY_TO_ACCESS_GPU;
197 break;
198 case IDH_REQ_GPU_INIT_DATA:
199 event = IDH_REQ_GPU_INIT_DATA_READY;
200 break;
201 case IDH_RAS_POISON:
202 if (data1 != 0)
203 event = IDH_RAS_POISON_READY;
204 break;
205 case IDH_REQ_RAS_ERROR_COUNT:
206 event = IDH_RAS_ERROR_COUNT_READY;
207 break;
208 case IDH_REQ_RAS_CPER_DUMP:
209 event = IDH_RAS_CPER_DUMP_READY;
210 break;
211 case IDH_REQ_RAS_CHK_CRITI:
212 event = IDH_REQ_RAS_CHK_CRITI_READY;
213 break;
214 case IDH_REQ_RAS_REMOTE_CMD:
215 event = IDH_REQ_RAS_REMOTE_CMD_READY;
216 break;
217 case IDH_REQ_PTL_UPDATE:
218 event = IDH_PTL_UPDATE_READY;
219 break;
220 default:
221 break;
222 }
223
224 if (event != -1) {
225 r = xgpu_nv_poll_msg(adev, event);
226 if (r) {
227 if (retry++ < 5)
228 goto send_request;
229
230 if (req != IDH_REQ_GPU_INIT_DATA) {
231 dev_err(adev->dev, "Doesn't get msg:%d from pf, error=%d\n", event, r);
232 goto out;
233 } else /* host doesn't support REQ_GPU_INIT_DATA handshake */
234 adev->virt.req_init_data_ver = 0;
235 } else {
236 if (req == IDH_REQ_GPU_INIT_DATA) {
237 switch (RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW1)) {
238 case GPU_CRIT_REGION_V2:
239 adev->virt.req_init_data_ver = GPU_CRIT_REGION_V2;
240 adev->virt.init_data_header.offset =
241 RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW2);
242 adev->virt.init_data_header.size_kb =
243 RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW3);
244 break;
245 default:
246 adev->virt.req_init_data_ver = GPU_CRIT_REGION_V1;
247 adev->virt.init_data_header.offset = -1;
248 adev->virt.init_data_header.size_kb = 0;
249 break;
250 }
251 }
252 }
253
254 /* Retrieve checksum from mailbox2 */
255 if (req == IDH_REQ_GPU_INIT_ACCESS || req == IDH_REQ_GPU_RESET_ACCESS) {
256 adev->virt.fw_reserve.checksum_key =
257 RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW2);
258 }
259
260 /* Retrieve PTL response from mailbox */
261 if (req == IDH_REQ_PTL_UPDATE) {
262 u32 dw1 = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW1);
263 u32 dw2 = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW2);
264 u32 status = AMD_SRIOV_PTL_UNPACK_STATUS(dw1);
265
266 if (status == AMD_SRIOV_RESP_UNSUPPORTED) {
267 r = -EOPNOTSUPP;
268 } else if (status == AMD_SRIOV_RESP_FAIL) {
269 r = -EIO;
270 } else {
271 adev->virt.ptl_state = AMD_SRIOV_PTL_UNPACK_STATE(dw1);
272 adev->virt.ptl_pref_format1 = AMD_SRIOV_PTL_UNPACK_FMT1(dw2);
273 adev->virt.ptl_pref_format2 = AMD_SRIOV_PTL_UNPACK_FMT2(dw2);
274 }
275 }
276 }
277
278out:
279 mutex_unlock(&virt->access_req_mutex);
280
281 return r;
282}
283
284static int xgpu_nv_send_access_requests(struct amdgpu_device *adev,
285 enum idh_request req)
286{
287 return xgpu_nv_send_access_requests_with_param(adev,
288 req, 0, 0, 0);
289}
290
291static int xgpu_nv_request_reset(struct amdgpu_device *adev)
292{
293 int ret, i = 0;
294
295 while (i < NV_MAILBOX_POLL_MSG_REP_MAX) {
296 ret = xgpu_nv_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS);
297 if (!ret)
298 break;
299 i++;
300 }
301
302 return ret;
303}
304
305static int xgpu_nv_request_full_gpu_access(struct amdgpu_device *adev,
306 bool init)
307{
308 enum idh_request req;
309
310 req = init ? IDH_REQ_GPU_INIT_ACCESS : IDH_REQ_GPU_FINI_ACCESS;
311 return xgpu_nv_send_access_requests(adev, req);
312}
313
314static int xgpu_nv_release_full_gpu_access(struct amdgpu_device *adev,
315 bool init)
316{
317 enum idh_request req;
318 int r = 0;
319
320 req = init ? IDH_REL_GPU_INIT_ACCESS : IDH_REL_GPU_FINI_ACCESS;
321 r = xgpu_nv_send_access_requests(adev, req);
322
323 return r;
324}
325
326static int xgpu_nv_request_init_data(struct amdgpu_device *adev)
327{
328 return xgpu_nv_send_access_requests_with_param(adev, IDH_REQ_GPU_INIT_DATA,
329 0, GPU_CRIT_REGION_V2, 0);
330}
331
332static int xgpu_nv_mailbox_ack_irq(struct amdgpu_device *adev,
333 struct amdgpu_irq_src *source,
334 struct amdgpu_iv_entry *entry)
335{
336 dev_dbg(adev->dev, "get ack intr and do nothing.\n");
337 return 0;
338}
339
340static int xgpu_nv_set_mailbox_ack_irq(struct amdgpu_device *adev,
341 struct amdgpu_irq_src *source,
342 unsigned type,
343 enum amdgpu_interrupt_state state)
344{
345 u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);
346
347 if (state == AMDGPU_IRQ_STATE_ENABLE)
348 tmp |= 2;
349 else
350 tmp &= ~2;
351
352 WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp);
353
354 return 0;
355}
356
357static void xgpu_nv_ready_to_reset(struct amdgpu_device *adev)
358{
359 xgpu_nv_mailbox_trans_msg(adev, IDH_READY_TO_RESET, 0, 0, 0);
360}
361
362static int xgpu_nv_wait_reset(struct amdgpu_device *adev)
363{
364 int timeout = NV_MAILBOX_POLL_FLR_TIMEDOUT;
365 do {
366 if (xgpu_nv_mailbox_peek_msg(adev) == IDH_FLR_NOTIFICATION_CMPL) {
367 dev_dbg(adev->dev, "Got NV IDH_FLR_NOTIFICATION_CMPL after %d ms\n", NV_MAILBOX_POLL_FLR_TIMEDOUT - timeout);
368 return 0;
369 }
370 msleep(10);
371 timeout -= 10;
372 } while (timeout > 1);
373
374 dev_dbg(adev->dev, "waiting NV IDH_FLR_NOTIFICATION_CMPL timeout\n");
375 return -ETIME;
376}
377
378static void xgpu_nv_mailbox_flr_work(struct work_struct *work)
379{
380 struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, flr_work);
381 struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt);
382 struct amdgpu_reset_context reset_context = { 0 };
383
384 amdgpu_virt_fini_data_exchange(adev);
385
386 /* Trigger recovery for world switch failure if no TDR */
387 if (amdgpu_device_should_recover_gpu(adev)
388 && (!amdgpu_device_has_job_running(adev) ||
389 adev->sdma_timeout == MAX_SCHEDULE_TIMEOUT ||
390 adev->gfx_timeout == MAX_SCHEDULE_TIMEOUT ||
391 adev->compute_timeout == MAX_SCHEDULE_TIMEOUT ||
392 adev->video_timeout == MAX_SCHEDULE_TIMEOUT)) {
393
394 reset_context.method = AMD_RESET_METHOD_NONE;
395 reset_context.reset_req_dev = adev;
396 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
397 set_bit(AMDGPU_HOST_FLR, &reset_context.flags);
398
399 amdgpu_device_gpu_recover(adev, NULL, &reset_context);
400 }
401}
402
403static void xgpu_nv_mailbox_req_bad_pages_work(struct work_struct *work)
404{
405 struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, req_bad_pages_work);
406 struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt);
407
408 if (down_read_trylock(&adev->reset_domain->sem)) {
409 amdgpu_virt_fini_data_exchange(adev);
410 amdgpu_virt_request_bad_pages(adev);
411 up_read(&adev->reset_domain->sem);
412 }
413}
414
415/**
416 * xgpu_nv_mailbox_handle_bad_pages_work - Reinitialize the data exchange region to get fresh bad page information
417 * @work: pointer to the work_struct
418 *
419 * This work handler is triggered when bad pages are ready, and it reinitializes
420 * the data exchange region to retrieve updated bad page information from the host.
421 */
422static void xgpu_nv_mailbox_handle_bad_pages_work(struct work_struct *work)
423{
424 struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, handle_bad_pages_work);
425 struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt);
426
427 if (down_read_trylock(&adev->reset_domain->sem)) {
428 amdgpu_virt_fini_data_exchange(adev);
429 amdgpu_virt_init_data_exchange(adev);
430 up_read(&adev->reset_domain->sem);
431 }
432}
433
434static int xgpu_nv_set_mailbox_rcv_irq(struct amdgpu_device *adev,
435 struct amdgpu_irq_src *src,
436 unsigned type,
437 enum amdgpu_interrupt_state state)
438{
439 u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);
440
441 if (state == AMDGPU_IRQ_STATE_ENABLE)
442 tmp |= 1;
443 else
444 tmp &= ~1;
445
446 WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp);
447
448 return 0;
449}
450
451static int xgpu_nv_mailbox_rcv_irq(struct amdgpu_device *adev,
452 struct amdgpu_irq_src *source,
453 struct amdgpu_iv_entry *entry)
454{
455 enum idh_event event = xgpu_nv_mailbox_peek_msg(adev);
456 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
457
458 switch (event) {
459 case IDH_RAS_BAD_PAGES_READY:
460 xgpu_nv_mailbox_send_ack(adev);
461 if (amdgpu_sriov_runtime(adev))
462 schedule_work(&adev->virt.handle_bad_pages_work);
463 break;
464 case IDH_RAS_BAD_PAGES_NOTIFICATION:
465 xgpu_nv_mailbox_send_ack(adev);
466 if (amdgpu_sriov_runtime(adev))
467 schedule_work(&adev->virt.req_bad_pages_work);
468 break;
469 case IDH_UNRECOV_ERR_NOTIFICATION:
470 xgpu_nv_mailbox_send_ack(adev);
471 if (!amdgpu_ras_is_rma(adev)) {
472 ras->is_rma = true;
473 dev_err(adev->dev, "VF is in an unrecoverable state. Runtime Services are halted.\n");
474 }
475
476 if (amdgpu_sriov_runtime(adev))
477 WARN_ONCE(!amdgpu_reset_domain_schedule(adev->reset_domain,
478 &adev->virt.flr_work),
479 "Failed to queue work! at %s",
480 __func__);
481 break;
482 case IDH_FLR_NOTIFICATION:
483 if (amdgpu_sriov_runtime(adev))
484 WARN_ONCE(!amdgpu_reset_domain_schedule(adev->reset_domain,
485 &adev->virt.flr_work),
486 "Failed to queue work! at %s",
487 __func__);
488 break;
489 /* READY_TO_ACCESS_GPU is fetched by kernel polling, IRQ can ignore
490 * it byfar since that polling thread will handle it,
491 * other msg like flr complete is not handled here.
492 */
493 case IDH_CLR_MSG_BUF:
494 case IDH_FLR_NOTIFICATION_CMPL:
495 case IDH_READY_TO_ACCESS_GPU:
496 default:
497 break;
498 }
499
500 return 0;
501}
502
503static const struct amdgpu_irq_src_funcs xgpu_nv_mailbox_ack_irq_funcs = {
504 .set = xgpu_nv_set_mailbox_ack_irq,
505 .process = xgpu_nv_mailbox_ack_irq,
506};
507
508static const struct amdgpu_irq_src_funcs xgpu_nv_mailbox_rcv_irq_funcs = {
509 .set = xgpu_nv_set_mailbox_rcv_irq,
510 .process = xgpu_nv_mailbox_rcv_irq,
511};
512
513void xgpu_nv_mailbox_set_irq_funcs(struct amdgpu_device *adev)
514{
515 adev->virt.ack_irq.num_types = 1;
516 adev->virt.ack_irq.funcs = &xgpu_nv_mailbox_ack_irq_funcs;
517 adev->virt.rcv_irq.num_types = 1;
518 adev->virt.rcv_irq.funcs = &xgpu_nv_mailbox_rcv_irq_funcs;
519}
520
521int xgpu_nv_mailbox_add_irq_id(struct amdgpu_device *adev)
522{
523 int r;
524
525 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 135, &adev->virt.rcv_irq);
526 if (r)
527 return r;
528
529 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 138, &adev->virt.ack_irq);
530 if (r) {
531 amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
532 return r;
533 }
534
535 return 0;
536}
537
538int xgpu_nv_mailbox_get_irq(struct amdgpu_device *adev)
539{
540 int r;
541
542 r = amdgpu_irq_get(adev, &adev->virt.rcv_irq, 0);
543 if (r)
544 return r;
545 r = amdgpu_irq_get(adev, &adev->virt.ack_irq, 0);
546 if (r) {
547 amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
548 return r;
549 }
550
551 INIT_WORK(&adev->virt.flr_work, xgpu_nv_mailbox_flr_work);
552 INIT_WORK(&adev->virt.req_bad_pages_work, xgpu_nv_mailbox_req_bad_pages_work);
553 INIT_WORK(&adev->virt.handle_bad_pages_work, xgpu_nv_mailbox_handle_bad_pages_work);
554
555 return 0;
556}
557
558void xgpu_nv_mailbox_put_irq(struct amdgpu_device *adev)
559{
560 amdgpu_irq_put(adev, &adev->virt.ack_irq, 0);
561 amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
562}
563
564static void xgpu_nv_ras_poison_handler(struct amdgpu_device *adev,
565 enum amdgpu_ras_block block)
566{
567 if (amdgpu_ip_version(adev, UMC_HWIP, 0) < IP_VERSION(12, 0, 0)) {
568 xgpu_nv_send_access_requests(adev, IDH_RAS_POISON);
569 } else {
570 amdgpu_virt_fini_data_exchange(adev);
571 xgpu_nv_send_access_requests_with_param(adev,
572 IDH_RAS_POISON, block, 0, 0);
573 }
574}
575
576static bool xgpu_nv_rcvd_ras_intr(struct amdgpu_device *adev)
577{
578 enum idh_event msg = xgpu_nv_mailbox_peek_msg(adev);
579
580 return (msg == IDH_RAS_ERROR_DETECTED || msg == 0xFFFFFFFF);
581}
582
583static int xgpu_nv_req_ras_err_count(struct amdgpu_device *adev)
584{
585 return xgpu_nv_send_access_requests(adev, IDH_REQ_RAS_ERROR_COUNT);
586}
587
588static int xgpu_nv_req_ras_cper_dump(struct amdgpu_device *adev, u64 vf_rptr)
589{
590 uint32_t vf_rptr_hi, vf_rptr_lo;
591
592 vf_rptr_hi = (uint32_t)(vf_rptr >> 32);
593 vf_rptr_lo = (uint32_t)(vf_rptr & 0xFFFFFFFF);
594 return xgpu_nv_send_access_requests_with_param(
595 adev, IDH_REQ_RAS_CPER_DUMP, vf_rptr_hi, vf_rptr_lo, 0);
596}
597
598static int xgpu_nv_req_ras_bad_pages(struct amdgpu_device *adev)
599{
600 return xgpu_nv_send_access_requests(adev, IDH_REQ_RAS_BAD_PAGES);
601}
602
603static int xgpu_nv_check_vf_critical_region(struct amdgpu_device *adev, u64 addr)
604{
605 uint32_t addr_hi, addr_lo;
606
607 addr_hi = (uint32_t)(addr >> 32);
608 addr_lo = (uint32_t)(addr & 0xFFFFFFFF);
609 return xgpu_nv_send_access_requests_with_param(
610 adev, IDH_REQ_RAS_CHK_CRITI, addr_hi, addr_lo, 0);
611}
612
613static int xgpu_nv_req_remote_ras_cmd(struct amdgpu_device *adev,
614 u32 param1, u32 param2, u32 param3)
615{
616 return xgpu_nv_send_access_requests_with_param(
617 adev, IDH_REQ_RAS_REMOTE_CMD, param1, param2, param3);
618}
619
620static int xgpu_nv_req_ptl_update(struct amdgpu_device *adev,
621 u32 req_code, u32 ptl_state, u32 fmt1, u32 fmt2)
622{
623 return xgpu_nv_send_access_requests_with_param(adev, IDH_REQ_PTL_UPDATE,
624 req_code, ptl_state, AMD_SRIOV_PTL_PACK_FORMATS(fmt1, fmt2));
625}
626
627const struct amdgpu_virt_ops xgpu_nv_virt_ops = {
628 .req_full_gpu = xgpu_nv_request_full_gpu_access,
629 .rel_full_gpu = xgpu_nv_release_full_gpu_access,
630 .req_init_data = xgpu_nv_request_init_data,
631 .reset_gpu = xgpu_nv_request_reset,
632 .ready_to_reset = xgpu_nv_ready_to_reset,
633 .wait_reset = xgpu_nv_wait_reset,
634 .trans_msg = xgpu_nv_mailbox_trans_msg,
635 .ras_poison_handler = xgpu_nv_ras_poison_handler,
636 .rcvd_ras_intr = xgpu_nv_rcvd_ras_intr,
637 .req_ras_err_count = xgpu_nv_req_ras_err_count,
638 .req_ras_cper_dump = xgpu_nv_req_ras_cper_dump,
639 .req_bad_pages = xgpu_nv_req_ras_bad_pages,
640 .req_ras_chk_criti = xgpu_nv_check_vf_critical_region,
641 .req_remote_ras_cmd = xgpu_nv_req_remote_ras_cmd,
642 .req_ptl_update = xgpu_nv_req_ptl_update,
643};