| 1 | |
| 2 | * Copyright 2014 Advanced Micro Devices, Inc.
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| 3 | *
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a
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| 5 | * copy of this software and associated documentation files (the "Software"),
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| 6 | * to deal in the Software without restriction, including without limitation
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the
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| 9 | * Software is furnished to do so, subject to the following conditions:
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| 10 | *
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| 11 | * The above copyright notice and this permission notice shall be included in
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| 12 | * all copies or substantial portions of the Software.
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| 13 | *
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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| 20 | * OTHER DEALINGS IN THE SOFTWARE.
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| 21 | *
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| 22 |
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| 23 |
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| 24 | #ifndef __MXGPU_NV_H__
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| 25 | #define __MXGPU_NV_H__
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| 26 |
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| 27 | #define NV_MAILBOX_POLL_ACK_TIMEDOUT 500
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| 28 | #define NV_MAILBOX_POLL_MSG_TIMEDOUT 15000
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| 29 | #define NV_MAILBOX_POLL_FLR_TIMEDOUT 10000
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| 30 | #define NV_MAILBOX_POLL_MSG_REP_MAX 11
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| 31 |
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| 32 | enum idh_request {
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| 33 | IDH_REQ_GPU_INIT_ACCESS = 1,
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| 34 | IDH_REL_GPU_INIT_ACCESS,
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| 35 | IDH_REQ_GPU_FINI_ACCESS,
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| 36 | IDH_REL_GPU_FINI_ACCESS,
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| 37 | IDH_REQ_GPU_RESET_ACCESS,
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| 38 | IDH_REQ_GPU_INIT_DATA,
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| 39 |
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| 40 | IDH_LOG_VF_ERROR = 200,
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| 41 | IDH_READY_TO_RESET = 201,
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| 42 | IDH_RAS_POISON = 202,
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| 43 | IDH_REQ_RAS_ERROR_COUNT = 203,
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| 44 | IDH_REQ_RAS_CPER_DUMP = 204,
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| 45 | IDH_REQ_RAS_BAD_PAGES = 205,
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| 46 | IDH_REQ_RAS_CHK_CRITI = 206,
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| 47 | IDH_REQ_RAS_REMOTE_CMD = 207,
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| 48 | IDH_REQ_PTL_UPDATE = 208
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| 49 | };
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| 50 |
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| 51 | enum idh_event {
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| 52 | IDH_CLR_MSG_BUF = 0,
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| 53 | IDH_READY_TO_ACCESS_GPU,
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| 54 | IDH_FLR_NOTIFICATION,
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| 55 | IDH_FLR_NOTIFICATION_CMPL,
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| 56 | IDH_SUCCESS,
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| 57 | IDH_FAIL,
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| 58 | IDH_QUERY_ALIVE,
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| 59 | IDH_REQ_GPU_INIT_DATA_READY,
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| 60 | IDH_RAS_POISON_READY,
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| 61 | IDH_PF_SOFT_FLR_NOTIFICATION,
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| 62 | IDH_RAS_ERROR_DETECTED,
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| 63 | IDH_RAS_ERROR_COUNT_READY = 11,
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| 64 | IDH_RAS_CPER_DUMP_READY = 14,
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| 65 | IDH_RAS_BAD_PAGES_READY = 15,
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| 66 | IDH_RAS_BAD_PAGES_NOTIFICATION = 16,
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| 67 | IDH_UNRECOV_ERR_NOTIFICATION = 17,
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| 68 | IDH_REQ_RAS_CHK_CRITI_READY = 18,
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| 69 | IDH_REQ_RAS_REMOTE_CMD_READY = 19,
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| 70 | IDH_PTL_UPDATE_READY = 20,
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| 71 |
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| 72 | IDH_TEXT_MESSAGE = 255,
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| 73 | };
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| 74 |
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| 75 | extern const struct amdgpu_virt_ops xgpu_nv_virt_ops;
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| 76 |
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| 77 | void xgpu_nv_mailbox_set_irq_funcs(struct amdgpu_device *adev);
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| 78 | int xgpu_nv_mailbox_add_irq_id(struct amdgpu_device *adev);
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| 79 | int xgpu_nv_mailbox_get_irq(struct amdgpu_device *adev);
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| 80 | void xgpu_nv_mailbox_put_irq(struct amdgpu_device *adev);
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| 81 |
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| 82 | #define mmMAILBOX_CONTROL 0xE5E
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| 83 |
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| 84 | #define NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE (mmMAILBOX_CONTROL * 4)
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| 85 | #define NV_MAIBOX_CONTROL_RCV_OFFSET_BYTE (NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE + 1)
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| 86 |
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| 87 | #define mmMAILBOX_MSGBUF_TRN_DW0 0xE56
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| 88 | #define mmMAILBOX_MSGBUF_TRN_DW1 0xE57
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| 89 | #define mmMAILBOX_MSGBUF_TRN_DW2 0xE58
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| 90 | #define mmMAILBOX_MSGBUF_TRN_DW3 0xE59
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| 91 |
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| 92 | #define mmMAILBOX_MSGBUF_RCV_DW0 0xE5A
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| 93 | #define mmMAILBOX_MSGBUF_RCV_DW1 0xE5B
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| 94 | #define mmMAILBOX_MSGBUF_RCV_DW2 0xE5C
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| 95 | #define mmMAILBOX_MSGBUF_RCV_DW3 0xE5D
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| 96 |
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| 97 | #define mmMAILBOX_INT_CNTL 0xE5F
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| 98 |
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| 99 | #endif
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